Commit | Line | Data |
---|---|---|
1595d96b VM |
1 | Submitted By: Jim Gifford (jim at cross-lfs dot org) |
2 | Date: 07-07-2009 | |
3 | Initial Package Version: 2.19.1 | |
4 | Origin: Upstream | |
5 | Upstream Status: Applied | |
6 | Description: This is a branch update for binutils-2.19.1, and should be | |
7 | rechecked periodically. | |
8 | ||
9 | This patch was created on 20090707 | |
10 | ||
11 | diff -Naur binutils-2.19.1.orig/bfd/ChangeLog binutils-2.19.1/bfd/ChangeLog | |
12 | --- binutils-2.19.1.orig/bfd/ChangeLog 2009-02-02 02:44:39.000000000 -0800 | |
13 | +++ binutils-2.19.1/bfd/ChangeLog 2009-03-02 05:55:19.000000000 -0800 | |
14 | @@ -1,3 +1,108 @@ | |
15 | +2009-03-02 Alan Modra <amodra@bigpond.net.au> | |
16 | + | |
17 | + 2009-02-15 Alan Modra <amodra@bigpond.net.au> | |
18 | + * elf64-ppc.c (struct _ppc64_elf_section_data): Delete t_symndx, | |
19 | + add toc.symndx and toc.add. | |
20 | + (ppc64_elf_check_relocs): Don't set htab->tls_get_addr here. | |
21 | + Set up toc.add. | |
22 | + (get_tls_mask): Add toc_addend param, set from toc.add. Adjust all | |
23 | + callers. | |
24 | + (ppc64_elf_tls_setup): Set htab->tls_get_addr and tls_get_addr_fd. | |
25 | + (branch_reloc_hash_match): New function, extracted from.. | |
26 | + (ppc64_elf_tls_optimize): ..here. | |
27 | + (ppc64_elf_relocate_section): Properly set addends when optimizing | |
28 | + tls sequences. Avoid unnecessary reading and writing of insns. | |
29 | + Only redo reloc when symbol changed. Bypass symbol checks when | |
30 | + using tlsld_got. | |
31 | + * elf32-ppc.c (ppc_elf_tls_setup): Correct comment. | |
32 | + (branch_reloc_hash_match): New function, extracted from.. | |
33 | + (ppc_elf_tls_optimize): ..here. | |
34 | + (ppc_elf_relocate_section): Avoid unnecessary reading of insns. | |
35 | + Don't clear addend on zapped __tls_get_addr reloc. | |
36 | + | |
37 | + 2009-02-01 Jan Kratochvil <jan.kratochvil@redhat.com> | |
38 | + * elf-eh-frame.c (REQUIRE_CLEARED_RELOCS) Remove. | |
39 | + (_bfd_elf_parse_eh_frame): Do not check relocations for removed FDEs. | |
40 | + | |
41 | + 2009-01-26 Nathan Sidwell <nathan@codesourcery.com> | |
42 | + * elf32-ppc.c (ppc_elf_relax_section): Add space for relocs | |
43 | + describing the trampolines. | |
44 | + (ppc_elf_relocate_section): Update relocs to describe the | |
45 | + trampolines. | |
46 | + | |
47 | + 2009-01-22 Alan Modra <amodra@bigpond.net.au> | |
48 | + PR 6832 | |
49 | + * dwarf2.c (find_line): Don't update stash->sec_info_ptr until | |
50 | + after comp_unit_find_line call. | |
51 | + | |
52 | + 2009-01-14 Alan Modra <amodra@bigpond.net.au> | |
53 | + PR 9735 | |
54 | + * syms.c (_bfd_stab_section_find_nearest_line): Don't free | |
55 | + saved filename, use bfd_alloc rather than bfd_malloc for it. | |
56 | + | |
57 | + 2009-01-11 Jan Kratochvil <jan.kratochvil@redhat.com> | |
58 | + * elflink.c (_bfd_elf_section_already_linked): Handle g++-3.4 | |
59 | + relocations in `.gnu.linkonce.r.*' referencing its `.gnu.linkonce.t.*'. | |
60 | + | |
61 | + 2008-12-11 Alan Modra <amodra@bigpond.net.au> | |
62 | + PR 7041 | |
63 | + * elf64-ppc.c (func_desc_adjust): Correct logic making fake function | |
64 | + descriptors. Similarly correct making function descriptors dynamic. | |
65 | + | |
66 | + 2008-11-14 Nathan Sidwell <nathan@codesourcery.com> | |
67 | + * elf.c (assign_file_positions_for_load_sections): Use header_size | |
68 | + to avoid moving the load address of file headers. | |
69 | + (assign_file_positions_for_load_sections): Set header_size for | |
70 | + segments containing the file header. | |
71 | + | |
72 | + 2008-11-13 Hans-Peter Nilsson <hp@axis.com> | |
73 | + PR ld/7028 | |
74 | + * elf.c (assign_file_positions_for_load_sections): Allocate phrds | |
75 | + with bfd_zalloc2 instead of bfd_alloc2. For the amount, use | |
76 | + the possibly-preset header-size, not the computed one. | |
77 | + | |
78 | + 2008-11-13 Alan Modra <amodra@bigpond.net.au> | |
79 | + PR 7023 | |
80 | + * elf.c (bfd_section_from_shdr <SHT_SYMTAB>): Fail on invalid sh_info. | |
81 | + | |
82 | + 2008-11-11 Alan Modra <amodra@bigpond.net.au> | |
83 | + PR 7012 | |
84 | + * dwarf2.c (find_line): Don't keep stale pointers into realloc'd | |
85 | + memory. Return on errors. Fix memory leak. | |
86 | + (_bfd_dwarf2_cleanup_debug_info): Free dwarf_str_buffer. | |
87 | + | |
88 | + 2008-10-10 Nathan Froyd <froydnj@codesourcery.com> | |
89 | + * elf32-ppc.c (ppc_elf_merge_obj_attributes): Merge | |
90 | + Tag_GNU_Power_ABI_Struct_Return. | |
91 | + | |
92 | + 2008-10-03 Alan Modra <amodra@bigpond.net.au> | |
93 | + * elf.c (bfd_elf_set_group_contents): Assign sh_info for ld -r when | |
94 | + the signature symbol is global. | |
95 | + * elflink.c (elf_link_input_bfd): Ensure group signature symbol | |
96 | + is output when ld -r. Set group sh_info when local. | |
97 | + * linker.c (default_indirect_link_order): Handle group sections | |
98 | + specially. | |
99 | + | |
100 | + 2008-09-28 Alan Modra <amodra@bigpond.net.au> | |
101 | + * elf.c (_bfd_elf_init_private_section_data): Tweak union copy. | |
102 | + (bfd_section_from_shdr): Don't change SHT_GROUP section name. | |
103 | + * elflink.c (section_signature): New function. | |
104 | + (_bfd_elf_section_already_linked): Use it. | |
105 | + | |
106 | +2009-02-15 Bjoern Haase <bjoern.m.haase@web.de> | |
107 | + | |
108 | + PR 9841 | |
109 | + * elf32-avr.c: Handle case where no local symbos exist correctly. | |
110 | + | |
111 | +2009-02-04 Eric B. Weddington <eric.weddington@atmel.com> | |
112 | + | |
113 | + * elf32-avr.c (avr_final_link_relocate): Allow avr25 to wraparound. | |
114 | + | |
115 | +2009-02-03 Tristan Gingold <gingold@adacore.com> | |
116 | + | |
117 | + * Makefile.am (RELEASE): Unset. | |
118 | + * Makefile.in: Regenerated. | |
119 | + | |
120 | 2009-02-02 Tristan Gingold <gingold@adacore.com> | |
121 | ||
122 | * configure.in: Bump version to 2.19.1 | |
123 | diff -Naur binutils-2.19.1.orig/bfd/dwarf2.c binutils-2.19.1/bfd/dwarf2.c | |
124 | --- binutils-2.19.1.orig/bfd/dwarf2.c 2008-10-02 01:07:16.000000000 -0700 | |
125 | +++ binutils-2.19.1/bfd/dwarf2.c 2009-03-02 05:50:55.000000000 -0800 | |
126 | @@ -1,6 +1,6 @@ | |
127 | /* DWARF 2 support. | |
128 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, | |
129 | - 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. | |
130 | + 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. | |
131 | ||
132 | Adapted from gdb/dwarf2read.c by Gavin Koch of Cygnus Solutions | |
133 | (gavin@cygnus.com). | |
134 | @@ -2989,8 +2989,6 @@ | |
135 | symbols, 0, | |
136 | &stash->info_ptr_memory, &total_size)) | |
137 | goto done; | |
138 | - stash->info_ptr = stash->info_ptr_memory; | |
139 | - stash->info_ptr_end = stash->info_ptr + total_size; | |
140 | } | |
141 | else | |
142 | { | |
143 | @@ -3008,63 +3006,64 @@ | |
144 | if (stash->info_ptr_memory == NULL) | |
145 | goto done; | |
146 | ||
147 | - stash->info_ptr = stash->info_ptr_memory; | |
148 | - stash->info_ptr_end = stash->info_ptr; | |
149 | - | |
150 | + total_size = 0; | |
151 | for (msec = find_debug_info (debug_bfd, NULL); | |
152 | msec; | |
153 | msec = find_debug_info (debug_bfd, msec)) | |
154 | { | |
155 | bfd_size_type size; | |
156 | - bfd_size_type start; | |
157 | ||
158 | size = msec->size; | |
159 | if (size == 0) | |
160 | continue; | |
161 | ||
162 | - start = stash->info_ptr_end - stash->info_ptr; | |
163 | - | |
164 | - if ((bfd_simple_get_relocated_section_contents | |
165 | - (debug_bfd, msec, stash->info_ptr + start, symbols)) | |
166 | - == NULL) | |
167 | - continue; | |
168 | + if (!(bfd_simple_get_relocated_section_contents | |
169 | + (debug_bfd, msec, stash->info_ptr_memory + total_size, | |
170 | + symbols))) | |
171 | + goto done; | |
172 | ||
173 | - stash->info_ptr_end = stash->info_ptr + start + size; | |
174 | + total_size += size; | |
175 | } | |
176 | - | |
177 | - BFD_ASSERT (stash->info_ptr_end == stash->info_ptr + total_size); | |
178 | } | |
179 | else | |
180 | { | |
181 | /* Case 3: multiple sections, some or all compressed. */ | |
182 | - stash->info_ptr_memory = bfd_malloc (1); | |
183 | - stash->info_ptr = stash->info_ptr_memory; | |
184 | - stash->info_ptr_end = stash->info_ptr; | |
185 | + stash->info_ptr_memory = NULL; | |
186 | + total_size = 0; | |
187 | for (msec = find_debug_info (debug_bfd, NULL); | |
188 | msec; | |
189 | msec = find_debug_info (debug_bfd, msec)) | |
190 | { | |
191 | bfd_size_type size = msec->size; | |
192 | - bfd_byte* buffer | |
193 | - = (bfd_simple_get_relocated_section_contents | |
194 | - (debug_bfd, msec, NULL, symbols)); | |
195 | - if (! buffer) | |
196 | + bfd_byte* buffer; | |
197 | + | |
198 | + if (size == 0) | |
199 | continue; | |
200 | + | |
201 | + buffer = (bfd_simple_get_relocated_section_contents | |
202 | + (debug_bfd, msec, NULL, symbols)); | |
203 | + if (! buffer) | |
204 | + goto done; | |
205 | + | |
206 | if (strcmp (msec->name, DWARF2_COMPRESSED_DEBUG_INFO) == 0) | |
207 | { | |
208 | if (! bfd_uncompress_section_contents (&buffer, &size)) | |
209 | - continue; | |
210 | + { | |
211 | + free (buffer); | |
212 | + goto done; | |
213 | + } | |
214 | } | |
215 | - stash->info_ptr = bfd_realloc (stash->info_ptr, | |
216 | - stash->info_ptr_end | |
217 | - - stash->info_ptr + size); | |
218 | - memcpy (stash->info_ptr_end, buffer, size); | |
219 | + stash->info_ptr_memory = bfd_realloc (stash->info_ptr_memory, | |
220 | + total_size + size); | |
221 | + memcpy (stash->info_ptr_memory + total_size, buffer, size); | |
222 | free (buffer); | |
223 | - stash->info_ptr_end += size; | |
224 | + total_size += size; | |
225 | } | |
226 | } | |
227 | } | |
228 | ||
229 | + stash->info_ptr = stash->info_ptr_memory; | |
230 | + stash->info_ptr_end = stash->info_ptr + total_size; | |
231 | stash->sec = find_debug_info (debug_bfd, NULL); | |
232 | stash->sec_info_ptr = stash->info_ptr; | |
233 | stash->syms = symbols; | |
234 | @@ -3187,13 +3186,6 @@ | |
235 | break; | |
236 | stash->info_ptr += length; | |
237 | ||
238 | - if ((bfd_vma) (stash->info_ptr - stash->sec_info_ptr) | |
239 | - == stash->sec->size) | |
240 | - { | |
241 | - stash->sec = find_debug_info (stash->bfd, stash->sec); | |
242 | - stash->sec_info_ptr = stash->info_ptr; | |
243 | - } | |
244 | - | |
245 | if (stash->all_comp_units) | |
246 | stash->all_comp_units->prev_unit = each; | |
247 | else | |
248 | @@ -3223,6 +3215,14 @@ | |
249 | functionname_ptr, | |
250 | linenumber_ptr, | |
251 | stash)); | |
252 | + | |
253 | + if ((bfd_vma) (stash->info_ptr - stash->sec_info_ptr) | |
254 | + == stash->sec->size) | |
255 | + { | |
256 | + stash->sec = find_debug_info (stash->bfd, stash->sec); | |
257 | + stash->sec_info_ptr = stash->info_ptr; | |
258 | + } | |
259 | + | |
260 | if (found) | |
261 | goto done; | |
262 | } | |
263 | @@ -3364,8 +3364,14 @@ | |
264 | } | |
265 | } | |
266 | ||
267 | - free (stash->dwarf_abbrev_buffer); | |
268 | - free (stash->dwarf_line_buffer); | |
269 | - free (stash->dwarf_ranges_buffer); | |
270 | - free (stash->info_ptr_memory); | |
271 | + if (stash->dwarf_abbrev_buffer) | |
272 | + free (stash->dwarf_abbrev_buffer); | |
273 | + if (stash->dwarf_line_buffer) | |
274 | + free (stash->dwarf_line_buffer); | |
275 | + if (stash->dwarf_str_buffer) | |
276 | + free (stash->dwarf_str_buffer); | |
277 | + if (stash->dwarf_ranges_buffer) | |
278 | + free (stash->dwarf_ranges_buffer); | |
279 | + if (stash->info_ptr_memory) | |
280 | + free (stash->info_ptr_memory); | |
281 | } | |
282 | diff -Naur binutils-2.19.1.orig/bfd/elf32-avr.c binutils-2.19.1/bfd/elf32-avr.c | |
283 | --- binutils-2.19.1.orig/bfd/elf32-avr.c 2008-12-23 05:54:49.000000000 -0800 | |
284 | +++ binutils-2.19.1/bfd/elf32-avr.c 2009-02-19 09:53:10.000000000 -0800 | |
285 | @@ -854,10 +854,11 @@ | |
286 | { | |
287 | /* Relative distance is too large. */ | |
288 | ||
289 | - /* Always apply WRAPAROUND for avr2 and avr4. */ | |
290 | + /* Always apply WRAPAROUND for avr2, avr25, and avr4. */ | |
291 | switch (bfd_get_mach (input_bfd)) | |
292 | { | |
293 | case bfd_mach_avr2: | |
294 | + case bfd_mach_avr25: | |
295 | case bfd_mach_avr4: | |
296 | break; | |
297 | ||
298 | @@ -1553,7 +1554,8 @@ | |
299 | /* Adjust the local symbols defined in this section. */ | |
300 | isym = (Elf_Internal_Sym *) symtab_hdr->contents; | |
301 | isymend = isym + symtab_hdr->sh_info; | |
302 | - for (; isym < isymend; isym++) | |
303 | + /* Fix PR 9841, there may be no local symbols. */ | |
304 | + for (; isym != NULL && isym < isymend; isym++) | |
305 | { | |
306 | if (isym->st_shndx == sec_shndx | |
307 | && isym->st_value > addr | |
308 | diff -Naur binutils-2.19.1.orig/bfd/elf32-ppc.c binutils-2.19.1/bfd/elf32-ppc.c | |
309 | --- binutils-2.19.1.orig/bfd/elf32-ppc.c 2008-12-23 05:54:49.000000000 -0800 | |
310 | +++ binutils-2.19.1/bfd/elf32-ppc.c 2009-03-02 05:55:19.000000000 -0800 | |
311 | @@ -1,6 +1,6 @@ | |
312 | /* PowerPC-specific support for 32-bit ELF | |
313 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, | |
314 | - 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. | |
315 | + 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. | |
316 | Written by Ian Lance Taylor, Cygnus Support. | |
317 | ||
318 | This file is part of BFD, the Binary File Descriptor library. | |
319 | @@ -3964,6 +3964,33 @@ | |
320 | ibfd, obfd, in_abi, out_abi); | |
321 | } | |
322 | ||
323 | + /* Check for conflicting Tag_GNU_Power_ABI_Struct_Return attributes | |
324 | + and merge non-conflicting ones. */ | |
325 | + in_attr = &in_attrs[Tag_GNU_Power_ABI_Struct_Return]; | |
326 | + out_attr = &out_attrs[Tag_GNU_Power_ABI_Struct_Return]; | |
327 | + if (in_attr->i != out_attr->i) | |
328 | + { | |
329 | + out_attr->type = 1; | |
330 | + if (out_attr->i == 0) | |
331 | + out_attr->i = in_attr->i; | |
332 | + else if (in_attr->i == 0) | |
333 | + ; | |
334 | + else if (out_attr->i == 1 && in_attr->i == 2) | |
335 | + _bfd_error_handler | |
336 | + (_("Warning: %B uses r3/r4 for small structure returns, %B uses memory"), obfd, ibfd); | |
337 | + else if (out_attr->i == 2 && in_attr->i == 1) | |
338 | + _bfd_error_handler | |
339 | + (_("Warning: %B uses r3/r4 for small structure returns, %B uses memory"), ibfd, obfd); | |
340 | + else if (in_attr->i > 2) | |
341 | + _bfd_error_handler | |
342 | + (_("Warning: %B uses unknown small structure return convention %d"), ibfd, | |
343 | + in_attr->i); | |
344 | + else | |
345 | + _bfd_error_handler | |
346 | + (_("Warning: %B uses unknown small structure return convention %d"), obfd, | |
347 | + out_attr->i); | |
348 | + } | |
349 | + | |
350 | /* Merge Tag_compatibility attributes and any common GNU ones. */ | |
351 | _bfd_elf_merge_object_attributes (ibfd, obfd); | |
352 | ||
353 | @@ -4298,7 +4325,8 @@ | |
354 | return TRUE; | |
355 | } | |
356 | \f | |
357 | -/* Set htab->tls_get_addr and call the generic ELF tls_setup function. */ | |
358 | +/* Set plt output section type, htab->tls_get_addr, and call the | |
359 | + generic ELF tls_setup function. */ | |
360 | ||
361 | asection * | |
362 | ppc_elf_tls_setup (bfd *obfd, struct bfd_link_info *info) | |
363 | @@ -4319,6 +4347,43 @@ | |
364 | return _bfd_elf_tls_setup (obfd, info); | |
365 | } | |
366 | ||
367 | +/* Return TRUE iff REL is a branch reloc with a global symbol matching | |
368 | + HASH. */ | |
369 | + | |
370 | +static bfd_boolean | |
371 | +branch_reloc_hash_match (const bfd *ibfd, | |
372 | + const Elf_Internal_Rela *rel, | |
373 | + const struct elf_link_hash_entry *hash) | |
374 | +{ | |
375 | + Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (ibfd); | |
376 | + enum elf_ppc_reloc_type r_type = ELF32_R_TYPE (rel->r_info); | |
377 | + unsigned int r_symndx = ELF32_R_SYM (rel->r_info); | |
378 | + | |
379 | + if (r_symndx >= symtab_hdr->sh_info | |
380 | + && (r_type == R_PPC_PLTREL24 | |
381 | + || r_type == R_PPC_LOCAL24PC | |
382 | + || r_type == R_PPC_REL14 | |
383 | + || r_type == R_PPC_REL14_BRTAKEN | |
384 | + || r_type == R_PPC_REL14_BRNTAKEN | |
385 | + || r_type == R_PPC_REL24 | |
386 | + || r_type == R_PPC_ADDR24 | |
387 | + || r_type == R_PPC_ADDR14 | |
388 | + || r_type == R_PPC_ADDR14_BRTAKEN | |
389 | + || r_type == R_PPC_ADDR14_BRNTAKEN)) | |
390 | + { | |
391 | + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (ibfd); | |
392 | + struct elf_link_hash_entry *h; | |
393 | + | |
394 | + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; | |
395 | + while (h->root.type == bfd_link_hash_indirect | |
396 | + || h->root.type == bfd_link_hash_warning) | |
397 | + h = (struct elf_link_hash_entry *) h->root.u.i.link; | |
398 | + if (h == hash) | |
399 | + return TRUE; | |
400 | + } | |
401 | + return FALSE; | |
402 | +} | |
403 | + | |
404 | /* Run through all the TLS relocs looking for optimization | |
405 | opportunities. */ | |
406 | ||
407 | @@ -4446,35 +4511,10 @@ | |
408 | if (!expecting_tls_get_addr) | |
409 | continue; | |
410 | ||
411 | - if (rel + 1 < relend) | |
412 | - { | |
413 | - enum elf_ppc_reloc_type r_type2; | |
414 | - unsigned long r_symndx2; | |
415 | - struct elf_link_hash_entry *h2; | |
416 | - | |
417 | - /* The next instruction should be a call to | |
418 | - __tls_get_addr. Peek at the reloc to be sure. */ | |
419 | - r_type2 = ELF32_R_TYPE (rel[1].r_info); | |
420 | - r_symndx2 = ELF32_R_SYM (rel[1].r_info); | |
421 | - if (r_symndx2 >= symtab_hdr->sh_info | |
422 | - && (r_type2 == R_PPC_REL14 | |
423 | - || r_type2 == R_PPC_REL14_BRTAKEN | |
424 | - || r_type2 == R_PPC_REL14_BRNTAKEN | |
425 | - || r_type2 == R_PPC_REL24 | |
426 | - || r_type2 == R_PPC_PLTREL24)) | |
427 | - { | |
428 | - struct elf_link_hash_entry **sym_hashes; | |
429 | - | |
430 | - sym_hashes = elf_sym_hashes (ibfd); | |
431 | - h2 = sym_hashes[r_symndx2 - symtab_hdr->sh_info]; | |
432 | - while (h2->root.type == bfd_link_hash_indirect | |
433 | - || h2->root.type == bfd_link_hash_warning) | |
434 | - h2 = ((struct elf_link_hash_entry *) | |
435 | - h2->root.u.i.link); | |
436 | - if (h2 == htab->tls_get_addr) | |
437 | - continue; | |
438 | - } | |
439 | - } | |
440 | + if (rel + 1 < relend | |
441 | + && branch_reloc_hash_match (ibfd, rel + 1, | |
442 | + htab->tls_get_addr)) | |
443 | + continue; | |
444 | ||
445 | /* Uh oh, we didn't find the expected call. We | |
446 | could just mark this symbol to exclude it | |
447 | @@ -5573,7 +5613,7 @@ | |
448 | Elf_Internal_Rela *internal_relocs = NULL; | |
449 | Elf_Internal_Rela *irel, *irelend; | |
450 | struct one_fixup *fixups = NULL; | |
451 | - bfd_boolean changed; | |
452 | + unsigned changes = 0; | |
453 | struct ppc_elf_link_hash_table *htab; | |
454 | bfd_size_type trampoff; | |
455 | asection *got2; | |
456 | @@ -5820,6 +5860,7 @@ | |
457 | fixups = f; | |
458 | ||
459 | trampoff += size; | |
460 | + changes++; | |
461 | } | |
462 | else | |
463 | { | |
464 | @@ -5870,7 +5911,6 @@ | |
465 | } | |
466 | ||
467 | /* Write out the trampolines. */ | |
468 | - changed = fixups != NULL; | |
469 | if (fixups != NULL) | |
470 | { | |
471 | const int *stub; | |
472 | @@ -5936,7 +5976,7 @@ | |
473 | if (contents != NULL | |
474 | && elf_section_data (isec)->this_hdr.contents != contents) | |
475 | { | |
476 | - if (!changed && !link_info->keep_memory) | |
477 | + if (!changes && !link_info->keep_memory) | |
478 | free (contents); | |
479 | else | |
480 | { | |
481 | @@ -5945,15 +5985,35 @@ | |
482 | } | |
483 | } | |
484 | ||
485 | - if (elf_section_data (isec)->relocs != internal_relocs) | |
486 | + if (changes != 0) | |
487 | { | |
488 | - if (!changed) | |
489 | + /* Append sufficient NOP relocs so we can write out relocation | |
490 | + information for the trampolines. */ | |
491 | + Elf_Internal_Rela *new_relocs = bfd_malloc ((changes + isec->reloc_count) | |
492 | + * sizeof (*new_relocs)); | |
493 | + unsigned ix; | |
494 | + | |
495 | + if (!new_relocs) | |
496 | + goto error_return; | |
497 | + memcpy (new_relocs, internal_relocs, | |
498 | + isec->reloc_count * sizeof (*new_relocs)); | |
499 | + for (ix = changes; ix--;) | |
500 | + { | |
501 | + irel = new_relocs + ix + isec->reloc_count; | |
502 | + | |
503 | + irel->r_info = ELF32_R_INFO (0, R_PPC_NONE); | |
504 | + } | |
505 | + if (internal_relocs != elf_section_data (isec)->relocs) | |
506 | free (internal_relocs); | |
507 | - else | |
508 | - elf_section_data (isec)->relocs = internal_relocs; | |
509 | + elf_section_data (isec)->relocs = new_relocs; | |
510 | + isec->reloc_count += changes; | |
511 | + elf_section_data (isec)->rel_hdr.sh_size | |
512 | + += changes * elf_section_data (isec)->rel_hdr.sh_entsize; | |
513 | } | |
514 | + else if (elf_section_data (isec)->relocs != internal_relocs) | |
515 | + free (internal_relocs); | |
516 | ||
517 | - *again = changed; | |
518 | + *again = changes != 0; | |
519 | return TRUE; | |
520 | ||
521 | error_return: | |
522 | @@ -6321,22 +6381,21 @@ | |
523 | case R_PPC_GOT_TLSLD16_LO: | |
524 | if (tls_mask != 0 && (tls_mask & TLS_LD) == 0) | |
525 | { | |
526 | - bfd_vma insn1, insn2; | |
527 | + unsigned int insn1, insn2; | |
528 | bfd_vma offset; | |
529 | ||
530 | tls_ldgd_opt: | |
531 | offset = rel[1].r_offset; | |
532 | - insn1 = bfd_get_32 (output_bfd, | |
533 | - contents + rel->r_offset - d_offset); | |
534 | if ((tls_mask & tls_gd) != 0) | |
535 | { | |
536 | /* IE */ | |
537 | + insn1 = bfd_get_32 (output_bfd, | |
538 | + contents + rel->r_offset - d_offset); | |
539 | insn1 &= (1 << 26) - 1; | |
540 | insn1 |= 32 << 26; /* lwz */ | |
541 | insn2 = 0x7c631214; /* add 3,3,2 */ | |
542 | rel[1].r_info | |
543 | = ELF32_R_INFO (ELF32_R_SYM (rel[1].r_info), R_PPC_NONE); | |
544 | - rel[1].r_addend = 0; | |
545 | r_type = (((r_type - (R_PPC_GOT_TLSGD16 & 3)) & 3) | |
546 | + R_PPC_GOT_TPREL16); | |
547 | rel->r_info = ELF32_R_INFO (r_symndx, r_type); | |
548 | @@ -6959,6 +7018,17 @@ | |
549 | ||
550 | bfd_put_32 (output_bfd, t0, contents + rel->r_offset); | |
551 | bfd_put_32 (output_bfd, t1, contents + rel->r_offset + 4); | |
552 | + | |
553 | + /* Rewrite the reloc and convert one of the trailing nop | |
554 | + relocs to describe this relocation. */ | |
555 | + BFD_ASSERT (ELF32_R_TYPE (relend[-1].r_info) == R_PPC_NONE); | |
556 | + /* The relocs are at the bottom 2 bytes */ | |
557 | + rel[0].r_offset += 2; | |
558 | + memmove (rel + 1, rel, (relend - rel - 1) * sizeof (*rel)); | |
559 | + rel[0].r_info = ELF32_R_INFO (r_symndx, R_PPC_ADDR16_HA); | |
560 | + rel[1].r_offset += 4; | |
561 | + rel[1].r_info = ELF32_R_INFO (r_symndx, R_PPC_ADDR16_LO); | |
562 | + rel++; | |
563 | } | |
564 | continue; | |
565 | ||
566 | diff -Naur binutils-2.19.1.orig/bfd/elf64-ppc.c binutils-2.19.1/bfd/elf64-ppc.c | |
567 | --- binutils-2.19.1.orig/bfd/elf64-ppc.c 2008-10-09 05:18:24.000000000 -0700 | |
568 | +++ binutils-2.19.1/bfd/elf64-ppc.c 2009-03-02 05:55:19.000000000 -0800 | |
569 | @@ -1,6 +1,6 @@ | |
570 | /* PowerPC64-specific support for 64-bit ELF. | |
571 | - Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 | |
572 | - Free Software Foundation, Inc. | |
573 | + Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, | |
574 | + 2009 Free Software Foundation, Inc. | |
575 | Written by Linus Nordberg, Swox AB <info@swox.com>, | |
576 | based on elf32-ppc.c by Ian Lance Taylor. | |
577 | Largely rewritten by Alan Modra <amodra@bigpond.net.au> | |
578 | @@ -2608,9 +2608,15 @@ | |
579 | long *adjust; | |
580 | } opd; | |
581 | ||
582 | - /* An array for toc sections, indexed by offset/8. | |
583 | - Specifies the relocation symbol index used at a given toc offset. */ | |
584 | - unsigned *t_symndx; | |
585 | + /* An array for toc sections, indexed by offset/8. */ | |
586 | + struct _toc_sec_data | |
587 | + { | |
588 | + /* Specifies the relocation symbol index used at a given toc offset. */ | |
589 | + unsigned *symndx; | |
590 | + | |
591 | + /* And the relocation addend. */ | |
592 | + bfd_vma *add; | |
593 | + } toc; | |
594 | } u; | |
595 | ||
596 | enum _ppc64_sec_type sec_type:2; | |
597 | @@ -4578,6 +4584,7 @@ | |
598 | const Elf_Internal_Rela *rel_end; | |
599 | asection *sreloc; | |
600 | asection **opd_sym_map; | |
601 | + struct elf_link_hash_entry *tga, *dottga; | |
602 | ||
603 | if (info->relocatable) | |
604 | return TRUE; | |
605 | @@ -4594,6 +4601,10 @@ | |
606 | BFD_ASSERT (is_ppc64_elf (abfd)); | |
607 | ||
608 | htab = ppc_hash_table (info); | |
609 | + tga = elf_link_hash_lookup (&htab->elf, "__tls_get_addr", | |
610 | + FALSE, FALSE, TRUE); | |
611 | + dottga = elf_link_hash_lookup (&htab->elf, ".__tls_get_addr", | |
612 | + FALSE, FALSE, TRUE); | |
613 | symtab_hdr = &elf_symtab_hdr (abfd); | |
614 | ||
615 | sym_hashes = elf_sym_hashes (abfd); | |
616 | @@ -4829,25 +4840,8 @@ | |
617 | if (!update_plt_info (abfd, (struct ppc_link_hash_entry *) h, | |
618 | rel->r_addend)) | |
619 | return FALSE; | |
620 | - if (h == &htab->tls_get_addr->elf | |
621 | - || h == &htab->tls_get_addr_fd->elf) | |
622 | + if (h == tga || h == dottga) | |
623 | sec->has_tls_reloc = 1; | |
624 | - else if (htab->tls_get_addr == NULL | |
625 | - && CONST_STRNEQ (h->root.root.string, ".__tls_get_addr") | |
626 | - && (h->root.root.string[15] == 0 | |
627 | - || h->root.root.string[15] == '@')) | |
628 | - { | |
629 | - htab->tls_get_addr = (struct ppc_link_hash_entry *) h; | |
630 | - sec->has_tls_reloc = 1; | |
631 | - } | |
632 | - else if (htab->tls_get_addr_fd == NULL | |
633 | - && CONST_STRNEQ (h->root.root.string, "__tls_get_addr") | |
634 | - && (h->root.root.string[14] == 0 | |
635 | - || h->root.root.string[14] == '@')) | |
636 | - { | |
637 | - htab->tls_get_addr_fd = (struct ppc_link_hash_entry *) h; | |
638 | - sec->has_tls_reloc = 1; | |
639 | - } | |
640 | } | |
641 | break; | |
642 | ||
643 | @@ -4891,23 +4885,30 @@ | |
644 | ppc64_sec = ppc64_elf_section_data (sec); | |
645 | if (ppc64_sec->sec_type != sec_toc) | |
646 | { | |
647 | + bfd_size_type amt; | |
648 | + | |
649 | /* One extra to simplify get_tls_mask. */ | |
650 | - bfd_size_type amt = sec->size * sizeof (unsigned) / 8 + 1; | |
651 | - ppc64_sec->u.t_symndx = bfd_zalloc (abfd, amt); | |
652 | - if (ppc64_sec->u.t_symndx == NULL) | |
653 | + amt = sec->size * sizeof (unsigned) / 8 + sizeof (unsigned); | |
654 | + ppc64_sec->u.toc.symndx = bfd_zalloc (abfd, amt); | |
655 | + if (ppc64_sec->u.toc.symndx == NULL) | |
656 | + return FALSE; | |
657 | + amt = sec->size * sizeof (bfd_vma) / 8; | |
658 | + ppc64_sec->u.toc.add = bfd_zalloc (abfd, amt); | |
659 | + if (ppc64_sec->u.toc.add == NULL) | |
660 | return FALSE; | |
661 | BFD_ASSERT (ppc64_sec->sec_type == sec_normal); | |
662 | ppc64_sec->sec_type = sec_toc; | |
663 | } | |
664 | BFD_ASSERT (rel->r_offset % 8 == 0); | |
665 | - ppc64_sec->u.t_symndx[rel->r_offset / 8] = r_symndx; | |
666 | + ppc64_sec->u.toc.symndx[rel->r_offset / 8] = r_symndx; | |
667 | + ppc64_sec->u.toc.add[rel->r_offset / 8] = rel->r_addend; | |
668 | ||
669 | /* Mark the second slot of a GD or LD entry. | |
670 | -1 to indicate GD and -2 to indicate LD. */ | |
671 | if (tls_type == (TLS_EXPLICIT | TLS_TLS | TLS_GD)) | |
672 | - ppc64_sec->u.t_symndx[rel->r_offset / 8 + 1] = -1; | |
673 | + ppc64_sec->u.toc.symndx[rel->r_offset / 8 + 1] = -1; | |
674 | else if (tls_type == (TLS_EXPLICIT | TLS_TLS | TLS_LD)) | |
675 | - ppc64_sec->u.t_symndx[rel->r_offset / 8 + 1] = -2; | |
676 | + ppc64_sec->u.toc.symndx[rel->r_offset / 8 + 1] = -2; | |
677 | goto dodyn; | |
678 | ||
679 | case R_PPC64_TPREL16: | |
680 | @@ -5847,7 +5848,7 @@ | |
681 | fdh = (struct ppc_link_hash_entry *) fdh->elf.root.u.i.link; | |
682 | ||
683 | if (fdh == NULL | |
684 | - && info->shared | |
685 | + && !info->executable | |
686 | && (fh->elf.root.type == bfd_link_hash_undefined | |
687 | || fh->elf.root.type == bfd_link_hash_undefweak)) | |
688 | { | |
689 | @@ -5880,7 +5881,7 @@ | |
690 | ||
691 | if (fdh != NULL | |
692 | && !fdh->elf.forced_local | |
693 | - && (info->shared | |
694 | + && (!info->executable | |
695 | || fdh->elf.def_dynamic | |
696 | || fdh->elf.ref_dynamic | |
697 | || (fdh->elf.root.type == bfd_link_hash_undefweak | |
698 | @@ -6258,9 +6259,12 @@ | |
699 | type suitable for optimization, and 1 otherwise. */ | |
700 | ||
701 | static int | |
702 | -get_tls_mask (char **tls_maskp, unsigned long *toc_symndx, | |
703 | +get_tls_mask (char **tls_maskp, | |
704 | + unsigned long *toc_symndx, | |
705 | + bfd_vma *toc_addend, | |
706 | Elf_Internal_Sym **locsymsp, | |
707 | - const Elf_Internal_Rela *rel, bfd *ibfd) | |
708 | + const Elf_Internal_Rela *rel, | |
709 | + bfd *ibfd) | |
710 | { | |
711 | unsigned long r_symndx; | |
712 | int next_r; | |
713 | @@ -6288,12 +6292,14 @@ | |
714 | off = sym->st_value; | |
715 | off += rel->r_addend; | |
716 | BFD_ASSERT (off % 8 == 0); | |
717 | - r_symndx = ppc64_elf_section_data (sec)->u.t_symndx[off / 8]; | |
718 | - next_r = ppc64_elf_section_data (sec)->u.t_symndx[off / 8 + 1]; | |
719 | - if (!get_sym_h (&h, &sym, &sec, tls_maskp, locsymsp, r_symndx, ibfd)) | |
720 | - return 0; | |
721 | + r_symndx = ppc64_elf_section_data (sec)->u.toc.symndx[off / 8]; | |
722 | + next_r = ppc64_elf_section_data (sec)->u.toc.symndx[off / 8 + 1]; | |
723 | if (toc_symndx != NULL) | |
724 | *toc_symndx = r_symndx; | |
725 | + if (toc_addend != NULL) | |
726 | + *toc_addend = ppc64_elf_section_data (sec)->u.toc.add[off / 8]; | |
727 | + if (!get_sym_h (&h, &sym, &sec, tls_maskp, locsymsp, r_symndx, ibfd)) | |
728 | + return 0; | |
729 | if ((h == NULL | |
730 | || ((h->root.type == bfd_link_hash_defined | |
731 | || h->root.type == bfd_link_hash_defweak) | |
732 | @@ -6898,36 +6904,49 @@ | |
733 | struct ppc_link_hash_table *htab; | |
734 | ||
735 | htab = ppc_hash_table (info); | |
736 | - if (htab->tls_get_addr != NULL) | |
737 | - { | |
738 | - struct ppc_link_hash_entry *h = htab->tls_get_addr; | |
739 | - | |
740 | - while (h->elf.root.type == bfd_link_hash_indirect | |
741 | - || h->elf.root.type == bfd_link_hash_warning) | |
742 | - h = (struct ppc_link_hash_entry *) h->elf.root.u.i.link; | |
743 | + htab->tls_get_addr = ((struct ppc_link_hash_entry *) | |
744 | + elf_link_hash_lookup (&htab->elf, ".__tls_get_addr", | |
745 | + FALSE, FALSE, TRUE)); | |
746 | + htab->tls_get_addr_fd = ((struct ppc_link_hash_entry *) | |
747 | + elf_link_hash_lookup (&htab->elf, "__tls_get_addr", | |
748 | + FALSE, FALSE, TRUE)); | |
749 | + return _bfd_elf_tls_setup (obfd, info); | |
750 | +} | |
751 | ||
752 | - htab->tls_get_addr = h; | |
753 | +/* Return TRUE iff REL is a branch reloc with a global symbol matching | |
754 | + HASH1 or HASH2. */ | |
755 | ||
756 | - if (htab->tls_get_addr_fd == NULL | |
757 | - && h->oh != NULL | |
758 | - && h->oh->is_func_descriptor | |
759 | - && (h->oh->elf.root.type == bfd_link_hash_defined | |
760 | - || h->oh->elf.root.type == bfd_link_hash_defweak)) | |
761 | - htab->tls_get_addr_fd = h->oh; | |
762 | - } | |
763 | +static bfd_boolean | |
764 | +branch_reloc_hash_match (const bfd *ibfd, | |
765 | + const Elf_Internal_Rela *rel, | |
766 | + const struct ppc_link_hash_entry *hash1, | |
767 | + const struct ppc_link_hash_entry *hash2) | |
768 | +{ | |
769 | + Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (ibfd); | |
770 | + enum elf_ppc64_reloc_type r_type = ELF64_R_TYPE (rel->r_info); | |
771 | + unsigned int r_symndx = ELF64_R_SYM (rel->r_info); | |
772 | ||
773 | - if (htab->tls_get_addr_fd != NULL) | |
774 | + if (r_symndx >= symtab_hdr->sh_info | |
775 | + && (r_type == R_PPC64_REL24 | |
776 | + || r_type == R_PPC64_REL14 | |
777 | + || r_type == R_PPC64_REL14_BRTAKEN | |
778 | + || r_type == R_PPC64_REL14_BRNTAKEN | |
779 | + || r_type == R_PPC64_ADDR24 | |
780 | + || r_type == R_PPC64_ADDR14 | |
781 | + || r_type == R_PPC64_ADDR14_BRTAKEN | |
782 | + || r_type == R_PPC64_ADDR14_BRNTAKEN)) | |
783 | { | |
784 | - struct ppc_link_hash_entry *h = htab->tls_get_addr_fd; | |
785 | - | |
786 | - while (h->elf.root.type == bfd_link_hash_indirect | |
787 | - || h->elf.root.type == bfd_link_hash_warning) | |
788 | - h = (struct ppc_link_hash_entry *) h->elf.root.u.i.link; | |
789 | + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (ibfd); | |
790 | + struct elf_link_hash_entry *h; | |
791 | ||
792 | - htab->tls_get_addr_fd = h; | |
793 | + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; | |
794 | + while (h->root.type == bfd_link_hash_indirect | |
795 | + || h->root.type == bfd_link_hash_warning) | |
796 | + h = (struct elf_link_hash_entry *) h->root.u.i.link; | |
797 | + if (h == &hash1->elf || h == &hash2->elf) | |
798 | + return TRUE; | |
799 | } | |
800 | - | |
801 | - return _bfd_elf_tls_setup (obfd, info); | |
802 | + return FALSE; | |
803 | } | |
804 | ||
805 | /* Run through all the TLS relocs looking for optimization | |
806 | @@ -7173,55 +7192,26 @@ | |
807 | if (!expecting_tls_get_addr) | |
808 | continue; | |
809 | ||
810 | - if (rel + 1 < relend) | |
811 | + if (rel + 1 < relend | |
812 | + && branch_reloc_hash_match (ibfd, rel + 1, | |
813 | + htab->tls_get_addr, | |
814 | + htab->tls_get_addr_fd)) | |
815 | { | |
816 | - Elf_Internal_Shdr *symtab_hdr; | |
817 | - enum elf_ppc64_reloc_type r_type2; | |
818 | - unsigned long r_symndx2; | |
819 | - struct elf_link_hash_entry *h2; | |
820 | - | |
821 | - symtab_hdr = &elf_symtab_hdr (ibfd); | |
822 | - | |
823 | - /* The next instruction should be a call to | |
824 | - __tls_get_addr. Peek at the reloc to be sure. */ | |
825 | - r_type2 = ELF64_R_TYPE (rel[1].r_info); | |
826 | - r_symndx2 = ELF64_R_SYM (rel[1].r_info); | |
827 | - if (r_symndx2 >= symtab_hdr->sh_info | |
828 | - && (r_type2 == R_PPC64_REL14 | |
829 | - || r_type2 == R_PPC64_REL14_BRTAKEN | |
830 | - || r_type2 == R_PPC64_REL14_BRNTAKEN | |
831 | - || r_type2 == R_PPC64_REL24)) | |
832 | + if (expecting_tls_get_addr == 2) | |
833 | { | |
834 | - struct elf_link_hash_entry **sym_hashes; | |
835 | - | |
836 | - sym_hashes = elf_sym_hashes (ibfd); | |
837 | - | |
838 | - h2 = sym_hashes[r_symndx2 - symtab_hdr->sh_info]; | |
839 | - while (h2->root.type == bfd_link_hash_indirect | |
840 | - || h2->root.type == bfd_link_hash_warning) | |
841 | - h2 = ((struct elf_link_hash_entry *) | |
842 | - h2->root.u.i.link); | |
843 | - if (h2 != NULL | |
844 | - && (h2 == &htab->tls_get_addr->elf | |
845 | - || h2 == &htab->tls_get_addr_fd->elf)) | |
846 | - { | |
847 | - if (expecting_tls_get_addr == 2) | |
848 | - { | |
849 | - /* Check for toc tls entries. */ | |
850 | - char *toc_tls; | |
851 | - int retval; | |
852 | - | |
853 | - retval = get_tls_mask (&toc_tls, NULL, | |
854 | - &locsyms, | |
855 | - rel, ibfd); | |
856 | - if (retval == 0) | |
857 | - goto err_free_rel; | |
858 | - if (retval > 1 && toc_tls != NULL) | |
859 | - toc_ref[toc_ref_index] = 1; | |
860 | - } | |
861 | - continue; | |
862 | - } | |
863 | + /* Check for toc tls entries. */ | |
864 | + char *toc_tls; | |
865 | + int retval; | |
866 | + | |
867 | + retval = get_tls_mask (&toc_tls, NULL, NULL, | |
868 | + &locsyms, | |
869 | + rel, ibfd); | |
870 | + if (retval == 0) | |
871 | + goto err_free_rel; | |
872 | + if (retval > 1 && toc_tls != NULL) | |
873 | + toc_ref[toc_ref_index] = 1; | |
874 | } | |
875 | + continue; | |
876 | } | |
877 | ||
878 | if (expecting_tls_get_addr != 1) | |
879 | @@ -9744,7 +9734,7 @@ | |
880 | /* Get tls info. */ | |
881 | char *tls_mask; | |
882 | ||
883 | - if (!get_tls_mask (&tls_mask, NULL, &local_syms, | |
884 | + if (!get_tls_mask (&tls_mask, NULL, NULL, &local_syms, | |
885 | irela - 1, input_bfd)) | |
886 | goto error_ret_free_internal; | |
887 | if (*tls_mask != 0) | |
888 | @@ -10236,6 +10226,7 @@ | |
889 | struct ppc_link_hash_entry *fdh; | |
890 | const char *sym_name; | |
891 | unsigned long r_symndx, toc_symndx; | |
892 | + bfd_vma toc_addend; | |
893 | char tls_mask, tls_gd, tls_type; | |
894 | char sym_type; | |
895 | bfd_vma relocation; | |
896 | @@ -10344,8 +10335,8 @@ | |
897 | /* Check for toc tls entries. */ | |
898 | char *toc_tls; | |
899 | ||
900 | - if (!get_tls_mask (&toc_tls, &toc_symndx, &local_syms, | |
901 | - rel, input_bfd)) | |
902 | + if (!get_tls_mask (&toc_tls, &toc_symndx, &toc_addend, | |
903 | + &local_syms, rel, input_bfd)) | |
904 | return FALSE; | |
905 | ||
906 | if (toc_tls) | |
907 | @@ -10407,8 +10398,8 @@ | |
908 | char *toc_tls; | |
909 | int retval; | |
910 | ||
911 | - retval = get_tls_mask (&toc_tls, &toc_symndx, &local_syms, | |
912 | - rel, input_bfd); | |
913 | + retval = get_tls_mask (&toc_tls, &toc_symndx, &toc_addend, | |
914 | + &local_syms, rel, input_bfd); | |
915 | if (retval == 0) | |
916 | return FALSE; | |
917 | ||
918 | @@ -10456,6 +10447,7 @@ | |
919 | if (toc_symndx != 0) | |
920 | { | |
921 | rel->r_info = ELF64_R_INFO (toc_symndx, r_type); | |
922 | + rel->r_addend = toc_addend; | |
923 | /* We changed the symbol. Start over in order to | |
924 | get h, sym, sec etc. right. */ | |
925 | rel--; | |
926 | @@ -10509,6 +10501,7 @@ | |
927 | if (toc_symndx != 0) | |
928 | { | |
929 | rel->r_info = ELF64_R_INFO (toc_symndx, r_type); | |
930 | + rel->r_addend = toc_addend; | |
931 | /* We changed the symbol. Start over in order to | |
932 | get h, sym, sec etc. right. */ | |
933 | rel--; | |
934 | @@ -10555,20 +10548,18 @@ | |
935 | case R_PPC64_GOT_TLSLD16_LO: | |
936 | if (tls_mask != 0 && (tls_mask & TLS_LD) == 0) | |
937 | { | |
938 | - bfd_vma insn1, insn2, insn3; | |
939 | + unsigned int insn1, insn2, insn3; | |
940 | bfd_vma offset; | |
941 | ||
942 | tls_ldgd_opt: | |
943 | /* We know that the next reloc is on a tls_get_addr | |
944 | call, since ppc64_elf_tls_optimize checks this. */ | |
945 | offset = rel[1].r_offset; | |
946 | - insn1 = bfd_get_32 (output_bfd, | |
947 | - contents + rel->r_offset - d_offset); | |
948 | - insn3 = bfd_get_32 (output_bfd, | |
949 | - contents + offset + 4); | |
950 | if ((tls_mask & tls_gd) != 0) | |
951 | { | |
952 | /* IE */ | |
953 | + insn1 = bfd_get_32 (output_bfd, | |
954 | + contents + rel->r_offset - d_offset); | |
955 | insn1 &= (1 << 26) - (1 << 2); | |
956 | insn1 |= 58 << 26; /* ld */ | |
957 | insn2 = 0x7c636a14; /* add 3,3,13 */ | |
958 | @@ -10603,28 +10594,33 @@ | |
959 | rel->r_addend -= (local_syms[r_symndx].st_value | |
960 | + sec->output_offset | |
961 | + sec->output_section->vma); | |
962 | - rel[1].r_addend = rel->r_addend; | |
963 | } | |
964 | else if (toc_symndx != 0) | |
965 | - r_symndx = toc_symndx; | |
966 | + { | |
967 | + r_symndx = toc_symndx; | |
968 | + rel->r_addend = toc_addend; | |
969 | + } | |
970 | r_type = R_PPC64_TPREL16_HA; | |
971 | rel->r_info = ELF64_R_INFO (r_symndx, r_type); | |
972 | rel[1].r_info = ELF64_R_INFO (r_symndx, | |
973 | R_PPC64_TPREL16_LO); | |
974 | rel[1].r_offset += d_offset; | |
975 | + rel[1].r_addend = rel->r_addend; | |
976 | } | |
977 | + bfd_put_32 (output_bfd, insn1, | |
978 | + contents + rel->r_offset - d_offset); | |
979 | + insn3 = bfd_get_32 (output_bfd, | |
980 | + contents + offset + 4); | |
981 | if (insn3 == NOP | |
982 | || insn3 == CROR_151515 || insn3 == CROR_313131) | |
983 | { | |
984 | - insn3 = insn2; | |
985 | - insn2 = NOP; | |
986 | rel[1].r_offset += 4; | |
987 | + bfd_put_32 (output_bfd, insn2, contents + offset + 4); | |
988 | + insn2 = NOP; | |
989 | } | |
990 | - bfd_put_32 (output_bfd, insn1, | |
991 | - contents + rel->r_offset - d_offset); | |
992 | bfd_put_32 (output_bfd, insn2, contents + offset); | |
993 | - bfd_put_32 (output_bfd, insn3, contents + offset + 4); | |
994 | - if (tls_gd == 0 || toc_symndx != 0) | |
995 | + if ((tls_mask & tls_gd) == 0 | |
996 | + && (tls_gd == 0 || toc_symndx != 0)) | |
997 | { | |
998 | /* We changed the symbol. Start over in order | |
999 | to get h, sym, sec etc. right. */ | |
1000 | @@ -11001,7 +10997,8 @@ | |
1001 | ||
1002 | *offp = off | 1; | |
1003 | if ((info->shared || indx != 0) | |
1004 | - && (h == NULL | |
1005 | + && (offp == &ppc64_tlsld_got (input_bfd)->offset | |
1006 | + || h == NULL | |
1007 | || ELF_ST_VISIBILITY (h->elf.other) == STV_DEFAULT | |
1008 | || h->elf.root.type != bfd_link_hash_undefweak)) | |
1009 | { | |
1010 | diff -Naur binutils-2.19.1.orig/bfd/elf.c binutils-2.19.1/bfd/elf.c | |
1011 | --- binutils-2.19.1.orig/bfd/elf.c 2008-12-23 05:54:48.000000000 -0800 | |
1012 | +++ binutils-2.19.1/bfd/elf.c 2009-03-02 05:41:07.000000000 -0800 | |
1013 | @@ -1608,6 +1608,8 @@ | |
1014 | ||
1015 | if (hdr->sh_entsize != bed->s->sizeof_sym) | |
1016 | return FALSE; | |
1017 | + if (hdr->sh_info * hdr->sh_entsize > hdr->sh_size) | |
1018 | + return FALSE; | |
1019 | BFD_ASSERT (elf_onesymtab (abfd) == 0); | |
1020 | elf_onesymtab (abfd) = shindex; | |
1021 | elf_tdata (abfd)->symtab_hdr = *hdr; | |
1022 | @@ -1863,14 +1865,8 @@ | |
1023 | return TRUE; | |
1024 | ||
1025 | case SHT_GROUP: | |
1026 | - /* We need a BFD section for objcopy and relocatable linking, | |
1027 | - and it's handy to have the signature available as the section | |
1028 | - name. */ | |
1029 | if (! IS_VALID_GROUP_SECTION_HEADER (hdr)) | |
1030 | return FALSE; | |
1031 | - name = group_signature (abfd, hdr); | |
1032 | - if (name == NULL) | |
1033 | - return FALSE; | |
1034 | if (!_bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex)) | |
1035 | return FALSE; | |
1036 | if (hdr->contents != NULL) | |
1037 | @@ -2687,13 +2683,15 @@ | |
1038 | *failedptr = TRUE; | |
1039 | } | |
1040 | ||
1041 | -/* Fill in the contents of a SHT_GROUP section. */ | |
1042 | +/* Fill in the contents of a SHT_GROUP section. Called from | |
1043 | + _bfd_elf_compute_section_file_positions for gas, objcopy, and | |
1044 | + when ELF targets use the generic linker, ld. Called for ld -r | |
1045 | + from bfd_elf_final_link. */ | |
1046 | ||
1047 | void | |
1048 | bfd_elf_set_group_contents (bfd *abfd, asection *sec, void *failedptrarg) | |
1049 | { | |
1050 | bfd_boolean *failedptr = failedptrarg; | |
1051 | - unsigned long symindx; | |
1052 | asection *elt, *first; | |
1053 | unsigned char *loc; | |
1054 | bfd_boolean gas; | |
1055 | @@ -2704,20 +2702,49 @@ | |
1056 | || *failedptr) | |
1057 | return; | |
1058 | ||
1059 | - symindx = 0; | |
1060 | - if (elf_group_id (sec) != NULL) | |
1061 | - symindx = elf_group_id (sec)->udata.i; | |
1062 | - | |
1063 | - if (symindx == 0) | |
1064 | - { | |
1065 | - /* If called from the assembler, swap_out_syms will have set up | |
1066 | - elf_section_syms; If called for "ld -r", use target_index. */ | |
1067 | - if (elf_section_syms (abfd) != NULL) | |
1068 | - symindx = elf_section_syms (abfd)[sec->index]->udata.i; | |
1069 | - else | |
1070 | - symindx = sec->target_index; | |
1071 | + if (elf_section_data (sec)->this_hdr.sh_info == 0) | |
1072 | + { | |
1073 | + unsigned long symindx = 0; | |
1074 | + | |
1075 | + /* elf_group_id will have been set up by objcopy and the | |
1076 | + generic linker. */ | |
1077 | + if (elf_group_id (sec) != NULL) | |
1078 | + symindx = elf_group_id (sec)->udata.i; | |
1079 | + | |
1080 | + if (symindx == 0) | |
1081 | + { | |
1082 | + /* If called from the assembler, swap_out_syms will have set up | |
1083 | + elf_section_syms. */ | |
1084 | + BFD_ASSERT (elf_section_syms (abfd) != NULL); | |
1085 | + symindx = elf_section_syms (abfd)[sec->index]->udata.i; | |
1086 | + } | |
1087 | + elf_section_data (sec)->this_hdr.sh_info = symindx; | |
1088 | + } | |
1089 | + else if (elf_section_data (sec)->this_hdr.sh_info == (unsigned int) -2) | |
1090 | + { | |
1091 | + /* The ELF backend linker sets sh_info to -2 when the group | |
1092 | + signature symbol is global, and thus the index can't be | |
1093 | + set until all local symbols are output. */ | |
1094 | + asection *igroup = elf_sec_group (elf_next_in_group (sec)); | |
1095 | + struct bfd_elf_section_data *sec_data = elf_section_data (igroup); | |
1096 | + unsigned long symndx = sec_data->this_hdr.sh_info; | |
1097 | + unsigned long extsymoff = 0; | |
1098 | + struct elf_link_hash_entry *h; | |
1099 | + | |
1100 | + if (!elf_bad_symtab (igroup->owner)) | |
1101 | + { | |
1102 | + Elf_Internal_Shdr *symtab_hdr; | |
1103 | + | |
1104 | + symtab_hdr = &elf_tdata (igroup->owner)->symtab_hdr; | |
1105 | + extsymoff = symtab_hdr->sh_info; | |
1106 | + } | |
1107 | + h = elf_sym_hashes (igroup->owner)[symndx - extsymoff]; | |
1108 | + while (h->root.type == bfd_link_hash_indirect | |
1109 | + || h->root.type == bfd_link_hash_warning) | |
1110 | + h = (struct elf_link_hash_entry *) h->root.u.i.link; | |
1111 | + | |
1112 | + elf_section_data (sec)->this_hdr.sh_info = h->indx; | |
1113 | } | |
1114 | - elf_section_data (sec)->this_hdr.sh_info = symindx; | |
1115 | ||
1116 | /* The contents won't be allocated for "ld -r" or objcopy. */ | |
1117 | gas = TRUE; | |
1118 | @@ -4131,6 +4158,7 @@ | |
1119 | bfd_size_type maxpagesize; | |
1120 | unsigned int alloc; | |
1121 | unsigned int i, j; | |
1122 | + bfd_vma header_pad = 0; | |
1123 | ||
1124 | if (link_info == NULL | |
1125 | && !_bfd_elf_map_sections_to_segments (abfd, link_info)) | |
1126 | @@ -4138,7 +4166,11 @@ | |
1127 | ||
1128 | alloc = 0; | |
1129 | for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next) | |
1130 | - ++alloc; | |
1131 | + { | |
1132 | + ++alloc; | |
1133 | + if (m->header_size) | |
1134 | + header_pad = m->header_size; | |
1135 | + } | |
1136 | ||
1137 | elf_elfheader (abfd)->e_phoff = bed->s->sizeof_ehdr; | |
1138 | elf_elfheader (abfd)->e_phentsize = bed->s->sizeof_phdr; | |
1139 | @@ -4156,7 +4188,21 @@ | |
1140 | return TRUE; | |
1141 | } | |
1142 | ||
1143 | - phdrs = bfd_alloc2 (abfd, alloc, sizeof (Elf_Internal_Phdr)); | |
1144 | + /* We're writing the size in elf_tdata (abfd)->program_header_size, | |
1145 | + see assign_file_positions_except_relocs, so make sure we have | |
1146 | + that amount allocated, with trailing space cleared. | |
1147 | + The variable alloc contains the computed need, while elf_tdata | |
1148 | + (abfd)->program_header_size contains the size used for the | |
1149 | + layout. | |
1150 | + See ld/emultempl/elf-generic.em:gld${EMULATION_NAME}_map_segments | |
1151 | + where the layout is forced to according to a larger size in the | |
1152 | + last iterations for the testcase ld-elf/header. */ | |
1153 | + BFD_ASSERT (elf_tdata (abfd)->program_header_size % bed->s->sizeof_phdr | |
1154 | + == 0); | |
1155 | + phdrs = bfd_zalloc2 (abfd, | |
1156 | + (elf_tdata (abfd)->program_header_size | |
1157 | + / bed->s->sizeof_phdr), | |
1158 | + sizeof (Elf_Internal_Phdr)); | |
1159 | elf_tdata (abfd)->phdr = phdrs; | |
1160 | if (phdrs == NULL) | |
1161 | return FALSE; | |
1162 | @@ -4167,6 +4213,11 @@ | |
1163 | ||
1164 | off = bed->s->sizeof_ehdr; | |
1165 | off += alloc * bed->s->sizeof_phdr; | |
1166 | + if (header_pad < (bfd_vma) off) | |
1167 | + header_pad = 0; | |
1168 | + else | |
1169 | + header_pad -= off; | |
1170 | + off += header_pad; | |
1171 | ||
1172 | for (m = elf_tdata (abfd)->segment_map, p = phdrs, j = 0; | |
1173 | m != NULL; | |
1174 | @@ -4354,6 +4405,11 @@ | |
1175 | ||
1176 | p->p_filesz += alloc * bed->s->sizeof_phdr; | |
1177 | p->p_memsz += alloc * bed->s->sizeof_phdr; | |
1178 | + if (m->count) | |
1179 | + { | |
1180 | + p->p_filesz += header_pad; | |
1181 | + p->p_memsz += header_pad; | |
1182 | + } | |
1183 | } | |
1184 | ||
1185 | if (p->p_type == PT_LOAD | |
1186 | @@ -5836,6 +5892,10 @@ | |
1187 | phdr_included = TRUE; | |
1188 | } | |
1189 | ||
1190 | + if (map->includes_filehdr && first_section) | |
1191 | + /* We need to keep the space used by the headers fixed. */ | |
1192 | + map->header_size = first_section->vma - segment->p_vaddr; | |
1193 | + | |
1194 | if (!map->includes_phdrs | |
1195 | && !map->includes_filehdr | |
1196 | && map->p_paddr_valid) | |
1197 | @@ -6004,7 +6064,7 @@ | |
1198 | if (elf_section_flags (isec) & SHF_GROUP) | |
1199 | elf_section_flags (osec) |= SHF_GROUP; | |
1200 | elf_next_in_group (osec) = elf_next_in_group (isec); | |
1201 | - elf_group_name (osec) = elf_group_name (isec); | |
1202 | + elf_section_data (osec)->group = elf_section_data (isec)->group; | |
1203 | } | |
1204 | } | |
1205 | ||
1206 | diff -Naur binutils-2.19.1.orig/bfd/elf-eh-frame.c binutils-2.19.1/bfd/elf-eh-frame.c | |
1207 | --- binutils-2.19.1.orig/bfd/elf-eh-frame.c 2008-09-17 02:00:44.000000000 -0700 | |
1208 | +++ binutils-2.19.1/bfd/elf-eh-frame.c 2009-03-02 05:53:31.000000000 -0800 | |
1209 | @@ -549,16 +549,6 @@ | |
1210 | < (bfd_size_type) ((buf) - ehbuf))) \ | |
1211 | cookie->rel++ | |
1212 | ||
1213 | -#define REQUIRE_CLEARED_RELOCS(buf) \ | |
1214 | - while (cookie->rel < cookie->relend \ | |
1215 | - && (cookie->rel->r_offset \ | |
1216 | - < (bfd_size_type) ((buf) - ehbuf))) \ | |
1217 | - { \ | |
1218 | - REQUIRE (cookie->rel->r_info == 0); \ | |
1219 | - REQUIRE (cookie->rel->r_addend == 0); \ | |
1220 | - cookie->rel++; \ | |
1221 | - } | |
1222 | - | |
1223 | #define GET_RELOC(buf) \ | |
1224 | ((cookie->rel < cookie->relend \ | |
1225 | && (cookie->rel->r_offset \ | |
1226 | @@ -817,16 +807,16 @@ | |
1227 | ||
1228 | buf = last_fde + 4 + hdr_length; | |
1229 | ||
1230 | - /* Cleared FDE? The instructions will not be cleared but verify all | |
1231 | - the relocation entries for them are cleared. */ | |
1232 | - if (rsec == NULL) | |
1233 | - { | |
1234 | - REQUIRE_CLEARED_RELOCS (buf); | |
1235 | - } | |
1236 | - else | |
1237 | - { | |
1238 | - SKIP_RELOCS (buf); | |
1239 | - } | |
1240 | + /* For NULL RSEC (cleared FDE belonging to a discarded section) | |
1241 | + the relocations are commonly cleared. We do not sanity check if | |
1242 | + all these relocations are cleared as (1) relocations to | |
1243 | + .gcc_except_table will remain uncleared (they will get dropped | |
1244 | + with the drop of this unused FDE) and (2) BFD already safely drops | |
1245 | + relocations of any type to .eh_frame by | |
1246 | + elf_section_ignore_discarded_relocs. | |
1247 | + TODO: The .gcc_except_table entries should be also filtered as | |
1248 | + .eh_frame entries; or GCC could rather use COMDAT for them. */ | |
1249 | + SKIP_RELOCS (buf); | |
1250 | } | |
1251 | ||
1252 | /* Try to interpret the CFA instructions and find the first | |
1253 | diff -Naur binutils-2.19.1.orig/bfd/elflink.c binutils-2.19.1/bfd/elflink.c | |
1254 | --- binutils-2.19.1.orig/bfd/elflink.c 2008-08-22 01:32:39.000000000 -0700 | |
1255 | +++ binutils-2.19.1/bfd/elflink.c 2009-03-02 05:48:42.000000000 -0800 | |
1256 | @@ -9046,6 +9046,63 @@ | |
1257 | continue; | |
1258 | } | |
1259 | ||
1260 | + if (finfo->info->relocatable | |
1261 | + && (o->flags & (SEC_LINKER_CREATED | SEC_GROUP)) == SEC_GROUP) | |
1262 | + { | |
1263 | + /* Deal with the group signature symbol. */ | |
1264 | + struct bfd_elf_section_data *sec_data = elf_section_data (o); | |
1265 | + unsigned long symndx = sec_data->this_hdr.sh_info; | |
1266 | + asection *osec = o->output_section; | |
1267 | + | |
1268 | + if (symndx >= locsymcount | |
1269 | + || (elf_bad_symtab (input_bfd) | |
1270 | + && finfo->sections[symndx] == NULL)) | |
1271 | + { | |
1272 | + struct elf_link_hash_entry *h = sym_hashes[symndx - extsymoff]; | |
1273 | + while (h->root.type == bfd_link_hash_indirect | |
1274 | + || h->root.type == bfd_link_hash_warning) | |
1275 | + h = (struct elf_link_hash_entry *) h->root.u.i.link; | |
1276 | + /* Arrange for symbol to be output. */ | |
1277 | + h->indx = -2; | |
1278 | + elf_section_data (osec)->this_hdr.sh_info = -2; | |
1279 | + } | |
1280 | + else if (ELF_ST_TYPE (isymbuf[symndx].st_info) == STT_SECTION) | |
1281 | + { | |
1282 | + /* We'll use the output section target_index. */ | |
1283 | + asection *sec = finfo->sections[symndx]->output_section; | |
1284 | + elf_section_data (osec)->this_hdr.sh_info = sec->target_index; | |
1285 | + } | |
1286 | + else | |
1287 | + { | |
1288 | + if (finfo->indices[symndx] == -1) | |
1289 | + { | |
1290 | + /* Otherwise output the local symbol now. */ | |
1291 | + Elf_Internal_Sym sym = isymbuf[symndx]; | |
1292 | + asection *sec = finfo->sections[symndx]->output_section; | |
1293 | + const char *name; | |
1294 | + | |
1295 | + name = bfd_elf_string_from_elf_section (input_bfd, | |
1296 | + symtab_hdr->sh_link, | |
1297 | + sym.st_name); | |
1298 | + if (name == NULL) | |
1299 | + return FALSE; | |
1300 | + | |
1301 | + sym.st_shndx = _bfd_elf_section_from_bfd_section (output_bfd, | |
1302 | + sec); | |
1303 | + if (sym.st_shndx == SHN_BAD) | |
1304 | + return FALSE; | |
1305 | + | |
1306 | + sym.st_value += o->output_offset; | |
1307 | + | |
1308 | + finfo->indices[symndx] = bfd_get_symcount (output_bfd); | |
1309 | + if (! elf_link_output_sym (finfo, name, &sym, o, NULL)) | |
1310 | + return FALSE; | |
1311 | + } | |
1312 | + elf_section_data (osec)->this_hdr.sh_info | |
1313 | + = finfo->indices[symndx]; | |
1314 | + } | |
1315 | + } | |
1316 | + | |
1317 | if ((o->flags & SEC_HAS_CONTENTS) == 0 | |
1318 | || (o->size == 0 && (o->flags & SEC_RELOC) == 0)) | |
1319 | continue; | |
1320 | @@ -11982,8 +12039,21 @@ | |
1321 | return ret; | |
1322 | } | |
1323 | ||
1324 | +/* For a SHT_GROUP section, return the group signature. For other | |
1325 | + sections, return the normal section name. */ | |
1326 | + | |
1327 | +static const char * | |
1328 | +section_signature (asection *sec) | |
1329 | +{ | |
1330 | + if ((sec->flags & SEC_GROUP) != 0 | |
1331 | + && elf_next_in_group (sec) != NULL | |
1332 | + && elf_group_name (elf_next_in_group (sec)) != NULL) | |
1333 | + return elf_group_name (elf_next_in_group (sec)); | |
1334 | + return sec->name; | |
1335 | +} | |
1336 | + | |
1337 | void | |
1338 | -_bfd_elf_section_already_linked (bfd *abfd, struct bfd_section *sec, | |
1339 | +_bfd_elf_section_already_linked (bfd *abfd, asection *sec, | |
1340 | struct bfd_link_info *info) | |
1341 | { | |
1342 | flagword flags; | |
1343 | @@ -12023,7 +12093,7 @@ | |
1344 | causes trouble for MIPS ELF, which relies on link once semantics | |
1345 | to handle the .reginfo section correctly. */ | |
1346 | ||
1347 | - name = bfd_get_section_name (abfd, sec); | |
1348 | + name = section_signature (sec); | |
1349 | ||
1350 | if (CONST_STRNEQ (name, ".gnu.linkonce.") | |
1351 | && (p = strchr (name + sizeof (".gnu.linkonce.") - 1, '.')) != NULL) | |
1352 | @@ -12038,7 +12108,7 @@ | |
1353 | /* We may have 2 different types of sections on the list: group | |
1354 | sections and linkonce sections. Match like sections. */ | |
1355 | if ((flags & SEC_GROUP) == (l->sec->flags & SEC_GROUP) | |
1356 | - && strcmp (name, l->sec->name) == 0 | |
1357 | + && strcmp (name, section_signature (l->sec)) == 0 | |
1358 | && bfd_coff_get_comdat_section (l->sec->owner, l->sec) == NULL) | |
1359 | { | |
1360 | /* The section has already been linked. See if we should | |
1361 | @@ -12161,6 +12231,28 @@ | |
1362 | } | |
1363 | } | |
1364 | ||
1365 | + /* Do not complain on unresolved relocations in `.gnu.linkonce.r.F' | |
1366 | + referencing its discarded `.gnu.linkonce.t.F' counterpart - g++-3.4 | |
1367 | + specific as g++-4.x is using COMDAT groups (without the `.gnu.linkonce' | |
1368 | + prefix) instead. `.gnu.linkonce.r.*' were the `.rodata' part of its | |
1369 | + matching `.gnu.linkonce.t.*'. If `.gnu.linkonce.r.F' is not discarded | |
1370 | + but its `.gnu.linkonce.t.F' is discarded means we chose one-only | |
1371 | + `.gnu.linkonce.t.F' section from a different bfd not requiring any | |
1372 | + `.gnu.linkonce.r.F'. Thus `.gnu.linkonce.r.F' should be discarded. | |
1373 | + The reverse order cannot happen as there is never a bfd with only the | |
1374 | + `.gnu.linkonce.r.F' section. The order of sections in a bfd does not | |
1375 | + matter as here were are looking only for cross-bfd sections. */ | |
1376 | + | |
1377 | + if ((flags & SEC_GROUP) == 0 && CONST_STRNEQ (name, ".gnu.linkonce.r.")) | |
1378 | + for (l = already_linked_list->entry; l != NULL; l = l->next) | |
1379 | + if ((l->sec->flags & SEC_GROUP) == 0 | |
1380 | + && CONST_STRNEQ (l->sec->name, ".gnu.linkonce.t.")) | |
1381 | + { | |
1382 | + if (abfd != l->sec->owner) | |
1383 | + sec->output_section = bfd_abs_section_ptr; | |
1384 | + break; | |
1385 | + } | |
1386 | + | |
1387 | /* This is the first section with this name. Record it. */ | |
1388 | if (! bfd_section_already_linked_table_insert (already_linked_list, sec)) | |
1389 | info->callbacks->einfo (_("%F%P: already_linked_table: %E")); | |
1390 | diff -Naur binutils-2.19.1.orig/bfd/linker.c binutils-2.19.1/bfd/linker.c | |
1391 | --- binutils-2.19.1.orig/bfd/linker.c 2008-08-16 20:12:49.000000000 -0700 | |
1392 | +++ binutils-2.19.1/bfd/linker.c 2009-03-02 05:32:54.000000000 -0800 | |
1393 | @@ -2796,18 +2796,36 @@ | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | - /* Get and relocate the section contents. */ | |
1398 | - sec_size = (input_section->rawsize > input_section->size | |
1399 | - ? input_section->rawsize | |
1400 | - : input_section->size); | |
1401 | - contents = bfd_malloc (sec_size); | |
1402 | - if (contents == NULL && sec_size != 0) | |
1403 | - goto error_return; | |
1404 | - new_contents = (bfd_get_relocated_section_contents | |
1405 | - (output_bfd, info, link_order, contents, info->relocatable, | |
1406 | - _bfd_generic_link_get_symbols (input_bfd))); | |
1407 | - if (!new_contents) | |
1408 | - goto error_return; | |
1409 | + if ((output_section->flags & (SEC_GROUP | SEC_LINKER_CREATED)) == SEC_GROUP | |
1410 | + && input_section->size != 0) | |
1411 | + { | |
1412 | + /* Group section contents are set by bfd_elf_set_group_contents. */ | |
1413 | + if (!output_bfd->output_has_begun) | |
1414 | + { | |
1415 | + /* FIXME: This hack ensures bfd_elf_set_group_contents is called. */ | |
1416 | + if (!bfd_set_section_contents (output_bfd, output_section, "", 0, 1)) | |
1417 | + goto error_return; | |
1418 | + } | |
1419 | + new_contents = output_section->contents; | |
1420 | + BFD_ASSERT (new_contents != NULL); | |
1421 | + BFD_ASSERT (input_section->output_offset == 0); | |
1422 | + } | |
1423 | + else | |
1424 | + { | |
1425 | + /* Get and relocate the section contents. */ | |
1426 | + sec_size = (input_section->rawsize > input_section->size | |
1427 | + ? input_section->rawsize | |
1428 | + : input_section->size); | |
1429 | + contents = bfd_malloc (sec_size); | |
1430 | + if (contents == NULL && sec_size != 0) | |
1431 | + goto error_return; | |
1432 | + new_contents = (bfd_get_relocated_section_contents | |
1433 | + (output_bfd, info, link_order, contents, | |
1434 | + info->relocatable, | |
1435 | + _bfd_generic_link_get_symbols (input_bfd))); | |
1436 | + if (!new_contents) | |
1437 | + goto error_return; | |
1438 | + } | |
1439 | ||
1440 | /* Output the section contents. */ | |
1441 | loc = input_section->output_offset * bfd_octets_per_byte (output_bfd); | |
1442 | diff -Naur binutils-2.19.1.orig/bfd/Makefile.in binutils-2.19.1/bfd/Makefile.in | |
1443 | --- binutils-2.19.1.orig/bfd/Makefile.in 2009-02-02 02:44:39.000000000 -0800 | |
1444 | +++ binutils-2.19.1/bfd/Makefile.in 2009-07-07 08:52:14.000000000 -0700 | |
1445 | @@ -190,7 +190,7 @@ | |
1446 | PACKAGE_TARNAME = @PACKAGE_TARNAME@ | |
1447 | PACKAGE_VERSION = @PACKAGE_VERSION@ | |
1448 | PATH_SEPARATOR = @PATH_SEPARATOR@ | |
1449 | -PKGVERSION = @PKGVERSION@ | |
1450 | +PKGVERSION = (GNU Binutils for Cross-LFS - Retrieved on 20090707) | |
1451 | POSUB = @POSUB@ | |
1452 | RANLIB = @RANLIB@ | |
1453 | REPORT_BUGS_TEXI = @REPORT_BUGS_TEXI@ | |
1454 | @@ -271,7 +271,7 @@ | |
1455 | ACLOCAL_AMFLAGS = -I . -I .. -I ../config | |
1456 | ||
1457 | # Uncomment the following line when doing a release. | |
1458 | -RELEASE = y | |
1459 | +RELEASE=y | |
1460 | INCDIR = $(srcdir)/../include | |
1461 | CSEARCH = -I. -I$(srcdir) -I$(INCDIR) | |
1462 | MKDEP = gcc -MM | |
1463 | diff -Naur binutils-2.19.1.orig/bfd/syms.c binutils-2.19.1/bfd/syms.c | |
1464 | --- binutils-2.19.1.orig/bfd/syms.c 2008-06-30 13:51:58.000000000 -0700 | |
1465 | +++ binutils-2.19.1/bfd/syms.c 2009-03-02 05:49:22.000000000 -0800 | |
1466 | @@ -1,6 +1,6 @@ | |
1467 | /* Generic symbol-table support for the BFD library. | |
1468 | Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, | |
1469 | - 2000, 2001, 2002, 2003, 2004, 2007 | |
1470 | + 2000, 2001, 2002, 2003, 2004, 2007, 2008, 2009 | |
1471 | Free Software Foundation, Inc. | |
1472 | Written by Cygnus Support. | |
1473 | ||
1474 | @@ -1379,10 +1379,11 @@ | |
1475 | { | |
1476 | size_t len; | |
1477 | ||
1478 | - if (info->filename != NULL) | |
1479 | - free (info->filename); | |
1480 | + /* Don't free info->filename here. objdump and other | |
1481 | + apps keep a copy of a previously returned file name | |
1482 | + pointer. */ | |
1483 | len = strlen (file_name) + 1; | |
1484 | - info->filename = bfd_malloc (dirlen + len); | |
1485 | + info->filename = bfd_alloc (abfd, dirlen + len); | |
1486 | if (info->filename == NULL) | |
1487 | return FALSE; | |
1488 | memcpy (info->filename, directory_name, dirlen); | |
1489 | diff -Naur binutils-2.19.1.orig/bfd/version.h binutils-2.19.1/bfd/version.h | |
1490 | --- binutils-2.19.1.orig/bfd/version.h 2009-02-02 02:09:26.000000000 -0800 | |
1491 | +++ binutils-2.19.1/bfd/version.h 2009-07-06 17:00:10.000000000 -0700 | |
1492 | @@ -1,4 +1,4 @@ | |
1493 | -#define BFD_VERSION_DATE 20090202 | |
1494 | +#define BFD_VERSION_DATE 20090707 | |
1495 | #define BFD_VERSION @bfd_version@ | |
1496 | #define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@ | |
1497 | #define REPORT_BUGS_TO @report_bugs_to@ | |
1498 | diff -Naur binutils-2.19.1.orig/binutils/ChangeLog binutils-2.19.1/binutils/ChangeLog | |
1499 | --- binutils-2.19.1.orig/binutils/ChangeLog 2008-12-23 05:54:49.000000000 -0800 | |
1500 | +++ binutils-2.19.1/binutils/ChangeLog 2009-03-02 05:43:13.000000000 -0800 | |
1501 | @@ -1,3 +1,16 @@ | |
1502 | +2009-03-02 Alan Modra <amodra@bigpond.net.au> | |
1503 | + | |
1504 | + 2008-12-04 Ben Elliston <bje@au.ibm.com> | |
1505 | + * doc/binutils.texi (objdump): Update booke documentation. | |
1506 | + * NEWS: Document user-visible changes to command line options. | |
1507 | + | |
1508 | + 2008-10-10 Nathan Froyd <froydnj@codesourcery.com> | |
1509 | + * readelf.c (display_power_gnu_attribute): Decode | |
1510 | + Tag_GNU_Power_ABI_Struct_Return. | |
1511 | + | |
1512 | + 2008-09-28 Alan Modra <amodra@bigpond.net.au> | |
1513 | + * objcopy.c (setup_section): Set elf_group_id. | |
1514 | + | |
1515 | 2008-12-23 Nick Clifton <nickc@redhat.com> | |
1516 | ||
1517 | * windmc.c (main): Use correct type for file length. | |
1518 | diff -Naur binutils-2.19.1.orig/binutils/doc/binutils.texi binutils-2.19.1/binutils/doc/binutils.texi | |
1519 | --- binutils-2.19.1.orig/binutils/doc/binutils.texi 2008-08-05 17:42:17.000000000 -0700 | |
1520 | +++ binutils-2.19.1/binutils/doc/binutils.texi 2009-03-02 05:43:13.000000000 -0800 | |
1521 | @@ -1843,12 +1843,12 @@ | |
1522 | instructs the disassembler to print a mnemonic suffix even when the | |
1523 | suffix could be inferred by the operands. | |
1524 | ||
1525 | -For PPC, @option{booke}, @option{booke32} and @option{booke64} select | |
1526 | -disassembly of BookE instructions. @option{32} and @option{64} select | |
1527 | -PowerPC and PowerPC64 disassembly, respectively. @option{e300} | |
1528 | -selects disassembly for the e300 family. @option{440} selects | |
1529 | -disassembly for the PowerPC 440. @option{ppcps} selects disassembly | |
1530 | -for the paired single instructions of the PPC750CL. | |
1531 | +For PowerPC, @option{booke} controls the disassembly of BookE | |
1532 | +instructions. @option{32} and @option{64} select PowerPC and | |
1533 | +PowerPC64 disassembly, respectively. @option{e300} selects | |
1534 | +disassembly for the e300 family. @option{440} selects disassembly for | |
1535 | +the PowerPC 440. @option{ppcps} selects disassembly for the paired | |
1536 | +single instructions of the PPC750CL. | |
1537 | ||
1538 | For MIPS, this option controls the printing of instruction mnemonic | |
1539 | names and register names in disassembled instructions. Multiple | |
1540 | diff -Naur binutils-2.19.1.orig/binutils/NEWS binutils-2.19.1/binutils/NEWS | |
1541 | --- binutils-2.19.1.orig/binutils/NEWS 2008-09-08 01:56:56.000000000 -0700 | |
1542 | +++ binutils-2.19.1/binutils/NEWS 2009-03-02 05:43:13.000000000 -0800 | |
1543 | @@ -1,5 +1,9 @@ | |
1544 | -*- text -*- | |
1545 | ||
1546 | +* Support for PowerPC booke64 instructions has been removed. The assembler no | |
1547 | + longer accepts -mbooke32 or -mbooke64 and the disassembler no longer accepts | |
1548 | + -Mbooke32 or -Mbooke64. Instead, -mbooke and -Mbooke should be used. | |
1549 | + | |
1550 | Changes in 2.19: | |
1551 | ||
1552 | * Added -wL switch to dump decoded contents of .debug_line. | |
1553 | diff -Naur binutils-2.19.1.orig/binutils/objcopy.c binutils-2.19.1/binutils/objcopy.c | |
1554 | --- binutils-2.19.1.orig/binutils/objcopy.c 2008-08-05 17:42:17.000000000 -0700 | |
1555 | +++ binutils-2.19.1/binutils/objcopy.c 2009-03-02 05:31:14.000000000 -0800 | |
1556 | @@ -2344,6 +2344,18 @@ | |
1557 | if (extract_symbol) | |
1558 | return; | |
1559 | ||
1560 | + if ((isection->flags & SEC_GROUP) != 0) | |
1561 | + { | |
1562 | + asymbol *gsym = group_signature (isection); | |
1563 | + | |
1564 | + if (gsym != NULL) | |
1565 | + { | |
1566 | + gsym->flags |= BSF_KEEP; | |
1567 | + if (ibfd->xvec->flavour == bfd_target_elf_flavour) | |
1568 | + elf_group_id (isection) = gsym; | |
1569 | + } | |
1570 | + } | |
1571 | + | |
1572 | /* Allow the BFD backend to copy any private data it understands | |
1573 | from the input section to the output section. */ | |
1574 | if (!bfd_copy_private_section_data (ibfd, isection, obfd, osection)) | |
1575 | @@ -2351,13 +2363,6 @@ | |
1576 | err = _("failed to copy private data"); | |
1577 | goto loser; | |
1578 | } | |
1579 | - else if ((isection->flags & SEC_GROUP) != 0) | |
1580 | - { | |
1581 | - asymbol *gsym = group_signature (isection); | |
1582 | - | |
1583 | - if (gsym != NULL) | |
1584 | - gsym->flags |= BSF_KEEP; | |
1585 | - } | |
1586 | ||
1587 | /* All went well. */ | |
1588 | return; | |
1589 | diff -Naur binutils-2.19.1.orig/binutils/readelf.c binutils-2.19.1/binutils/readelf.c | |
1590 | --- binutils-2.19.1.orig/binutils/readelf.c 2008-09-17 02:00:44.000000000 -0700 | |
1591 | +++ binutils-2.19.1/binutils/readelf.c 2009-03-02 05:35:24.000000000 -0800 | |
1592 | @@ -9062,6 +9062,29 @@ | |
1593 | return p; | |
1594 | } | |
1595 | ||
1596 | + if (tag == Tag_GNU_Power_ABI_Struct_Return) | |
1597 | + { | |
1598 | + val = read_uleb128 (p, &len); | |
1599 | + p += len; | |
1600 | + printf (" Tag_GNU_Power_ABI_Struct_Return: "); | |
1601 | + switch (val) | |
1602 | + { | |
1603 | + case 0: | |
1604 | + printf ("Any\n"); | |
1605 | + break; | |
1606 | + case 1: | |
1607 | + printf ("r3/r4\n"); | |
1608 | + break; | |
1609 | + case 2: | |
1610 | + printf ("Memory\n"); | |
1611 | + break; | |
1612 | + default: | |
1613 | + printf ("??? (%d)\n", val); | |
1614 | + break; | |
1615 | + } | |
1616 | + return p; | |
1617 | + } | |
1618 | + | |
1619 | if (tag & 1) | |
1620 | type = 1; /* String. */ | |
1621 | else | |
1622 | diff -Naur binutils-2.19.1.orig/configure.ac binutils-2.19.1/configure.ac | |
1623 | --- binutils-2.19.1.orig/configure.ac 2009-02-02 03:54:49.000000000 -0800 | |
1624 | +++ binutils-2.19.1/configure.ac 2008-09-03 19:18:16.000000000 -0700 | |
1625 | @@ -166,7 +166,7 @@ | |
1626 | # binutils, gas and ld appear in that order because it makes sense to run | |
1627 | # "make check" in that particular order. | |
1628 | # If --enable-gold is used, "gold" will replace "ld". | |
1629 | -host_tools="byacc flex bison binutils gas ld fixincludes gcc sid sim gdb make patch prms send-pr gprof etc expect dejagnu ash bash bzip2 m4 autoconf automake libtool diff rcs fileutils shellutils time textutils wdiff find uudecode hello tar gzip indent recode release sed utils guile perl gawk findutils gettext zip fastjar gnattools" | |
1630 | +host_tools="texinfo byacc flex bison binutils gas ld fixincludes gcc sid sim gdb make patch prms send-pr gprof etc expect dejagnu ash bash bzip2 m4 autoconf automake libtool diff rcs fileutils shellutils time textutils wdiff find uudecode hello tar gzip indent recode release sed utils guile perl gawk findutils gettext zip fastjar gnattools" | |
1631 | ||
1632 | # libgcj represents the runtime libraries only used by gcj. | |
1633 | libgcj="target-libffi \ | |
1634 | diff -Naur binutils-2.19.1.orig/gas/ChangeLog binutils-2.19.1/gas/ChangeLog | |
1635 | --- binutils-2.19.1.orig/gas/ChangeLog 2009-01-14 00:51:14.000000000 -0800 | |
1636 | +++ binutils-2.19.1/gas/ChangeLog 2009-04-01 08:47:36.000000000 -0700 | |
1637 | @@ -1,3 +1,39 @@ | |
1638 | +2009-04-01 Nick Clifton <nickc@redhat.com> | |
1639 | + | |
1640 | + * Import this patch: | |
1641 | + | |
1642 | + 2008-11-14 Peter Jansen <pwjansen@yahoo.com> | |
1643 | + | |
1644 | + PR 7026 | |
1645 | + * config/tc-arm.c: Ensure that all uses of as_bad have a | |
1646 | + formatting string. | |
1647 | + | |
1648 | +2009-03-04 Alan Modra <amodra@bigpond.net.au> | |
1649 | + | |
1650 | + * config/tc-ppc.c (md_assemble): APUinfo only for e500. | |
1651 | + | |
1652 | +2009-03-02 Alan Modra <amodra@bigpond.net.au> | |
1653 | + | |
1654 | + 2009-02-26 Peter Bergner <bergner@vnet.ibm.com> | |
1655 | + * config/tc-ppc.c (pre_defined_registers): Add "f32" to "f63", | |
1656 | + "f.32" to "f.63", "vs0" to "vs63" and "vs.0" to "vs.63". | |
1657 | + (parse_cpu): Extend -mpower7 to accept power7 and isel instructions. | |
1658 | + | |
1659 | + 2009-01-09 Peter Bergner <bergner@vnet.ibm.com> | |
1660 | + * config/tc-ppc.c (ppc_setup_opcodes): Remove PPC_OPCODE_NOPOWER4 test. | |
1661 | + Test the new "deprecated" opcode field. | |
1662 | + | |
1663 | + 2008-12-04 Ben Elliston <bje@au.ibm.com> | |
1664 | + * config/tc-ppc.c (parse_cpu): Remove booke64 support. Update | |
1665 | + usage strings. | |
1666 | + (ppc_setup_opcodes): Likewise, remove booke64 support. | |
1667 | + * doc/c-ppc.texi (PowerPC-Opts): Remove -mbooke32 and -mbooke64. | |
1668 | + * doc/as.texinfo (Overview): Likewise. | |
1669 | + | |
1670 | + 2008-09-09 Peter Bergner <bergner@vnet.ibm.com> | |
1671 | + * config/tc-ppc.c (ppc_setup_opcodes): Simplify POWER4/NOPOWER4 test. | |
1672 | + Remove POWER5 and POWER6 tests. | |
1673 | + | |
1674 | 2009-01-14 Jakub Jelinek <jakub@redhat.com> | |
1675 | ||
1676 | * Makefile.am (ehopt.o): Add struc-symbol.h. | |
1677 | @@ -132,7 +168,7 @@ | |
1678 | targets. | |
1679 | * doc/c-i386.texi (i386-Directives): New node. Used to document | |
1680 | the .lcomm directive. | |
1681 | - | |
1682 | + | |
1683 | 2008-08-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> | |
1684 | ||
1685 | * config/tc-hppa.h: Don't define DWARF2_EH_FRAME_READ_ONLY on Linux | |
1686 | diff -Naur binutils-2.19.1.orig/gas/config/tc-arm.c binutils-2.19.1/gas/config/tc-arm.c | |
1687 | --- binutils-2.19.1.orig/gas/config/tc-arm.c 2008-08-12 16:39:30.000000000 -0700 | |
1688 | +++ binutils-2.19.1/gas/config/tc-arm.c 2009-04-01 08:47:37.000000000 -0700 | |
1689 | @@ -3456,7 +3456,7 @@ | |
1690 | ||
1691 | if (reg == FAIL) | |
1692 | { | |
1693 | - as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); | |
1694 | + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); | |
1695 | goto error; | |
1696 | } | |
1697 | ||
1698 | @@ -3470,7 +3470,7 @@ | |
1699 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); | |
1700 | if (hi_reg == FAIL) | |
1701 | { | |
1702 | - as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); | |
1703 | + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR])); | |
1704 | goto error; | |
1705 | } | |
1706 | else if (reg >= hi_reg) | |
1707 | @@ -3588,7 +3588,7 @@ | |
1708 | ||
1709 | if (reg == FAIL) | |
1710 | { | |
1711 | - as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
1712 | + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
1713 | goto error; | |
1714 | } | |
1715 | ||
1716 | @@ -3603,7 +3603,7 @@ | |
1717 | hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); | |
1718 | if (hi_reg == FAIL) | |
1719 | { | |
1720 | - as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
1721 | + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG])); | |
1722 | goto error; | |
1723 | } | |
1724 | else if (reg >= hi_reg) | |
1725 | @@ -3709,7 +3709,7 @@ | |
1726 | reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); | |
1727 | if (reg == FAIL) | |
1728 | { | |
1729 | - as_bad (_(reg_expected_msgs[REG_TYPE_RN])); | |
1730 | + as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN])); | |
1731 | ignore_rest_of_line (); | |
1732 | return; | |
1733 | } | |
1734 | diff -Naur binutils-2.19.1.orig/gas/config/tc-ppc.c binutils-2.19.1/gas/config/tc-ppc.c | |
1735 | --- binutils-2.19.1.orig/gas/config/tc-ppc.c 2008-08-01 21:38:50.000000000 -0700 | |
1736 | +++ binutils-2.19.1/gas/config/tc-ppc.c 2009-03-03 15:16:02.000000000 -0800 | |
1737 | @@ -1,6 +1,6 @@ | |
1738 | /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) | |
1739 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, | |
1740 | - 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. | |
1741 | + 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. | |
1742 | Written by Ian Lance Taylor, Cygnus Support. | |
1743 | ||
1744 | This file is part of GAS, the GNU Assembler. | |
1745 | @@ -358,9 +358,42 @@ | |
1746 | { "f.3", 3 }, | |
1747 | { "f.30", 30 }, | |
1748 | { "f.31", 31 }, | |
1749 | + | |
1750 | + { "f.32", 32 }, /* Extended floating point scalar registers (ISA 2.06). */ | |
1751 | + { "f.33", 33 }, | |
1752 | + { "f.34", 34 }, | |
1753 | + { "f.35", 35 }, | |
1754 | + { "f.36", 36 }, | |
1755 | + { "f.37", 37 }, | |
1756 | + { "f.38", 38 }, | |
1757 | + { "f.39", 39 }, | |
1758 | { "f.4", 4 }, | |
1759 | + { "f.40", 40 }, | |
1760 | + { "f.41", 41 }, | |
1761 | + { "f.42", 42 }, | |
1762 | + { "f.43", 43 }, | |
1763 | + { "f.44", 44 }, | |
1764 | + { "f.45", 45 }, | |
1765 | + { "f.46", 46 }, | |
1766 | + { "f.47", 47 }, | |
1767 | + { "f.48", 48 }, | |
1768 | + { "f.49", 49 }, | |
1769 | { "f.5", 5 }, | |
1770 | + { "f.50", 50 }, | |
1771 | + { "f.51", 51 }, | |
1772 | + { "f.52", 52 }, | |
1773 | + { "f.53", 53 }, | |
1774 | + { "f.54", 54 }, | |
1775 | + { "f.55", 55 }, | |
1776 | + { "f.56", 56 }, | |
1777 | + { "f.57", 57 }, | |
1778 | + { "f.58", 58 }, | |
1779 | + { "f.59", 59 }, | |
1780 | { "f.6", 6 }, | |
1781 | + { "f.60", 60 }, | |
1782 | + { "f.61", 61 }, | |
1783 | + { "f.62", 62 }, | |
1784 | + { "f.63", 63 }, | |
1785 | { "f.7", 7 }, | |
1786 | { "f.8", 8 }, | |
1787 | { "f.9", 9 }, | |
1788 | @@ -391,9 +424,42 @@ | |
1789 | { "f3", 3 }, | |
1790 | { "f30", 30 }, | |
1791 | { "f31", 31 }, | |
1792 | + | |
1793 | + { "f32", 32 }, /* Extended floating point scalar registers (ISA 2.06). */ | |
1794 | + { "f33", 33 }, | |
1795 | + { "f34", 34 }, | |
1796 | + { "f35", 35 }, | |
1797 | + { "f36", 36 }, | |
1798 | + { "f37", 37 }, | |
1799 | + { "f38", 38 }, | |
1800 | + { "f39", 39 }, | |
1801 | { "f4", 4 }, | |
1802 | + { "f40", 40 }, | |
1803 | + { "f41", 41 }, | |
1804 | + { "f42", 42 }, | |
1805 | + { "f43", 43 }, | |
1806 | + { "f44", 44 }, | |
1807 | + { "f45", 45 }, | |
1808 | + { "f46", 46 }, | |
1809 | + { "f47", 47 }, | |
1810 | + { "f48", 48 }, | |
1811 | + { "f49", 49 }, | |
1812 | { "f5", 5 }, | |
1813 | + { "f50", 50 }, | |
1814 | + { "f51", 51 }, | |
1815 | + { "f52", 52 }, | |
1816 | + { "f53", 53 }, | |
1817 | + { "f54", 54 }, | |
1818 | + { "f55", 55 }, | |
1819 | + { "f56", 56 }, | |
1820 | + { "f57", 57 }, | |
1821 | + { "f58", 58 }, | |
1822 | + { "f59", 59 }, | |
1823 | { "f6", 6 }, | |
1824 | + { "f60", 60 }, | |
1825 | + { "f61", 61 }, | |
1826 | + { "f62", 62 }, | |
1827 | + { "f63", 63 }, | |
1828 | { "f7", 7 }, | |
1829 | { "f8", 8 }, | |
1830 | { "f9", 9 }, | |
1831 | @@ -501,7 +567,7 @@ | |
1832 | { "srr0", 26 }, /* Machine Status Save/Restore Register 0 */ | |
1833 | { "srr1", 27 }, /* Machine Status Save/Restore Register 1 */ | |
1834 | ||
1835 | - { "v.0", 0 }, /* Vector registers */ | |
1836 | + { "v.0", 0 }, /* Vector (Altivec/VMX) registers */ | |
1837 | { "v.1", 1 }, | |
1838 | { "v.10", 10 }, | |
1839 | { "v.11", 11 }, | |
1840 | @@ -567,6 +633,136 @@ | |
1841 | { "v8", 8 }, | |
1842 | { "v9", 9 }, | |
1843 | ||
1844 | + { "vs.0", 0 }, /* Vector Scalar (VSX) registers (ISA 2.06). */ | |
1845 | + { "vs.1", 1 }, | |
1846 | + { "vs.10", 10 }, | |
1847 | + { "vs.11", 11 }, | |
1848 | + { "vs.12", 12 }, | |
1849 | + { "vs.13", 13 }, | |
1850 | + { "vs.14", 14 }, | |
1851 | + { "vs.15", 15 }, | |
1852 | + { "vs.16", 16 }, | |
1853 | + { "vs.17", 17 }, | |
1854 | + { "vs.18", 18 }, | |
1855 | + { "vs.19", 19 }, | |
1856 | + { "vs.2", 2 }, | |
1857 | + { "vs.20", 20 }, | |
1858 | + { "vs.21", 21 }, | |
1859 | + { "vs.22", 22 }, | |
1860 | + { "vs.23", 23 }, | |
1861 | + { "vs.24", 24 }, | |
1862 | + { "vs.25", 25 }, | |
1863 | + { "vs.26", 26 }, | |
1864 | + { "vs.27", 27 }, | |
1865 | + { "vs.28", 28 }, | |
1866 | + { "vs.29", 29 }, | |
1867 | + { "vs.3", 3 }, | |
1868 | + { "vs.30", 30 }, | |
1869 | + { "vs.31", 31 }, | |
1870 | + { "vs.32", 32 }, | |
1871 | + { "vs.33", 33 }, | |
1872 | + { "vs.34", 34 }, | |
1873 | + { "vs.35", 35 }, | |
1874 | + { "vs.36", 36 }, | |
1875 | + { "vs.37", 37 }, | |
1876 | + { "vs.38", 38 }, | |
1877 | + { "vs.39", 39 }, | |
1878 | + { "vs.4", 4 }, | |
1879 | + { "vs.40", 40 }, | |
1880 | + { "vs.41", 41 }, | |
1881 | + { "vs.42", 42 }, | |
1882 | + { "vs.43", 43 }, | |
1883 | + { "vs.44", 44 }, | |
1884 | + { "vs.45", 45 }, | |
1885 | + { "vs.46", 46 }, | |
1886 | + { "vs.47", 47 }, | |
1887 | + { "vs.48", 48 }, | |
1888 | + { "vs.49", 49 }, | |
1889 | + { "vs.5", 5 }, | |
1890 | + { "vs.50", 50 }, | |
1891 | + { "vs.51", 51 }, | |
1892 | + { "vs.52", 52 }, | |
1893 | + { "vs.53", 53 }, | |
1894 | + { "vs.54", 54 }, | |
1895 | + { "vs.55", 55 }, | |
1896 | + { "vs.56", 56 }, | |
1897 | + { "vs.57", 57 }, | |
1898 | + { "vs.58", 58 }, | |
1899 | + { "vs.59", 59 }, | |
1900 | + { "vs.6", 6 }, | |
1901 | + { "vs.60", 60 }, | |
1902 | + { "vs.61", 61 }, | |
1903 | + { "vs.62", 62 }, | |
1904 | + { "vs.63", 63 }, | |
1905 | + { "vs.7", 7 }, | |
1906 | + { "vs.8", 8 }, | |
1907 | + { "vs.9", 9 }, | |
1908 | + | |
1909 | + { "vs0", 0 }, | |
1910 | + { "vs1", 1 }, | |
1911 | + { "vs10", 10 }, | |
1912 | + { "vs11", 11 }, | |
1913 | + { "vs12", 12 }, | |
1914 | + { "vs13", 13 }, | |
1915 | + { "vs14", 14 }, | |
1916 | + { "vs15", 15 }, | |
1917 | + { "vs16", 16 }, | |
1918 | + { "vs17", 17 }, | |
1919 | + { "vs18", 18 }, | |
1920 | + { "vs19", 19 }, | |
1921 | + { "vs2", 2 }, | |
1922 | + { "vs20", 20 }, | |
1923 | + { "vs21", 21 }, | |
1924 | + { "vs22", 22 }, | |
1925 | + { "vs23", 23 }, | |
1926 | + { "vs24", 24 }, | |
1927 | + { "vs25", 25 }, | |
1928 | + { "vs26", 26 }, | |
1929 | + { "vs27", 27 }, | |
1930 | + { "vs28", 28 }, | |
1931 | + { "vs29", 29 }, | |
1932 | + { "vs3", 3 }, | |
1933 | + { "vs30", 30 }, | |
1934 | + { "vs31", 31 }, | |
1935 | + { "vs32", 32 }, | |
1936 | + { "vs33", 33 }, | |
1937 | + { "vs34", 34 }, | |
1938 | + { "vs35", 35 }, | |
1939 | + { "vs36", 36 }, | |
1940 | + { "vs37", 37 }, | |
1941 | + { "vs38", 38 }, | |
1942 | + { "vs39", 39 }, | |
1943 | + { "vs4", 4 }, | |
1944 | + { "vs40", 40 }, | |
1945 | + { "vs41", 41 }, | |
1946 | + { "vs42", 42 }, | |
1947 | + { "vs43", 43 }, | |
1948 | + { "vs44", 44 }, | |
1949 | + { "vs45", 45 }, | |
1950 | + { "vs46", 46 }, | |
1951 | + { "vs47", 47 }, | |
1952 | + { "vs48", 48 }, | |
1953 | + { "vs49", 49 }, | |
1954 | + { "vs5", 5 }, | |
1955 | + { "vs50", 50 }, | |
1956 | + { "vs51", 51 }, | |
1957 | + { "vs52", 52 }, | |
1958 | + { "vs53", 53 }, | |
1959 | + { "vs54", 54 }, | |
1960 | + { "vs55", 55 }, | |
1961 | + { "vs56", 56 }, | |
1962 | + { "vs57", 57 }, | |
1963 | + { "vs58", 58 }, | |
1964 | + { "vs59", 59 }, | |
1965 | + { "vs6", 6 }, | |
1966 | + { "vs60", 60 }, | |
1967 | + { "vs61", 61 }, | |
1968 | + { "vs62", 62 }, | |
1969 | + { "vs63", 63 }, | |
1970 | + { "vs7", 7 }, | |
1971 | + { "vs8", 8 }, | |
1972 | + { "vs9", 9 }, | |
1973 | + | |
1974 | { "xer", 1 }, | |
1975 | ||
1976 | }; | |
1977 | @@ -919,12 +1115,6 @@ | |
1978 | { | |
1979 | ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32; | |
1980 | } | |
1981 | - /* -mbooke64 means enable 64-bit BookE support. */ | |
1982 | - else if (strcmp (arg, "booke64") == 0) | |
1983 | - { | |
1984 | - ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | |
1985 | - | PPC_OPCODE_BOOKE64 | PPC_OPCODE_64); | |
1986 | - } | |
1987 | else if (strcmp (arg, "power4") == 0) | |
1988 | { | |
1989 | ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | |
1990 | @@ -946,8 +1136,9 @@ | |
1991 | else if (strcmp (arg, "power7") == 0) | |
1992 | { | |
1993 | ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | |
1994 | - | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | |
1995 | - | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
1996 | + | PPC_OPCODE_ISEL | PPC_OPCODE_64 | |
1997 | + | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | |
1998 | + | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | |
1999 | | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX); | |
2000 | } | |
2001 | else if (strcmp (arg, "cell") == 0) | |
2002 | @@ -1149,8 +1340,7 @@ | |
2003 | fprintf (stream, _("\ | |
2004 | -mppc64, -m620 generate code for PowerPC 620/625/630\n\ | |
2005 | -mppc64bridge generate code for PowerPC 64, including bridge insns\n\ | |
2006 | --mbooke64 generate code for 64-bit PowerPC BookE\n\ | |
2007 | --mbooke, mbooke32 generate code for 32-bit PowerPC BookE\n\ | |
2008 | +-mbooke generate code for 32-bit PowerPC BookE\n\ | |
2009 | -mpower4 generate code for Power4 architecture\n\ | |
2010 | -mpower5 generate code for Power5 architecture\n\ | |
2011 | -mpower6 generate code for Power6 architecture\n\ | |
2012 | @@ -1359,8 +1549,7 @@ | |
2013 | ||
2014 | There are also cases where the table needs to be out | |
2015 | of order to disassemble the correct instruction for | |
2016 | - processor variants. eg. "lhae" booke64 insn must be | |
2017 | - found before "ld" ppc64 insn. */ | |
2018 | + processor variants. */ | |
2019 | else if (0) | |
2020 | { | |
2021 | unsigned long t1 = op[0].opcode; | |
2022 | @@ -1420,23 +1609,7 @@ | |
2023 | || ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) | |
2024 | == (ppc_cpu & (PPC_OPCODE_32 | PPC_OPCODE_64))) | |
2025 | || (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0) | |
2026 | - /* Certain instructions (eg: extsw) do not exist in the | |
2027 | - 32-bit BookE instruction set, but they do exist in the | |
2028 | - 64-bit BookE instruction set, and other PPC instruction | |
2029 | - sets. Check to see if the opcode has the BOOKE64 flag set. | |
2030 | - If it does make sure that the target CPU is not the BookE32. */ | |
2031 | - && ((op->flags & PPC_OPCODE_BOOKE64) == 0 | |
2032 | - || (ppc_cpu & PPC_OPCODE_BOOKE64) == PPC_OPCODE_BOOKE64 | |
2033 | - || (ppc_cpu & PPC_OPCODE_BOOKE) == 0) | |
2034 | - && ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0 | |
2035 | - || ((op->flags & PPC_OPCODE_POWER4) | |
2036 | - == (ppc_cpu & PPC_OPCODE_POWER4))) | |
2037 | - && ((op->flags & PPC_OPCODE_POWER5) == 0 | |
2038 | - || ((op->flags & PPC_OPCODE_POWER5) | |
2039 | - == (ppc_cpu & PPC_OPCODE_POWER5))) | |
2040 | - && ((op->flags & PPC_OPCODE_POWER6) == 0 | |
2041 | - || ((op->flags & PPC_OPCODE_POWER6) | |
2042 | - == (ppc_cpu & PPC_OPCODE_POWER6)))) | |
2043 | + && !(ppc_cpu & op->deprecated)) | |
2044 | { | |
2045 | const char *retval; | |
2046 | ||
2047 | @@ -2792,10 +2965,7 @@ | |
2048 | ||
2049 | #ifdef OBJ_ELF | |
2050 | /* Do we need/want a APUinfo section? */ | |
2051 | - if (ppc_cpu & (PPC_OPCODE_SPE | |
2052 | - | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | |
2053 | - | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | |
2054 | - | PPC_OPCODE_RFMCI)) | |
2055 | + if ((ppc_cpu & PPC_OPCODE_E500MC) != 0) | |
2056 | { | |
2057 | /* These are all version "1". */ | |
2058 | if (opcode->flags & PPC_OPCODE_SPE) | |
2059 | diff -Naur binutils-2.19.1.orig/gas/doc/as.texinfo binutils-2.19.1/gas/doc/as.texinfo | |
2060 | --- binutils-2.19.1.orig/gas/doc/as.texinfo 2008-10-02 01:07:17.000000000 -0700 | |
2061 | +++ binutils-2.19.1/gas/doc/as.texinfo 2009-03-02 05:43:14.000000000 -0800 | |
2062 | @@ -409,8 +409,7 @@ | |
2063 | ||
2064 | @emph{Target PowerPC options:} | |
2065 | [@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}| | |
2066 | - @b{-m403}|@b{-m405}|@b{-mppc64}|@b{-m620}|@b{-mppc64bridge}|@b{-mbooke}| | |
2067 | - @b{-mbooke32}|@b{-mbooke64}] | |
2068 | + @b{-m403}|@b{-m405}|@b{-mppc64}|@b{-m620}|@b{-mppc64bridge}|@b{-mbooke}] | |
2069 | [@b{-mcom}|@b{-many}|@b{-maltivec}|@b{-mvsx}] [@b{-memb}] | |
2070 | [@b{-mregnames}|@b{-mno-regnames}] | |
2071 | [@b{-mrelocatable}|@b{-mrelocatable-lib}] | |
2072 | diff -Naur binutils-2.19.1.orig/gas/doc/c-ppc.texi binutils-2.19.1/gas/doc/c-ppc.texi | |
2073 | --- binutils-2.19.1.orig/gas/doc/c-ppc.texi 2008-08-01 21:38:50.000000000 -0700 | |
2074 | +++ binutils-2.19.1/gas/doc/c-ppc.texi 2009-03-02 05:43:14.000000000 -0800 | |
2075 | @@ -70,10 +70,7 @@ | |
2076 | @item -mppc64bridge | |
2077 | Generate code for PowerPC 64, including bridge insns. | |
2078 | ||
2079 | -@item -mbooke64 | |
2080 | -Generate code for 64-bit BookE. | |
2081 | - | |
2082 | -@item -mbooke, mbooke32 | |
2083 | +@item -mbooke | |
2084 | Generate code for 32-bit BookE. | |
2085 | ||
2086 | @item -me300 | |
2087 | diff -Naur binutils-2.19.1.orig/gas/testsuite/ChangeLog binutils-2.19.1/gas/testsuite/ChangeLog | |
2088 | --- binutils-2.19.1.orig/gas/testsuite/ChangeLog 2009-01-14 00:49:59.000000000 -0800 | |
2089 | +++ binutils-2.19.1/gas/testsuite/ChangeLog 2009-03-02 05:59:36.000000000 -0800 | |
2090 | @@ -1,3 +1,56 @@ | |
2091 | +2009-03-02 Alan Modra <amodra@bigpond.net.au> | |
2092 | + | |
2093 | + 2009-02-26 Peter Bergner <bergner@vnet.ibm.com> | |
2094 | + * gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests. | |
2095 | + * gas/ppc/e500mc.s: Likewise. | |
2096 | + * gas/ppc/power6.d ("cdtbcd", "cbcdtd", "addg6s"): Add tests. | |
2097 | + * gas/ppc/power6.s: Likewise. | |
2098 | + * gas/ppc/power7.d ("lfdpx", "mffgpr", "mftgpr"): Remove invalid tests. | |
2099 | + ("wait", "waitsrv", "waitimpl", "divwe", "divwe.", "divweo", "divweo.", | |
2100 | + "divweu", "divweu.", "divweuo", "divweuo.", "bpermd", "popcntw", | |
2101 | + "popcntd", "ldbrx", "stdbrx", "lfiwzx", "lfiwzx", "fcfids", "fcfids.", | |
2102 | + "fcfidus", "fcfidus.", "fctiwu", "fctiwu.", "fctiwuz", "fctiwuz.", | |
2103 | + "fctidu", "fctidu.", "fctiduz", "fctiduz.", "fcfidu", "fcfidu.", | |
2104 | + "ftdiv", "ftdiv", "ftsqrt", "ftsqrt", "dcbtt", "dcbtstt", "dcffix", | |
2105 | + "dcffix.", "lbarx", "lbarx", "lbarx", "lharx", "lharx", "lharx", | |
2106 | + "stbcx.", "sthcx.", "fre", "fre.", "fres", "fres.", "frsqrte", | |
2107 | + "frsqrte.", "frsqrtes", "frsqrtes.", "isel"): Add tests. | |
2108 | + * gas/ppc/power7.s: Likewise. | |
2109 | + * gas/ppc/vsx.d: New test. | |
2110 | + * gas/ppc/vsx.s: Likewise. | |
2111 | + * gas/ppc/ppc.exp: Run it. | |
2112 | + | |
2113 | + 2009-02-19 Peter Bergner <bergner@vnet.ibm.com> | |
2114 | + * gas/ppc/e500mc.d ("lfdepx", "stfdepx"): Fix tests to expect a | |
2115 | + floating point register. | |
2116 | + | |
2117 | + 2009-02-05 Peter Bergner <bergner@vnet.ibm.com> | |
2118 | + * gas/ppc/booke.s ("dcbt", "dcbtst"): New tests. | |
2119 | + * gas/ppc/booke.d: Likewise. | |
2120 | + * gas/ppc/power4_32.s: Likewise. | |
2121 | + * gas/ppc/power4_32.d: Likewise. | |
2122 | + | |
2123 | + 2009-01-14 Peter Bergner <bergner@vnet.ibm.com> | |
2124 | + * gas/ppc/power6.s ("mtfsf", "mtfsf.", "mtfsfi", "mtfsfi."): Add tests. | |
2125 | + * gas/ppc/power6.d: Likewise. | |
2126 | + | |
2127 | + 2008-12-04 Ben Elliston <bje@au.ibm.com> | |
2128 | + * gas/ppc/booke.s: Remove booke64 instructions. | |
2129 | + * gas/ppc/booke.d: Update expected disassembly output. | |
2130 | + * gas/ppc/booke_xcoff.s: Use -mbooke/-Mbooke. | |
2131 | + * gas/ppc/booke_xcoff.d: Likewise. | |
2132 | + * gas/ppc/booke_xcoff64.d: Likewise. | |
2133 | + * gas/ppc/booke_xcoff64.s: Likewise. | |
2134 | + | |
2135 | + 2008-09-09 Peter Bergner <bergner@vnet.ibm.com> | |
2136 | + * gas/ppc/common.s: New test. | |
2137 | + * gas/ppc/common.d: Likewise. | |
2138 | + * gas/ppc/power4_32.s: Likewise. | |
2139 | + * gas/ppc/power4_32.d: Likewise. | |
2140 | + * gas/ppc/power6.s: Add attn, mtcr, mtcrf, mfcr, dcbz. | |
2141 | + * gas/ppc/power6.d: Likewise. | |
2142 | + * gas/ppc/ppc.exp: Run power4_32 test. | |
2143 | + | |
2144 | 2009-01-08 Adam Nemet <anemet@caviumnetworks.com> | |
2145 | ||
2146 | * gas/mips/mips1-fp.s, gas/mips/mips1-fp.d, gas/mips/mips1-fp.l: | |
2147 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke.d binutils-2.19.1/gas/testsuite/gas/ppc/booke.d | |
2148 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke.d 2007-04-18 16:58:12.000000000 -0700 | |
2149 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/booke.d 2009-03-02 05:54:22.000000000 -0800 | |
2150 | @@ -1,4 +1,4 @@ | |
2151 | -#as: -mbooke64 | |
2152 | +#as: -mbooke | |
2153 | #objdump: -dr -Mbooke | |
2154 | #name: BookE tests | |
2155 | ||
2156 | @@ -6,151 +6,38 @@ | |
2157 | ||
2158 | Disassembly of section \.text: | |
2159 | ||
2160 | -0+0000000 <start>: | |
2161 | - 0: 24 25 00 30 bce 1,4\*cr1\+gt,30 <branch_target_1> | |
2162 | - 4: 24 46 00 3d bcel 2,4\*cr1\+eq,40 <branch_target_2> | |
2163 | - 8: 24 67 00 52 bcea 3,4\*cr1\+so,50 <branch_target_3> | |
2164 | - 8: R_PPC(64)?_ADDR14 \.text\+0x50 | |
2165 | - c: 24 88 00 73 bcela 4,4\*cr2\+lt,70 <branch_target_4> | |
2166 | - c: R_PPC(64)?_ADDR14 \.text\+0x70 | |
2167 | - 10: 4c a9 00 22 bclre 5,4\*cr2\+gt | |
2168 | - 14: 4c aa 00 23 bclrel 5,4\*cr2\+eq | |
2169 | - 18: 4d 0b 04 22 bcctre 8,4\*cr2\+so | |
2170 | - 1c: 4d 0c 04 23 bcctrel 8,4\*cr3\+lt | |
2171 | - 20: 58 00 00 74 be 94 <branch_target_5> | |
2172 | - 24: 58 00 00 89 bel ac <branch_target_6> | |
2173 | - 28: 58 00 00 f6 bea f4 <branch_target_7> | |
2174 | - 28: R_PPC(64)?_ADDR24 \.text\+0xf4 | |
2175 | - 2c: 58 00 01 2b bela 128 <branch_target_8> | |
2176 | - 2c: R_PPC(64)?_ADDR24 \.text\+0x128 | |
2177 | - | |
2178 | -0+0000030 <branch_target_1>: | |
2179 | - 30: e9 09 00 80 lbze r8,8\(r9\) | |
2180 | - 34: e9 8f 00 41 lbzue r12,4\(r15\) | |
2181 | - 38: 7c 86 40 fe lbzuxe r4,r6,r8 | |
2182 | - 3c: 7c 65 38 be lbzxe r3,r5,r7 | |
2183 | - | |
2184 | -0+0000040 <branch_target_2>: | |
2185 | - 40: f8 a6 06 40 lde r5,400\(r6\) | |
2186 | - 44: f8 c7 07 11 ldue r6,452\(r7\) | |
2187 | - 48: 7c e8 4e 3e ldxe r7,r8,r9 | |
2188 | - 4c: 7d 4b 66 7e lduxe r10,r11,r12 | |
2189 | - | |
2190 | -0+0000050 <branch_target_3>: | |
2191 | - 50: f9 81 02 06 lfde f12,128\(r1\) | |
2192 | - 54: f8 25 00 47 lfdue f1,16\(r5\) | |
2193 | - 58: 7c a1 1c be lfdxe f5,r1,r3 | |
2194 | - 5c: 7c c2 24 fe lfduxe f6,r2,r4 | |
2195 | - 60: f9 09 00 c4 lfse f8,48\(r9\) | |
2196 | - 64: f9 2a 01 15 lfsue f9,68\(r10\) | |
2197 | - 68: 7d 44 44 7e lfsuxe f10,r4,r8 | |
2198 | - 6c: 7d 23 3c 3e lfsxe f9,r3,r7 | |
2199 | - | |
2200 | -0+0000070 <branch_target_4>: | |
2201 | - 70: e9 45 03 24 lhae r10,50\(r5\) | |
2202 | - 74: e8 23 00 55 lhaue r1,5\(r3\) | |
2203 | - 78: 7c a1 1a fe lhauxe r5,r1,r3 | |
2204 | - 7c: 7f be fa be lhaxe r29,r30,r31 | |
2205 | - 80: 7c 22 1e 3c lhbrxe r1,r2,r3 | |
2206 | - 84: e8 83 01 22 lhze r4,18\(r3\) | |
2207 | - 88: e8 c9 01 43 lhzue r6,20\(r9\) | |
2208 | - 8c: 7c a7 4a 7e lhzuxe r5,r7,r9 | |
2209 | - 90: 7d 27 2a 3e lhzxe r9,r7,r5 | |
2210 | - | |
2211 | -0+0000094 <branch_target_5>: | |
2212 | - 94: 7d 4f a0 fc lwarxe r10,r15,r20 | |
2213 | - 98: 7c aa 94 3c lwbrxe r5,r10,r18 | |
2214 | - 9c: eb 9d 00 46 lwze r28,4\(r29\) | |
2215 | - a0: e9 0a 02 87 lwzue r8,40\(r10\) | |
2216 | - a4: 7c 66 48 7e lwzuxe r3,r6,r9 | |
2217 | - a8: 7f dd e0 3e lwzxe r30,r29,r28 | |
2218 | - | |
2219 | -0+00000ac <branch_target_6>: | |
2220 | - ac: 7c 06 3d fc dcbae r6,r7 | |
2221 | - b0: 7c 08 48 bc dcbfe r8,r9 | |
2222 | - b4: 7c 0a 5b bc dcbie r10,r11 | |
2223 | - b8: 7c 08 f0 7c dcbste r8,r30 | |
2224 | - bc: 7c c3 0a 3c dcbte 6,r3,r1 | |
2225 | - c0: 7c a4 11 fa dcbtste 5,r4,r2 | |
2226 | - c4: 7c 0f 77 fc dcbze r15,r14 | |
2227 | - c8: 7c 03 27 bc icbie r3,r4 | |
2228 | - cc: 7c a8 48 2c icbt 5,r8,r9 | |
2229 | - d0: 7c ca 78 3c icbte 6,r10,r15 | |
2230 | - d4: 7c a6 02 26 mfapidi r5,r6 | |
2231 | - d8: 7c 07 46 24 tlbivax r7,r8 | |
2232 | - dc: 7c 09 56 26 tlbivaxe r9,r10 | |
2233 | - e0: 7c 0b 67 24 tlbsx r11,r12 | |
2234 | - e4: 7c 0d 77 26 tlbsxe r13,r14 | |
2235 | - e8: 7c 00 07 a4 tlbwe | |
2236 | - ec: 7c 00 07 a4 tlbwe | |
2237 | - f0: 7c 21 0f a4 tlbwe r1,r1,1 | |
2238 | - | |
2239 | -0+00000f4 <branch_target_7>: | |
2240 | - f4: 7c 22 1b 14 adde64 r1,r2,r3 | |
2241 | - f8: 7c 85 37 14 adde64o r4,r5,r6 | |
2242 | - fc: 7c e8 03 d4 addme64 r7,r8 | |
2243 | - 100: 7d 2a 07 d4 addme64o r9,r10 | |
2244 | - 104: 7d 6c 03 94 addze64 r11,r12 | |
2245 | - 108: 7d ae 07 94 addze64o r13,r14 | |
2246 | - 10c: 7e 80 04 40 mcrxr64 cr5 | |
2247 | - 110: 7d f0 8b 10 subfe64 r15,r16,r17 | |
2248 | - 114: 7e 53 a7 10 subfe64o r18,r19,r20 | |
2249 | - 118: 7e b6 03 d0 subfme64 r21,r22 | |
2250 | - 11c: 7e f8 07 d0 subfme64o r23,r24 | |
2251 | - 120: 7f 3a 03 90 subfze64 r25,r26 | |
2252 | - 124: 7f 7c 07 90 subfze64o r27,r28 | |
2253 | - | |
2254 | -0+0000128 <branch_target_8>: | |
2255 | - 128: e8 22 03 28 stbe r1,50\(r2\) | |
2256 | - 12c: e8 64 02 89 stbue r3,40\(r4\) | |
2257 | - 130: 7c a6 39 fe stbuxe r5,r6,r7 | |
2258 | - 134: 7d 09 51 be stbxe r8,r9,r10 | |
2259 | - 138: 7d 6c 6b ff stdcxe\. r11,r12,r13 | |
2260 | - 13c: f9 cf 00 78 stde r14,28\(r15\) | |
2261 | - 140: fa 11 00 59 stdue r16,20\(r17\) | |
2262 | - 144: 7e 53 a7 3e stdxe r18,r19,r20 | |
2263 | - 148: 7e b6 bf 7e stduxe r21,r22,r23 | |
2264 | - 14c: f8 38 00 3e stfde f1,12\(r24\) | |
2265 | - 150: f8 59 00 0f stfdue f2,0\(r25\) | |
2266 | - 154: 7c 7a dd be stfdxe f3,r26,r27 | |
2267 | - 158: 7c 9c ed fe stfduxe f4,r28,r29 | |
2268 | - 15c: 7c be ff be stfiwxe f5,r30,r31 | |
2269 | - 160: f8 de 00 6c stfse f6,24\(r30\) | |
2270 | - 164: f8 fd 00 5d stfsue f7,20\(r29\) | |
2271 | - 168: 7d 1c dd 3e stfsxe f8,r28,r27 | |
2272 | - 16c: 7d 3a cd 7e stfsuxe f9,r26,r25 | |
2273 | - 170: 7f 17 b7 3c sthbrxe r24,r23,r22 | |
2274 | - 174: ea b4 01 ea sthe r21,30\(r20\) | |
2275 | - 178: ea 72 02 8b sthue r19,40\(r18\) | |
2276 | - 17c: 7e 30 7b 7e sthuxe r17,r16,r15 | |
2277 | - 180: 7d cd 63 3e sthxe r14,r13,r12 | |
2278 | - 184: 7d 6a 4d 3c stwbrxe r11,r10,r9 | |
2279 | - 188: 7d 07 31 3d stwcxe\. r8,r7,r6 | |
2280 | - 18c: e8 a4 03 2e stwe r5,50\(r4\) | |
2281 | - 190: e8 62 02 8f stwue r3,40\(r2\) | |
2282 | - 194: 7c 22 19 7e stwuxe r1,r2,r3 | |
2283 | - 198: 7c 85 31 3e stwxe r4,r5,r6 | |
2284 | - 19c: 4c 00 00 66 rfci | |
2285 | - 1a0: 7c 60 01 06 wrtee r3 | |
2286 | - 1a4: 7c 00 81 46 wrteei 1 | |
2287 | - 1a8: 7c 85 02 06 mfdcrx r4,r5 | |
2288 | - 1ac: 7c aa 3a 86 mfdcr r5,234 | |
2289 | - 1b0: 7c e6 03 06 mtdcrx r6,r7 | |
2290 | - 1b4: 7d 10 6b 86 mtdcr 432,r8 | |
2291 | - 1b8: 7c 00 04 ac msync | |
2292 | - 1bc: 7c 09 55 ec dcba r9,r10 | |
2293 | - 1c0: 7c 00 06 ac mbar | |
2294 | - 1c4: 7c 00 06 ac mbar | |
2295 | - 1c8: 7c 20 06 ac mbar 1 | |
2296 | - 1cc: 7d 8d 77 24 tlbsx r12,r13,r14 | |
2297 | - 1d0: 7d 8d 77 25 tlbsx\. r12,r13,r14 | |
2298 | - 1d4: 7d 8d 77 26 tlbsxe r12,r13,r14 | |
2299 | - 1d8: 7d 8d 77 27 tlbsxe\. r12,r13,r14 | |
2300 | - 1dc: 7c 12 42 a6 mfsprg r0,2 | |
2301 | - 1e0: 7c 12 42 a6 mfsprg r0,2 | |
2302 | - 1e4: 7c 12 43 a6 mtsprg 2,r0 | |
2303 | - 1e8: 7c 12 43 a6 mtsprg 2,r0 | |
2304 | - 1ec: 7c 07 42 a6 mfsprg r0,7 | |
2305 | - 1f0: 7c 07 42 a6 mfsprg r0,7 | |
2306 | - 1f4: 7c 17 43 a6 mtsprg 7,r0 | |
2307 | - 1f8: 7c 17 43 a6 mtsprg 7,r0 | |
2308 | +0+0000000 <branch_target_1>: | |
2309 | + 0: 7c a8 48 2c icbt 5,r8,r9 | |
2310 | + 4: 7c a6 02 26 mfapidi r5,r6 | |
2311 | + 8: 7c 07 46 24 tlbivax r7,r8 | |
2312 | + c: 7c 0b 67 24 tlbsx r11,r12 | |
2313 | + 10: 7c 00 07 a4 tlbwe | |
2314 | + 14: 7c 00 07 a4 tlbwe | |
2315 | + 18: 7c 21 0f a4 tlbwe r1,r1,1 | |
2316 | + | |
2317 | +0+000001c <branch_target_2>: | |
2318 | + 1c: 4c 00 00 66 rfci | |
2319 | + 20: 7c 60 01 06 wrtee r3 | |
2320 | + 24: 7c 00 81 46 wrteei 1 | |
2321 | + 28: 7c 85 02 06 mfdcrx r4,r5 | |
2322 | + 2c: 7c aa 3a 86 mfdcr r5,234 | |
2323 | + 30: 7c e6 03 06 mtdcrx r6,r7 | |
2324 | + 34: 7d 10 6b 86 mtdcr 432,r8 | |
2325 | + 38: 7c 00 04 ac msync | |
2326 | + 3c: 7c 09 55 ec dcba r9,r10 | |
2327 | + 40: 7c 00 06 ac mbar | |
2328 | + 44: 7c 00 06 ac mbar | |
2329 | + 48: 7c 20 06 ac mbar 1 | |
2330 | + 4c: 7d 8d 77 24 tlbsx r12,r13,r14 | |
2331 | + 50: 7d 8d 77 25 tlbsx\. r12,r13,r14 | |
2332 | + 54: 7c 12 42 a6 mfsprg r0,2 | |
2333 | + 58: 7c 12 42 a6 mfsprg r0,2 | |
2334 | + 5c: 7c 12 43 a6 mtsprg 2,r0 | |
2335 | + 60: 7c 12 43 a6 mtsprg 2,r0 | |
2336 | + 64: 7c 07 42 a6 mfsprg r0,7 | |
2337 | + 68: 7c 07 42 a6 mfsprg r0,7 | |
2338 | + 6c: 7c 17 43 a6 mtsprg 7,r0 | |
2339 | + 70: 7c 17 43 a6 mtsprg 7,r0 | |
2340 | + 74: 7c 05 32 2c dcbt r5,r6 | |
2341 | + 78: 7c 05 32 2c dcbt r5,r6 | |
2342 | + 7c: 7d 05 32 2c dcbt 8,r5,r6 | |
2343 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke.s binutils-2.19.1/gas/testsuite/gas/ppc/booke.s | |
2344 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke.s 2007-04-18 16:58:12.000000000 -0700 | |
2345 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/booke.s 2009-03-02 05:54:22.000000000 -0800 | |
2346 | @@ -1,127 +1,17 @@ | |
2347 | # Motorola PowerPC BookE tests | |
2348 | -#as: -mbooke32 | |
2349 | +#as: -mbooke | |
2350 | .section ".text" | |
2351 | -start: | |
2352 | - bce 1, 5, branch_target_1 | |
2353 | - bcel 2, 6, branch_target_2 | |
2354 | - bcea 3, 7, branch_target_3 | |
2355 | - bcela 4, 8, branch_target_4 | |
2356 | - bclre 5, 9 | |
2357 | - bclrel 5, 10 | |
2358 | - bcctre 8, 11 | |
2359 | - bcctrel 8, 12 | |
2360 | - be branch_target_5 | |
2361 | - bel branch_target_6 | |
2362 | - bea branch_target_7 | |
2363 | - bela branch_target_8 | |
2364 | ||
2365 | -branch_target_1: | |
2366 | - lbze 8, 8(9) | |
2367 | - lbzue 12, 4(15) | |
2368 | - lbzuxe 4, 6, 8 | |
2369 | - lbzxe 3, 5, 7 | |
2370 | - | |
2371 | -branch_target_2: | |
2372 | - lde 5, 400(6) | |
2373 | - ldue 6, 452(7) | |
2374 | - ldxe 7, 8, 9 | |
2375 | - lduxe 10, 11, 12 | |
2376 | - | |
2377 | -branch_target_3: | |
2378 | - lfde 12, 128(1) | |
2379 | - lfdue 1, 16(5) | |
2380 | - lfdxe 5, 1, 3 | |
2381 | - lfduxe 6, 2, 4 | |
2382 | - lfse 8, 48(9) | |
2383 | - lfsue 9, 68(10) | |
2384 | - lfsuxe 10, 4, 8 | |
2385 | - lfsxe 9, 3, 7 | |
2386 | - | |
2387 | -branch_target_4: | |
2388 | - lhae 10, 50(5) | |
2389 | - lhaue 1, 5(3) | |
2390 | - lhauxe 5, 1, 3 | |
2391 | - lhaxe 29, 30, 31 | |
2392 | - lhbrxe 1, 2, 3 | |
2393 | - lhze 4, 18(3) | |
2394 | - lhzue 6, 20(9) | |
2395 | - lhzuxe 5, 7, 9 | |
2396 | - lhzxe 9, 7, 5 | |
2397 | - | |
2398 | -branch_target_5: | |
2399 | - lwarxe 10, 15, 20 | |
2400 | - lwbrxe 5, 10, 18 | |
2401 | - lwze 28, 4(29) | |
2402 | - lwzue 8, 40(10) | |
2403 | - lwzuxe 3, 6, 9 | |
2404 | - lwzxe 30, 29, 28 | |
2405 | - | |
2406 | -branch_target_6: | |
2407 | - dcbae 6, 7 | |
2408 | - dcbfe 8, 9 | |
2409 | - dcbie 10, 11 | |
2410 | - dcbste 8, 30 | |
2411 | - dcbte 6, 3, 1 | |
2412 | - dcbtste 5, 4, 2 | |
2413 | - dcbze 15, 14 | |
2414 | - icbie 3, 4 | |
2415 | +branch_target_1: | |
2416 | icbt 5, 8, 9 | |
2417 | - icbte 6, 10, 15 | |
2418 | mfapidi 5, 6 | |
2419 | tlbivax 7, 8 | |
2420 | - tlbivaxe 9, 10 | |
2421 | tlbsx 11, 12 | |
2422 | - tlbsxe 13, 14 | |
2423 | tlbwe | |
2424 | tlbwe 0,0,0 | |
2425 | tlbwe 1,1,1 | |
2426 | ||
2427 | -branch_target_7: | |
2428 | - adde64 1, 2, 3 | |
2429 | - adde64o 4, 5, 6 | |
2430 | - addme64 7, 8 | |
2431 | - addme64o 9, 10 | |
2432 | - addze64 11, 12 | |
2433 | - addze64o 13, 14 | |
2434 | - mcrxr64 5 | |
2435 | - subfe64 15, 16, 17 | |
2436 | - subfe64o 18, 19, 20 | |
2437 | - subfme64 21, 22 | |
2438 | - subfme64o 23, 24 | |
2439 | - subfze64 25, 26 | |
2440 | - subfze64o 27, 28 | |
2441 | - | |
2442 | -branch_target_8: | |
2443 | - stbe 1, 50(2) | |
2444 | - stbue 3, 40(4) | |
2445 | - stbuxe 5, 6, 7 | |
2446 | - stbxe 8, 9, 10 | |
2447 | - stdcxe. 11, 12, 13 | |
2448 | - stde 14, 28(15) | |
2449 | - stdue 16, 20(17) | |
2450 | - stdxe 18, 19, 20 | |
2451 | - stduxe 21, 22, 23 | |
2452 | - stfde 1, 12(24) | |
2453 | - stfdue 2, 0(25) | |
2454 | - stfdxe 3, 26, 27 | |
2455 | - stfduxe 4, 28, 29 | |
2456 | - stfiwxe 5, 30, 31 | |
2457 | - stfse 6, 24(30) | |
2458 | - stfsue 7, 20(29) | |
2459 | - stfsxe 8, 28, 27 | |
2460 | - stfsuxe 9, 26, 25 | |
2461 | - sthbrxe 24, 23, 22 | |
2462 | - sthe 21, 30(20) | |
2463 | - sthue 19, 40(18) | |
2464 | - sthuxe 17, 16, 15 | |
2465 | - sthxe 14, 13, 12 | |
2466 | - stwbrxe 11, 10, 9 | |
2467 | - stwcxe. 8, 7, 6 | |
2468 | - stwe 5, 50(4) | |
2469 | - stwue 3, 40(2) | |
2470 | - stwuxe 1, 2, 3 | |
2471 | - stwxe 4, 5, 6 | |
2472 | - | |
2473 | +branch_target_2: | |
2474 | rfci | |
2475 | wrtee 3 | |
2476 | wrteei 1 | |
2477 | @@ -137,8 +27,6 @@ | |
2478 | ||
2479 | tlbsx 12, 13, 14 | |
2480 | tlbsx. 12, 13, 14 | |
2481 | - tlbsxe 12, 13, 14 | |
2482 | - tlbsxe. 12, 13, 14 | |
2483 | ||
2484 | mfsprg 0, 2 | |
2485 | mfsprg2 0 | |
2486 | @@ -148,3 +36,7 @@ | |
2487 | mfsprg7 0 | |
2488 | mtsprg 7, 0 | |
2489 | mtsprg7 0 | |
2490 | + | |
2491 | + dcbt 5,6 | |
2492 | + dcbt 0,5,6 | |
2493 | + dcbt 8,5,6 | |
2494 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff64.d binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff64.d | |
2495 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff64.d 2007-10-01 09:24:40.000000000 -0700 | |
2496 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff64.d 2009-03-02 05:43:14.000000000 -0800 | |
2497 | @@ -1,5 +1,5 @@ | |
2498 | -#as: -a64 -mppc64 -mbooke64 | |
2499 | -#objdump: -dr -Mbooke64 | |
2500 | +#as: -a64 -mppc64 -mbooke | |
2501 | +#objdump: -dr -Mbooke | |
2502 | #name: xcoff64 BookE tests | |
2503 | ||
2504 | .*: file format aix5?coff64-rs6000 | |
2505 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff64.s binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff64.s | |
2506 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff64.s 2007-10-01 09:24:40.000000000 -0700 | |
2507 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff64.s 2009-03-02 05:43:15.000000000 -0800 | |
2508 | @@ -1,5 +1,5 @@ | |
2509 | # Motorola PowerPC BookE tests | |
2510 | -#as: -a64 -mppc64 -mbooke64 | |
2511 | +#as: -a64 -mppc64 -mbooke | |
2512 | .csect .text[PR] | |
2513 | .csect main[DS] | |
2514 | main: | |
2515 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff.d binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff.d | |
2516 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff.d 2007-10-01 09:24:40.000000000 -0700 | |
2517 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff.d 2009-03-02 05:43:14.000000000 -0800 | |
2518 | @@ -1,5 +1,5 @@ | |
2519 | -#as: -mppc32 -mbooke32 | |
2520 | -#objdump: -mpowerpc -dr -Mbooke32 | |
2521 | +#as: -mppc32 -mbooke | |
2522 | +#objdump: -mpowerpc -dr -Mbooke | |
2523 | #name: xcoff BookE tests | |
2524 | ||
2525 | .*: file format aixcoff-rs6000 | |
2526 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff.s binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff.s | |
2527 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/booke_xcoff.s 2007-10-01 09:24:40.000000000 -0700 | |
2528 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/booke_xcoff.s 2009-03-02 05:43:14.000000000 -0800 | |
2529 | @@ -1,5 +1,5 @@ | |
2530 | # Motorola PowerPC BookE tests | |
2531 | -#as: -mbooke32 | |
2532 | +#as: -mbooke | |
2533 | .csect .text[PR] | |
2534 | .csect main[DS] | |
2535 | main: | |
2536 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/common.d binutils-2.19.1/gas/testsuite/gas/ppc/common.d | |
2537 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/common.d 1969-12-31 16:00:00.000000000 -0800 | |
2538 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/common.d 2009-03-02 05:37:44.000000000 -0800 | |
2539 | @@ -0,0 +1,190 @@ | |
2540 | +#objdump: -d -Mcom | |
2541 | +#as: -a32 -mcom | |
2542 | +#name: PowerPC COMMON instructions | |
2543 | + | |
2544 | +.*: +file format elf32-powerpc.* | |
2545 | + | |
2546 | +Disassembly of section \.text: | |
2547 | + | |
2548 | +0+00 <start>: | |
2549 | + | |
2550 | + 0: 7c 83 28 39 and. r3,r4,r5 | |
2551 | + 4: 7c 83 28 38 and r3,r4,r5 | |
2552 | + 8: 7d cd 78 78 andc r13,r14,r15 | |
2553 | + c: 7e 30 90 79 andc. r16,r17,r18 | |
2554 | + 10: 48 00 00 02 ba 0 <start> | |
2555 | + 14: 40 01 00 00 bdnzf- gt,14 <start\+0x14> | |
2556 | + 18: 40 85 00 02 blea- cr1,0 <start> | |
2557 | + 1c: 40 43 00 01 bdzfl- so,1c <start\+0x1c> | |
2558 | + 20: 41 47 00 03 bdztla- 4\*cr1\+so,0 <start> | |
2559 | + 24: 4e 80 04 20 bctr | |
2560 | + 28: 4e 80 04 21 bctrl | |
2561 | + 2c: 42 40 00 02 bdza- 0 <start> | |
2562 | + 30: 42 40 00 00 bdz- 30 <start\+0x30> | |
2563 | + 34: 42 40 00 03 bdzla- 0 <start> | |
2564 | + 38: 42 40 00 01 bdzl- 38 <start\+0x38> | |
2565 | + 3c: 41 82 00 00 beq- 3c <start\+0x3c> | |
2566 | + 40: 41 8a 00 02 beqa- cr2,0 <start> | |
2567 | + 44: 41 86 00 01 beql- cr1,44 <start\+0x44> | |
2568 | + 48: 41 8e 00 03 beqla- cr3,0 <start> | |
2569 | + 4c: 40 80 00 00 bge- 4c <start\+0x4c> | |
2570 | + 50: 40 90 00 02 bgea- cr4,0 <start> | |
2571 | + 54: 40 88 00 01 bgel- cr2,54 <start\+0x54> | |
2572 | + 58: 40 98 00 03 bgela- cr6,0 <start> | |
2573 | + 5c: 41 91 00 00 bgt- cr4,5c <start\+0x5c> | |
2574 | + 60: 41 99 00 02 bgta- cr6,0 <start> | |
2575 | + 64: 41 95 00 01 bgtl- cr5,64 <start\+0x64> | |
2576 | + 68: 41 9d 00 03 bgtla- cr7,0 <start> | |
2577 | + 6c: 48 00 00 00 b 6c <start\+0x6c> | |
2578 | + 70: 48 00 00 03 bla 0 <start> | |
2579 | + 74: 40 81 00 00 ble- 74 <start\+0x74> | |
2580 | + 78: 40 91 00 02 blea- cr4,0 <start> | |
2581 | + 7c: 40 89 00 01 blel- cr2,7c <start\+0x7c> | |
2582 | + 80: 40 99 00 03 blela- cr6,0 <start> | |
2583 | + 84: 48 00 00 01 bl 84 <start\+0x84> | |
2584 | + 88: 41 80 00 00 blt- 88 <start\+0x88> | |
2585 | + 8c: 41 88 00 02 blta- cr2,0 <start> | |
2586 | + 90: 41 84 00 01 bltl- cr1,90 <start\+0x90> | |
2587 | + 94: 41 8c 00 03 bltla- cr3,0 <start> | |
2588 | + 98: 40 82 00 00 bne- 98 <start\+0x98> | |
2589 | + 9c: 40 8a 00 02 bnea- cr2,0 <start> | |
2590 | + a0: 40 86 00 01 bnel- cr1,a0 <start\+0xa0> | |
2591 | + a4: 40 8e 00 03 bnela- cr3,0 <start> | |
2592 | + a8: 40 85 00 00 ble- cr1,a8 <start\+0xa8> | |
2593 | + ac: 40 95 00 02 blea- cr5,0 <start> | |
2594 | + b0: 40 8d 00 01 blel- cr3,b0 <start\+0xb0> | |
2595 | + b4: 40 9d 00 03 blela- cr7,0 <start> | |
2596 | + b8: 40 84 00 00 bge- cr1,b8 <start\+0xb8> | |
2597 | + bc: 40 94 00 02 bgea- cr5,0 <start> | |
2598 | + c0: 40 8c 00 01 bgel- cr3,c0 <start\+0xc0> | |
2599 | + c4: 40 9c 00 03 bgela- cr7,0 <start> | |
2600 | + c8: 40 93 00 00 bns- cr4,c8 <start\+0xc8> | |
2601 | + cc: 40 9b 00 02 bnsa- cr6,0 <start> | |
2602 | + d0: 40 97 00 01 bnsl- cr5,d0 <start\+0xd0> | |
2603 | + d4: 40 9f 00 03 bnsla- cr7,0 <start> | |
2604 | + d8: 41 93 00 00 bso- cr4,d8 <start\+0xd8> | |
2605 | + dc: 41 9b 00 02 bsoa- cr6,0 <start> | |
2606 | + e0: 41 97 00 01 bsol- cr5,e0 <start\+0xe0> | |
2607 | + e4: 41 9f 00 03 bsola- cr7,0 <start> | |
2608 | + e8: 4c 85 32 02 crand 4\*cr1\+lt,4\*cr1\+gt,4\*cr1\+eq | |
2609 | + ec: 4c 64 29 02 crandc so,4\*cr1\+lt,4\*cr1\+gt | |
2610 | + f0: 4c e0 0a 42 creqv 4\*cr1\+so,lt,gt | |
2611 | + f4: 4c 22 19 c2 crnand gt,eq,so | |
2612 | + f8: 4c 01 10 42 crnor lt,gt,eq | |
2613 | + fc: 4c a6 3b 82 cror 4\*cr1\+gt,4\*cr1\+eq,4\*cr1\+so | |
2614 | + 100: 4c 43 23 42 crorc eq,so,4\*cr1\+lt | |
2615 | + 104: 4c c7 01 82 crxor 4\*cr1\+eq,4\*cr1\+so,lt | |
2616 | + 108: 7d 6a 62 39 eqv. r10,r11,r12 | |
2617 | + 10c: 7d 6a 62 38 eqv r10,r11,r12 | |
2618 | + 110: fe a0 fa 11 fabs. f21,f31 | |
2619 | + 114: fe a0 fa 10 fabs f21,f31 | |
2620 | + 118: fd 8a 58 40 fcmpo cr3,f10,f11 | |
2621 | + 11c: fd 84 28 00 fcmpu cr3,f4,f5 | |
2622 | + 120: fc 60 20 91 fmr. f3,f4 | |
2623 | + 124: fc 60 20 90 fmr f3,f4 | |
2624 | + 128: fe 80 f1 11 fnabs. f20,f30 | |
2625 | + 12c: fe 80 f1 10 fnabs f20,f30 | |
2626 | + 130: fc 60 20 51 fneg. f3,f4 | |
2627 | + 134: fc 60 20 50 fneg f3,f4 | |
2628 | + 138: fc c0 38 18 frsp f6,f7 | |
2629 | + 13c: fd 00 48 19 frsp. f8,f9 | |
2630 | + 140: 89 21 00 00 lbz r9,0\(r1\) | |
2631 | + 144: 8d 41 00 01 lbzu r10,1\(r1\) | |
2632 | + 148: 7e 95 b0 ee lbzux r20,r21,r22 | |
2633 | + 14c: 7c 64 28 ae lbzx r3,r4,r5 | |
2634 | + 150: ca a1 00 08 lfd f21,8\(r1\) | |
2635 | + 154: ce c1 00 10 lfdu f22,16\(r1\) | |
2636 | + 158: 7e 95 b4 ee lfdux f20,r21,r22 | |
2637 | + 15c: 7d ae 7c ae lfdx f13,r14,r15 | |
2638 | + 160: c2 61 00 00 lfs f19,0\(r1\) | |
2639 | + 164: c6 81 00 04 lfsu f20,4\(r1\) | |
2640 | + 168: 7d 4b 64 6e lfsux f10,r11,r12 | |
2641 | + 16c: 7d 4b 64 2e lfsx f10,r11,r12 | |
2642 | + 170: a9 e1 00 06 lha r15,6\(r1\) | |
2643 | + 174: ae 01 00 08 lhau r16,8\(r1\) | |
2644 | + 178: 7d 2a 5a ee lhaux r9,r10,r11 | |
2645 | + 17c: 7d 2a 5a ae lhax r9,r10,r11 | |
2646 | + 180: 7c 64 2e 2c lhbrx r3,r4,r5 | |
2647 | + 184: a1 a1 00 00 lhz r13,0\(r1\) | |
2648 | + 188: a5 c1 00 02 lhzu r14,2\(r1\) | |
2649 | + 18c: 7e 96 c2 6e lhzux r20,r22,r24 | |
2650 | + 190: 7e f8 ca 2e lhzx r23,r24,r25 | |
2651 | + 194: 4c 04 00 00 mcrf cr0,cr1 | |
2652 | + 198: fd 90 00 80 mcrfs cr3,cr4 | |
2653 | + 19c: 7d 80 04 00 mcrxr cr3 | |
2654 | + 1a0: 7c 60 00 26 mfcr r3 | |
2655 | + 1a4: 7c 69 02 a6 mfctr r3 | |
2656 | + 1a8: 7c b3 02 a6 mfdar r5 | |
2657 | + 1ac: 7c 92 02 a6 mfdsisr r4 | |
2658 | + 1b0: ff c0 04 8e mffs f30 | |
2659 | + 1b4: ff e0 04 8f mffs. f31 | |
2660 | + 1b8: 7c 48 02 a6 mflr r2 | |
2661 | + 1bc: 7e 60 00 a6 mfmsr r19 | |
2662 | + 1c0: 7c 78 00 26 mfocrf r3,128 | |
2663 | + 1c4: 7c 25 02 a6 mfrtcl r1 | |
2664 | + 1c8: 7c 04 02 a6 mfrtcu r0 | |
2665 | + 1cc: 7c d9 02 a6 mfsdr1 r6 | |
2666 | + 1d0: 7c 60 22 a6 mfspr r3,128 | |
2667 | + 1d4: 7c fa 02 a6 mfsrr0 r7 | |
2668 | + 1d8: 7d 1b 02 a6 mfsrr1 r8 | |
2669 | + 1dc: 7f c1 02 a6 mfxer r30 | |
2670 | + 1e0: 7f fe fb 79 mr. r30,r31 | |
2671 | + 1e4: 7f fe fb 78 mr r30,r31 | |
2672 | + 1e8: 7c 6f f1 20 mtcr r3 | |
2673 | + 1ec: 7c 68 01 20 mtcrf 128,r3 | |
2674 | + 1f0: 7e 69 03 a6 mtctr r19 | |
2675 | + 1f4: 7e b3 03 a6 mtdar r21 | |
2676 | + 1f8: 7f 16 03 a6 mtdec r24 | |
2677 | + 1fc: 7e 92 03 a6 mtdsisr r20 | |
2678 | + 200: fc 60 00 8d mtfsb0. so | |
2679 | + 204: fc 60 00 8c mtfsb0 so | |
2680 | + 208: fc 60 00 4d mtfsb1. so | |
2681 | + 20c: fc 60 00 4c mtfsb1 so | |
2682 | + 210: fc 0c 55 8e mtfsf 6,f10 | |
2683 | + 214: fc 0c 5d 8f mtfsf. 6,f11 | |
2684 | + 218: ff 00 01 0c mtfsfi 6,0 | |
2685 | + 21c: ff 00 f1 0d mtfsfi. 6,15 | |
2686 | + 220: 7e 48 03 a6 mtlr r18 | |
2687 | + 224: 7d 40 01 24 mtmsr r10 | |
2688 | + 228: 7c 78 01 20 mtocrf 128,r3 | |
2689 | + 22c: 7e f5 03 a6 mtrtcl r23 | |
2690 | + 230: 7e d4 03 a6 mtrtcu r22 | |
2691 | + 234: 7f 39 03 a6 mtsdr1 r25 | |
2692 | + 238: 7c 60 23 a6 mtspr 128,r3 | |
2693 | + 23c: 7f 5a 03 a6 mtsrr0 r26 | |
2694 | + 240: 7f 7b 03 a6 mtsrr1 r27 | |
2695 | + 244: 7e 21 03 a6 mtxer r17 | |
2696 | + 248: 7f bc f3 b9 nand. r28,r29,r30 | |
2697 | + 24c: 7f bc f3 b8 nand r28,r29,r30 | |
2698 | + 250: 7c 64 00 d1 neg. r3,r4 | |
2699 | + 254: 7c 64 00 d0 neg r3,r4 | |
2700 | + 258: 7e 11 04 d0 nego r16,r17 | |
2701 | + 25c: 7e 53 04 d1 nego. r18,r19 | |
2702 | + 260: 7e b4 b0 f9 nor. r20,r21,r22 | |
2703 | + 264: 7e b4 b0 f8 nor r20,r21,r22 | |
2704 | + 268: 7e b4 a8 f9 not. r20,r21 | |
2705 | + 26c: 7e b4 a8 f8 not r20,r21 | |
2706 | + 270: 7c 40 23 78 or r0,r2,r4 | |
2707 | + 274: 7d cc 83 79 or. r12,r14,r16 | |
2708 | + 278: 7e 0f 8b 38 orc r15,r16,r17 | |
2709 | + 27c: 7e 72 a3 39 orc. r18,r19,r20 | |
2710 | + 280: 4c 00 00 64 rfi | |
2711 | + 284: 99 61 00 02 stb r11,2\(r1\) | |
2712 | + 288: 9d 81 00 03 stbu r12,3\(r1\) | |
2713 | + 28c: 7d ae 79 ee stbux r13,r14,r15 | |
2714 | + 290: 7c 64 29 ae stbx r3,r4,r5 | |
2715 | + 294: db 21 00 20 stfd f25,32\(r1\) | |
2716 | + 298: df 41 00 28 stfdu f26,40\(r1\) | |
2717 | + 29c: 7c 01 15 ee stfdux f0,r1,r2 | |
2718 | + 2a0: 7f be fd ae stfdx f29,r30,r31 | |
2719 | + 2a4: d2 e1 00 14 stfs f23,20\(r1\) | |
2720 | + 2a8: d7 01 00 18 stfsu f24,24\(r1\) | |
2721 | + 2ac: 7f 5b e5 6e stfsux f26,r27,r28 | |
2722 | + 2b0: 7e f8 cd 2e stfsx f23,r24,r25 | |
2723 | + 2b4: b2 21 00 0a sth r17,10\(r1\) | |
2724 | + 2b8: 7c c7 47 2c sthbrx r6,r7,r8 | |
2725 | + 2bc: b6 41 00 0c sthu r18,12\(r1\) | |
2726 | + 2c0: 7e b6 bb 6e sthux r21,r22,r23 | |
2727 | + 2c4: 7d 8d 73 2e sthx r12,r13,r14 | |
2728 | + 2c8: 7f dd fa 79 xor. r29,r30,r31 | |
2729 | + 2cc: 7f dd fa 78 xor r29,r30,r31 | |
2730 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/common.s binutils-2.19.1/gas/testsuite/gas/ppc/common.s | |
2731 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/common.s 1969-12-31 16:00:00.000000000 -0800 | |
2732 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/common.s 2009-03-02 05:37:44.000000000 -0800 | |
2733 | @@ -0,0 +1,182 @@ | |
2734 | + .section ".text" | |
2735 | +start: | |
2736 | + and. 3,4,5 | |
2737 | + and 3,4,5 | |
2738 | + andc 13,14,15 | |
2739 | + andc. 16,17,18 | |
2740 | + ba label_abs | |
2741 | + bc 0,1,foo | |
2742 | + bca 4,5,foo_abs | |
2743 | + bcl 2,3,foo | |
2744 | + bcla 10,7,foo_abs | |
2745 | + bctr | |
2746 | + bctrl | |
2747 | + bdza foo_abs | |
2748 | + bdz foo | |
2749 | + bdzla foo_abs | |
2750 | + bdzl foo | |
2751 | + beq 0,foo | |
2752 | + beqa 2,foo_abs | |
2753 | + beql 1,foo | |
2754 | + beqla 3,foo_abs | |
2755 | + bge 0,foo | |
2756 | + bgea 4,foo_abs | |
2757 | + bgel 2,foo | |
2758 | + bgela 6,foo_abs | |
2759 | + bgt 4,foo | |
2760 | + bgta 6,foo_abs | |
2761 | + bgtl 5,foo | |
2762 | + bgtla 7,foo_abs | |
2763 | + b label | |
2764 | + bla label_abs | |
2765 | + ble 0,foo | |
2766 | + blea 4,foo | |
2767 | + blel 2,foo | |
2768 | + blela 6,foo_abs | |
2769 | + bl label | |
2770 | + blt 0,foo | |
2771 | + blta 2,foo_abs | |
2772 | + bltl 1,foo | |
2773 | + bltla 3,foo_abs | |
2774 | + bne 0,foo | |
2775 | + bnea 2,foo | |
2776 | + bnel 1,foo | |
2777 | + bnela 3,foo_abs | |
2778 | + bng 1,foo | |
2779 | + bnga 5,foo_abs | |
2780 | + bngl 3,foo | |
2781 | + bngla 7,foo_abs | |
2782 | + bnl 1,foo | |
2783 | + bnla 5,foo_abs | |
2784 | + bnll 3,foo | |
2785 | + bnlla 7,foo_abs | |
2786 | + bns 4,foo | |
2787 | + bnsa 6,foo_abs | |
2788 | + bnsl 5,foo | |
2789 | + bnsla 7,foo_abs | |
2790 | + bso 4,foo | |
2791 | + bsoa 6,foo_abs | |
2792 | + bsol 5,foo | |
2793 | + bsola 7,foo_abs | |
2794 | + crand 4,5,6 | |
2795 | + crandc 3,4,5 | |
2796 | + creqv 7,0,1 | |
2797 | + crnand 1,2,3 | |
2798 | + crnor 0,1,2 | |
2799 | + cror 5,6,7 | |
2800 | + crorc 2,3,4 | |
2801 | + crxor 6,7,0 | |
2802 | + eqv. 10,11,12 | |
2803 | + eqv 10,11,12 | |
2804 | + fabs. 21,31 | |
2805 | + fabs 21,31 | |
2806 | + fcmpo 3,10,11 | |
2807 | + fcmpu 3,4,5 | |
2808 | + fmr. 3,4 | |
2809 | + fmr 3,4 | |
2810 | + fnabs. 20,30 | |
2811 | + fnabs 20,30 | |
2812 | + fneg. 3,4 | |
2813 | + fneg 3,4 | |
2814 | + frsp 6,7 | |
2815 | + frsp. 8,9 | |
2816 | + lbz 9,0(1) | |
2817 | + lbzu 10,1(1) | |
2818 | + lbzux 20,21,22 | |
2819 | + lbzx 3,4,5 | |
2820 | + lfd 21,8(1) | |
2821 | + lfdu 22,16(1) | |
2822 | + lfdux 20,21,22 | |
2823 | + lfdx 13,14,15 | |
2824 | + lfs 19,0(1) | |
2825 | + lfsu 20,4(1) | |
2826 | + lfsux 10,11,12 | |
2827 | + lfsx 10,11,12 | |
2828 | + lha 15,6(1) | |
2829 | + lhau 16,8(1) | |
2830 | + lhaux 9,10,11 | |
2831 | + lhax 9,10,11 | |
2832 | + lhbrx 3,4,5 | |
2833 | + lhz 13,0(1) | |
2834 | + lhzu 14,2(1) | |
2835 | + lhzux 20,22,24 | |
2836 | + lhzx 23,24,25 | |
2837 | + mcrf 0,1 | |
2838 | + mcrfs 3,4 | |
2839 | + mcrxr 3 | |
2840 | + mfcr 3 | |
2841 | + mfctr 3 | |
2842 | + mfdar 5 | |
2843 | + mfdsisr 4 | |
2844 | + mffs 30 | |
2845 | + mffs. 31 | |
2846 | + mflr 2 | |
2847 | + mfmsr 19 | |
2848 | + mfocrf 3,0x80 | |
2849 | + mfrtcl 1 | |
2850 | + mfrtcu 0 | |
2851 | + mfsdr1 6 | |
2852 | + mfspr 3,0x80 | |
2853 | + mfsrr0 7 | |
2854 | + mfsrr1 8 | |
2855 | + mfxer 30 | |
2856 | + mr. 30,31 | |
2857 | + mr 30,31 | |
2858 | + mtcr 3 | |
2859 | + mtcrf 0x80,3 | |
2860 | + mtctr 19 | |
2861 | + mtdar 21 | |
2862 | + mtdec 24 | |
2863 | + mtdsisr 20 | |
2864 | + mtfsb0. 3 | |
2865 | + mtfsb0 3 | |
2866 | + mtfsb1. 3 | |
2867 | + mtfsb1 3 | |
2868 | + mtfsf 6,10 | |
2869 | + mtfsf. 6,11 | |
2870 | + mtfsfi 6,0 | |
2871 | + mtfsfi. 6,15 | |
2872 | + mtlr 18 | |
2873 | + mtmsr 10 | |
2874 | + mtocrf 0x80,3 | |
2875 | + mtrtcl 23 | |
2876 | + mtrtcu 22 | |
2877 | + mtsdr1 25 | |
2878 | + mtspr 0x80,3 | |
2879 | + mtsrr0 26 | |
2880 | + mtsrr1 27 | |
2881 | + mtxer 17 | |
2882 | + nand. 28,29,30 | |
2883 | + nand 28,29,30 | |
2884 | + neg. 3,4 | |
2885 | + neg 3,4 | |
2886 | + nego 16,17 | |
2887 | + nego. 18,19 | |
2888 | + nor. 20,21,22 | |
2889 | + nor 20,21,22 | |
2890 | + not. 20,21 | |
2891 | + not 20,21 | |
2892 | + or 0,2,4 | |
2893 | + or. 12,14,16 | |
2894 | + orc 15,16,17 | |
2895 | + orc. 18,19,20 | |
2896 | + rfi | |
2897 | + stb 11,2(1) | |
2898 | + stbu 12,3(1) | |
2899 | + stbux 13,14,15 | |
2900 | + stbx 3,4,5 | |
2901 | + stfd 25,32(1) | |
2902 | + stfdu 26,40(1) | |
2903 | + stfdux 0,1,2 | |
2904 | + stfdx 29,30,31 | |
2905 | + stfs 23,20(1) | |
2906 | + stfsu 24,24(1) | |
2907 | + stfsux 26,27,28 | |
2908 | + stfsx 23,24,25 | |
2909 | + sth 17,10(1) | |
2910 | + sthbrx 6,7,8 | |
2911 | + sthu 18,12(1) | |
2912 | + sthux 21,22,23 | |
2913 | + sthx 12,13,14 | |
2914 | + xor. 29,30,31 | |
2915 | + xor 29,30,31 | |
2916 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/e500mc.d binutils-2.19.1/gas/testsuite/gas/ppc/e500mc.d | |
2917 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/e500mc.d 2008-04-14 04:01:38.000000000 -0700 | |
2918 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/e500mc.d 2009-03-02 05:59:36.000000000 -0800 | |
2919 | @@ -6,7 +6,7 @@ | |
2920 | ||
2921 | Disassembly of section \.text: | |
2922 | ||
2923 | -0+0000000 <start>: | |
2924 | +0+00 <start>: | |
2925 | 0: 4c 00 00 4e rfdi | |
2926 | 4: 4c 00 00 cc rfgi | |
2927 | 8: 4c 1f f9 8c dnh 0,1023 | |
2928 | @@ -14,38 +14,43 @@ | |
2929 | 10: 7c 09 57 be icbiep r9,r10 | |
2930 | 14: 7c 00 69 dc msgclr r13 | |
2931 | 18: 7c 00 71 9c msgsnd r14 | |
2932 | - 1c: 7c 00 00 7c wait | |
2933 | - 20: 7f 9c e3 78 mdors | |
2934 | - 24: 7c 00 02 1c ehpriv | |
2935 | - 28: 7c 18 cb c6 dsn r24,r25 | |
2936 | - 2c: 7c 22 18 be lbepx r1,r2,r3 | |
2937 | - 30: 7c 85 32 3e lhepx r4,r5,r6 | |
2938 | - 34: 7c e8 48 3e lwepx r7,r8,r9 | |
2939 | - 38: 7d 4b 60 3a ldepx r10,r11,r12 | |
2940 | - 3c: 7d ae 7c be lfdepx r13,r14,r15 | |
2941 | - 40: 7e 11 91 be stbepx r16,r17,r18 | |
2942 | - 44: 7e 74 ab 3e sthepx r19,r20,r21 | |
2943 | - 48: 7e d7 c1 3e stwepx r22,r23,r24 | |
2944 | - 4c: 7f 3a d9 3a stdepx r25,r26,r27 | |
2945 | - 50: 7f 9d f5 be stfdepx r28,r29,r30 | |
2946 | - 54: 7c 01 14 06 lbdx r0,r1,r2 | |
2947 | - 58: 7d 8d 74 46 lhdx r12,r13,r14 | |
2948 | - 5c: 7c 64 2c 86 lwdx r3,r4,r5 | |
2949 | - 60: 7f 5b e6 46 lfddx f26,r27,r28 | |
2950 | - 64: 7d f0 8c c6 lddx r15,r16,r17 | |
2951 | - 68: 7c c7 45 06 stbdx r6,r7,r8 | |
2952 | - 6c: 7e 53 a5 46 sthdx r18,r19,r20 | |
2953 | - 70: 7d 2a 5d 86 stwdx r9,r10,r11 | |
2954 | - 74: 7f be ff 46 stfddx f29,r30,r31 | |
2955 | - 78: 7e b6 bd c6 stddx r21,r22,r23 | |
2956 | - 7c: 7c 20 0d ec dcbal r0,r1 | |
2957 | - 80: 7c 26 3f ec dcbzl r6,r7 | |
2958 | - 84: 7c 1f 00 7e dcbstep r31,r0 | |
2959 | - 88: 7c 01 10 fe dcbfep r1,r2 | |
2960 | - 8c: 7c 64 29 fe dcbtstep r3,r4,r5 | |
2961 | - 90: 7c c7 42 7e dcbtep r6,r7,r8 | |
2962 | - 94: 7c 0b 67 fe dcbzep r11,r12 | |
2963 | - 98: 7c 00 06 26 tlbilx 0,0,r0 | |
2964 | - 9c: 7c 20 06 26 tlbilx 1,0,r0 | |
2965 | - a0: 7c 62 1e 26 tlbilx 3,r2,r3 | |
2966 | - a4: 7c 64 2e 26 tlbilx 3,r4,r5 | |
2967 | + 1c: 7c 00 00 7c wait | |
2968 | + 20: 7c 00 00 7c wait | |
2969 | + 24: 7c 20 00 7c waitrsv | |
2970 | + 28: 7c 20 00 7c waitrsv | |
2971 | + 2c: 7c 40 00 7c waitimpl | |
2972 | + 30: 7c 40 00 7c waitimpl | |
2973 | + 34: 7f 9c e3 78 mdors | |
2974 | + 38: 7c 00 02 1c ehpriv | |
2975 | + 3c: 7c 18 cb c6 dsn r24,r25 | |
2976 | + 40: 7c 22 18 be lbepx r1,r2,r3 | |
2977 | + 44: 7c 85 32 3e lhepx r4,r5,r6 | |
2978 | + 48: 7c e8 48 3e lwepx r7,r8,r9 | |
2979 | + 4c: 7d 4b 60 3a ldepx r10,r11,r12 | |
2980 | + 50: 7d ae 7c be lfdepx f13,r14,r15 | |
2981 | + 54: 7e 11 91 be stbepx r16,r17,r18 | |
2982 | + 58: 7e 74 ab 3e sthepx r19,r20,r21 | |
2983 | + 5c: 7e d7 c1 3e stwepx r22,r23,r24 | |
2984 | + 60: 7f 3a d9 3a stdepx r25,r26,r27 | |
2985 | + 64: 7f 9d f5 be stfdepx f28,r29,r30 | |
2986 | + 68: 7c 01 14 06 lbdx r0,r1,r2 | |
2987 | + 6c: 7d 8d 74 46 lhdx r12,r13,r14 | |
2988 | + 70: 7c 64 2c 86 lwdx r3,r4,r5 | |
2989 | + 74: 7f 5b e6 46 lfddx f26,r27,r28 | |
2990 | + 78: 7d f0 8c c6 lddx r15,r16,r17 | |
2991 | + 7c: 7c c7 45 06 stbdx r6,r7,r8 | |
2992 | + 80: 7e 53 a5 46 sthdx r18,r19,r20 | |
2993 | + 84: 7d 2a 5d 86 stwdx r9,r10,r11 | |
2994 | + 88: 7f be ff 46 stfddx f29,r30,r31 | |
2995 | + 8c: 7e b6 bd c6 stddx r21,r22,r23 | |
2996 | + 90: 7c 20 0d ec dcbal r0,r1 | |
2997 | + 94: 7c 26 3f ec dcbzl r6,r7 | |
2998 | + 98: 7c 1f 00 7e dcbstep r31,r0 | |
2999 | + 9c: 7c 01 10 fe dcbfep r1,r2 | |
3000 | + a0: 7c 64 29 fe dcbtstep r3,r4,r5 | |
3001 | + a4: 7c c7 42 7e dcbtep r6,r7,r8 | |
3002 | + a8: 7c 0b 67 fe dcbzep r11,r12 | |
3003 | + ac: 7c 00 06 26 tlbilx 0,0,r0 | |
3004 | + b0: 7c 20 06 26 tlbilx 1,0,r0 | |
3005 | + b4: 7c 62 1e 26 tlbilx 3,r2,r3 | |
3006 | + b8: 7c 64 2e 26 tlbilx 3,r4,r5 | |
3007 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/e500mc.s binutils-2.19.1/gas/testsuite/gas/ppc/e500mc.s | |
3008 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/e500mc.s 2008-04-14 04:01:38.000000000 -0700 | |
3009 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/e500mc.s 2009-03-02 05:59:36.000000000 -0800 | |
3010 | @@ -9,6 +9,11 @@ | |
3011 | msgclr 13 | |
3012 | msgsnd 14 | |
3013 | wait | |
3014 | + wait 0 | |
3015 | + waitrsv | |
3016 | + wait 1 | |
3017 | + waitimpl | |
3018 | + wait 2 | |
3019 | mdors | |
3020 | ehpriv | |
3021 | dsn 24, 25 | |
3022 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power4_32.d binutils-2.19.1/gas/testsuite/gas/ppc/power4_32.d | |
3023 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power4_32.d 1969-12-31 16:00:00.000000000 -0800 | |
3024 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/power4_32.d 2009-03-02 05:54:22.000000000 -0800 | |
3025 | @@ -0,0 +1,46 @@ | |
3026 | +#objdump: -d -Mpower4 | |
3027 | +#as: -a32 -mpower4 | |
3028 | +#name: Power4 instructions | |
3029 | + | |
3030 | +.*: +file format elf32-powerpc.* | |
3031 | + | |
3032 | +Disassembly of section \.text: | |
3033 | + | |
3034 | +0+00 <start>: | |
3035 | + 0: 80 c7 00 00 lwz r6,0\(r7\) | |
3036 | + 4: 80 c7 00 10 lwz r6,16\(r7\) | |
3037 | + 8: 80 c7 ff f0 lwz r6,-16\(r7\) | |
3038 | + c: 80 c7 80 00 lwz r6,-32768\(r7\) | |
3039 | + 10: 80 c7 7f f0 lwz r6,32752\(r7\) | |
3040 | + 14: 90 c7 00 00 stw r6,0\(r7\) | |
3041 | + 18: 90 c7 00 10 stw r6,16\(r7\) | |
3042 | + 1c: 90 c7 ff f0 stw r6,-16\(r7\) | |
3043 | + 20: 90 c7 80 00 stw r6,-32768\(r7\) | |
3044 | + 24: 90 c7 7f f0 stw r6,32752\(r7\) | |
3045 | + 28: 00 00 02 00 attn | |
3046 | + 2c: 7c 6f f1 20 mtcr r3 | |
3047 | + 30: 7c 6f f1 20 mtcr r3 | |
3048 | + 34: 7c 68 11 20 mtcrf 129,r3 | |
3049 | + 38: 7c 70 11 20 mtocrf 1,r3 | |
3050 | + 3c: 7c 70 21 20 mtocrf 2,r3 | |
3051 | + 40: 7c 70 41 20 mtocrf 4,r3 | |
3052 | + 44: 7c 70 81 20 mtocrf 8,r3 | |
3053 | + 48: 7c 71 01 20 mtocrf 16,r3 | |
3054 | + 4c: 7c 72 01 20 mtocrf 32,r3 | |
3055 | + 50: 7c 74 01 20 mtocrf 64,r3 | |
3056 | + 54: 7c 78 01 20 mtocrf 128,r3 | |
3057 | + 58: 7c 60 00 26 mfcr r3 | |
3058 | + 5c: 7c 70 10 26 mfocrf r3,1 | |
3059 | + 60: 7c 70 20 26 mfocrf r3,2 | |
3060 | + 64: 7c 70 40 26 mfocrf r3,4 | |
3061 | + 68: 7c 70 80 26 mfocrf r3,8 | |
3062 | + 6c: 7c 71 00 26 mfocrf r3,16 | |
3063 | + 70: 7c 72 00 26 mfocrf r3,32 | |
3064 | + 74: 7c 74 00 26 mfocrf r3,64 | |
3065 | + 78: 7c 78 00 26 mfocrf r3,128 | |
3066 | + 7c: 7c 01 17 ec dcbz r1,r2 | |
3067 | + 80: 7c 23 27 ec dcbzl r3,r4 | |
3068 | + 84: 7c 05 37 ec dcbz r5,r6 | |
3069 | + 88: 7c 05 32 2c dcbt r5,r6 | |
3070 | + 8c: 7c 05 32 2c dcbt r5,r6 | |
3071 | + 90: 7d 05 32 2c dcbt r5,r6,8 | |
3072 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power4_32.s binutils-2.19.1/gas/testsuite/gas/ppc/power4_32.s | |
3073 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power4_32.s 1969-12-31 16:00:00.000000000 -0800 | |
3074 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/power4_32.s 2009-03-02 05:54:22.000000000 -0800 | |
3075 | @@ -0,0 +1,39 @@ | |
3076 | + .section ".text" | |
3077 | +start: | |
3078 | + lwz 6,0(7) | |
3079 | + lwz 6,16(7) | |
3080 | + lwz 6,-16(7) | |
3081 | + lwz 6,-32768(7) | |
3082 | + lwz 6,32752(7) | |
3083 | + stw 6,0(7) | |
3084 | + stw 6,16(7) | |
3085 | + stw 6,-16(7) | |
3086 | + stw 6,-32768(7) | |
3087 | + stw 6,32752(7) | |
3088 | + attn | |
3089 | + mtcr 3 | |
3090 | + mtcrf 0xff,3 | |
3091 | + mtcrf 0x81,3 | |
3092 | + mtcrf 0x01,3 | |
3093 | + mtcrf 0x02,3 | |
3094 | + mtcrf 0x04,3 | |
3095 | + mtcrf 0x08,3 | |
3096 | + mtcrf 0x10,3 | |
3097 | + mtcrf 0x20,3 | |
3098 | + mtcrf 0x40,3 | |
3099 | + mtcrf 0x80,3 | |
3100 | + mfcr 3 | |
3101 | + mfcr 3,0x01 | |
3102 | + mfcr 3,0x02 | |
3103 | + mfcr 3,0x04 | |
3104 | + mfcr 3,0x08 | |
3105 | + mfcr 3,0x10 | |
3106 | + mfcr 3,0x20 | |
3107 | + mfcr 3,0x40 | |
3108 | + mfcr 3,0x80 | |
3109 | + dcbz 1, 2 | |
3110 | + dcbzl 3, 4 | |
3111 | + dcbz 5, 6 | |
3112 | + dcbt 5,6 | |
3113 | + dcbt 5,6,0 | |
3114 | + dcbt 5,6,8 | |
3115 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power6.d binutils-2.19.1/gas/testsuite/gas/ppc/power6.d | |
3116 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power6.d 2008-07-31 19:44:12.000000000 -0700 | |
3117 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/power6.d 2009-03-02 05:59:36.000000000 -0800 | |
3118 | @@ -28,4 +28,44 @@ | |
3119 | 48: 7e 08 3a ac dstt r8,r7,0 | |
3120 | 4c: 7c 65 32 ec dstst r5,r6,3 | |
3121 | 50: 7e 44 2a ec dststt r4,r5,2 | |
3122 | - | |
3123 | + 54: 00 00 02 00 attn | |
3124 | + 58: 7c 6f f1 20 mtcr r3 | |
3125 | + 5c: 7c 6f f1 20 mtcr r3 | |
3126 | + 60: 7c 68 11 20 mtcrf 129,r3 | |
3127 | + 64: 7c 70 11 20 mtocrf 1,r3 | |
3128 | + 68: 7c 70 21 20 mtocrf 2,r3 | |
3129 | + 6c: 7c 70 41 20 mtocrf 4,r3 | |
3130 | + 70: 7c 70 81 20 mtocrf 8,r3 | |
3131 | + 74: 7c 71 01 20 mtocrf 16,r3 | |
3132 | + 78: 7c 72 01 20 mtocrf 32,r3 | |
3133 | + 7c: 7c 74 01 20 mtocrf 64,r3 | |
3134 | + 80: 7c 78 01 20 mtocrf 128,r3 | |
3135 | + 84: 7c 60 00 26 mfcr r3 | |
3136 | + 88: 7c 70 10 26 mfocrf r3,1 | |
3137 | + 8c: 7c 70 20 26 mfocrf r3,2 | |
3138 | + 90: 7c 70 40 26 mfocrf r3,4 | |
3139 | + 94: 7c 70 80 26 mfocrf r3,8 | |
3140 | + 98: 7c 71 00 26 mfocrf r3,16 | |
3141 | + 9c: 7c 72 00 26 mfocrf r3,32 | |
3142 | + a0: 7c 74 00 26 mfocrf r3,64 | |
3143 | + a4: 7c 78 00 26 mfocrf r3,128 | |
3144 | + a8: 7c 01 17 ec dcbz r1,r2 | |
3145 | + ac: 7c 23 27 ec dcbzl r3,r4 | |
3146 | + b0: 7c 05 37 ec dcbz r5,r6 | |
3147 | + b4: fc 0c 55 8e mtfsf 6,f10 | |
3148 | + b8: fc 0c 5d 8f mtfsf. 6,f11 | |
3149 | + bc: fc 0c 55 8e mtfsf 6,f10 | |
3150 | + c0: fc 0c 5d 8f mtfsf. 6,f11 | |
3151 | + c4: fc 0d 55 8e mtfsf 6,f10,0,1 | |
3152 | + c8: fc 0d 5d 8f mtfsf. 6,f11,0,1 | |
3153 | + cc: fe 0c 55 8e mtfsf 6,f10,1,0 | |
3154 | + d0: fe 0c 5d 8f mtfsf. 6,f11,1,0 | |
3155 | + d4: ff 00 01 0c mtfsfi 6,0 | |
3156 | + d8: ff 00 f1 0d mtfsfi. 6,15 | |
3157 | + dc: ff 00 01 0c mtfsfi 6,0 | |
3158 | + e0: ff 00 f1 0d mtfsfi. 6,15 | |
3159 | + e4: ff 01 01 0c mtfsfi 6,0,1 | |
3160 | + e8: ff 01 f1 0d mtfsfi. 6,15,1 | |
3161 | + ec: 7d 6a 02 74 cbcdtd r10,r11 | |
3162 | + f0: 7d 6a 02 34 cdtbcd r10,r11 | |
3163 | + f4: 7d 4b 60 94 addg6s r10,r11,r12 | |
3164 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power6.s binutils-2.19.1/gas/testsuite/gas/ppc/power6.s | |
3165 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power6.s 2008-07-31 19:44:12.000000000 -0700 | |
3166 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/power6.s 2009-03-02 05:59:36.000000000 -0800 | |
3167 | @@ -23,3 +23,44 @@ | |
3168 | dstt 8,7,0 | |
3169 | dstst 5,6,3 | |
3170 | dststt 4,5,2 | |
3171 | + attn | |
3172 | + mtcr 3 | |
3173 | + mtcrf 0xff,3 | |
3174 | + mtcrf 0x81,3 | |
3175 | + mtcrf 0x01,3 | |
3176 | + mtcrf 0x02,3 | |
3177 | + mtcrf 0x04,3 | |
3178 | + mtcrf 0x08,3 | |
3179 | + mtcrf 0x10,3 | |
3180 | + mtcrf 0x20,3 | |
3181 | + mtcrf 0x40,3 | |
3182 | + mtcrf 0x80,3 | |
3183 | + mfcr 3 | |
3184 | + mfcr 3,0x01 | |
3185 | + mfcr 3,0x02 | |
3186 | + mfcr 3,0x04 | |
3187 | + mfcr 3,0x08 | |
3188 | + mfcr 3,0x10 | |
3189 | + mfcr 3,0x20 | |
3190 | + mfcr 3,0x40 | |
3191 | + mfcr 3,0x80 | |
3192 | + dcbz 1, 2 | |
3193 | + dcbzl 3, 4 | |
3194 | + dcbz 5, 6 | |
3195 | + mtfsf 6,10 | |
3196 | + mtfsf. 6,11 | |
3197 | + mtfsf 6,10,0,0 | |
3198 | + mtfsf. 6,11,0,0 | |
3199 | + mtfsf 6,10,0,1 | |
3200 | + mtfsf. 6,11,0,1 | |
3201 | + mtfsf 6,10,1,0 | |
3202 | + mtfsf. 6,11,1,0 | |
3203 | + mtfsfi 6,0 | |
3204 | + mtfsfi. 6,15 | |
3205 | + mtfsfi 6,0,0 | |
3206 | + mtfsfi. 6,15,0 | |
3207 | + mtfsfi 6,0,1 | |
3208 | + mtfsfi. 6,15,1 | |
3209 | + cbcdtd 10,11 | |
3210 | + cdtbcd 10,11 | |
3211 | + addg6s 10,11,12 | |
3212 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power7.d binutils-2.19.1/gas/testsuite/gas/ppc/power7.d | |
3213 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power7.d 2008-08-01 21:38:51.000000000 -0700 | |
3214 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/power7.d 2009-03-02 05:59:36.000000000 -0800 | |
3215 | @@ -1,8 +1,8 @@ | |
3216 | -#as: -a32 -mpower7 | |
3217 | +#as: -mpower7 | |
3218 | #objdump: -dr -Mpower7 | |
3219 | #name: POWER7 tests (includes DFP, Altivec and VSX) | |
3220 | ||
3221 | -.*: +file format elf32-powerpc.* | |
3222 | +.*: +file format elf(32)?(64)?-powerpc.* | |
3223 | ||
3224 | Disassembly of section \.text: | |
3225 | ||
3226 | @@ -33,25 +33,81 @@ | |
3227 | 5c: f1 6c 67 87 xvmovdp vs43,vs44 | |
3228 | 60: f0 64 2f 80 xvcpsgndp vs3,vs4,vs5 | |
3229 | 64: f1 6c 6f 87 xvcpsgndp vs43,vs44,vs45 | |
3230 | - 68: 4c 00 03 24 doze | |
3231 | - 6c: 4c 00 03 64 nap | |
3232 | - 70: 4c 00 03 a4 sleep | |
3233 | - 74: 4c 00 03 e4 rvwinkle | |
3234 | - 78: 7c 83 01 34 prtyw r3,r4 | |
3235 | - 7c: 7d cd 01 74 prtyd r13,r14 | |
3236 | - 80: 7d 5c 02 a6 mfcfar r10 | |
3237 | - 84: 7d 7c 03 a6 mtcfar r11 | |
3238 | - 88: 7c 83 2b f8 cmpb r3,r4,r5 | |
3239 | - 8c: 7c c0 3c be mffgpr f6,r7 | |
3240 | - 90: 7d 00 4d be mftgpr r8,f9 | |
3241 | - 94: 7d 4b 66 2a lwzcix r10,r11,r12 | |
3242 | - 98: 7d ae 7e 2e lfdpx f13,r14,r15 | |
3243 | - 9c: ee 11 90 04 dadd f16,f17,f18 | |
3244 | - a0: fe 96 c0 04 daddq f20,f22,f24 | |
3245 | - a4: 7c 60 06 6c dss 3 | |
3246 | - a8: 7e 00 06 6c dssall | |
3247 | - ac: 7c 25 22 ac dst r5,r4,1 | |
3248 | - b0: 7e 08 3a ac dstt r8,r7,0 | |
3249 | - b4: 7c 65 32 ec dstst r5,r6,3 | |
3250 | - b8: 7e 44 2a ec dststt r4,r5,2 | |
3251 | - bc: 4e 80 00 20 blr | |
3252 | + 68: 7c 00 00 7c wait | |
3253 | + 6c: 7c 00 00 7c wait | |
3254 | + 70: 7c 20 00 7c waitrsv | |
3255 | + 74: 7c 20 00 7c waitrsv | |
3256 | + 78: 7c 40 00 7c waitimpl | |
3257 | + 7c: 7c 40 00 7c waitimpl | |
3258 | + 80: 4c 00 03 24 doze | |
3259 | + 84: 4c 00 03 64 nap | |
3260 | + 88: 4c 00 03 a4 sleep | |
3261 | + 8c: 4c 00 03 e4 rvwinkle | |
3262 | + 90: 7c 83 01 34 prtyw r3,r4 | |
3263 | + 94: 7d cd 01 74 prtyd r13,r14 | |
3264 | + 98: 7d 5c 02 a6 mfcfar r10 | |
3265 | + 9c: 7d 7c 03 a6 mtcfar r11 | |
3266 | + a0: 7c 83 2b f8 cmpb r3,r4,r5 | |
3267 | + a4: 7d 4b 66 2a lwzcix r10,r11,r12 | |
3268 | + a8: ee 11 90 04 dadd f16,f17,f18 | |
3269 | + ac: fe 96 c0 04 daddq f20,f22,f24 | |
3270 | + b0: 7c 60 06 6c dss 3 | |
3271 | + b4: 7e 00 06 6c dssall | |
3272 | + b8: 7c 25 22 ac dst r5,r4,1 | |
3273 | + bc: 7e 08 3a ac dstt r8,r7,0 | |
3274 | + c0: 7c 65 32 ec dstst r5,r6,3 | |
3275 | + c4: 7e 44 2a ec dststt r4,r5,2 | |
3276 | + c8: 7d 4b 63 56 divwe r10,r11,r12 | |
3277 | + cc: 7d 6c 6b 57 divwe\. r11,r12,r13 | |
3278 | + d0: 7d 8d 77 56 divweo r12,r13,r14 | |
3279 | + d4: 7d ae 7f 57 divweo\. r13,r14,r15 | |
3280 | + d8: 7d 4b 63 16 divweu r10,r11,r12 | |
3281 | + dc: 7d 6c 6b 17 divweu\. r11,r12,r13 | |
3282 | + e0: 7d 8d 77 16 divweuo r12,r13,r14 | |
3283 | + e4: 7d ae 7f 17 divweuo\. r13,r14,r15 | |
3284 | + e8: 7e 27 d9 f8 bpermd r7,r17,r27 | |
3285 | + ec: 7e 8a 02 f4 popcntw r10,r20 | |
3286 | + f0: 7e 8a 03 f4 popcntd r10,r20 | |
3287 | + f4: 7e 95 b4 28 ldbrx r20,r21,r22 | |
3288 | + f8: 7e 95 b5 28 stdbrx r20,r21,r22 | |
3289 | + fc: 7d 40 56 ee lfiwzx f10,0,r10 | |
3290 | + 100: 7d 49 56 ee lfiwzx f10,r9,r10 | |
3291 | + 104: ec 80 2e 9c fcfids f4,f5 | |
3292 | + 108: ec 80 2e 9d fcfids\. f4,f5 | |
3293 | + 10c: ec 80 2f 9c fcfidus f4,f5 | |
3294 | + 110: ec 80 2f 9d fcfidus\. f4,f5 | |
3295 | + 114: fc 80 29 1c fctiwu f4,f5 | |
3296 | + 118: fc 80 29 1d fctiwu\. f4,f5 | |
3297 | + 11c: fc 80 29 1e fctiwuz f4,f5 | |
3298 | + 120: fc 80 29 1f fctiwuz\. f4,f5 | |
3299 | + 124: fc 80 2f 5c fctidu f4,f5 | |
3300 | + 128: fc 80 2f 5d fctidu\. f4,f5 | |
3301 | + 12c: fc 80 2f 5e fctiduz f4,f5 | |
3302 | + 130: fc 80 2f 5f fctiduz\. f4,f5 | |
3303 | + 134: fc 80 2f 9c fcfidu f4,f5 | |
3304 | + 138: fc 80 2f 9d fcfidu\. f4,f5 | |
3305 | + 13c: fc 0a 59 00 ftdiv cr0,f10,f11 | |
3306 | + 140: ff 8a 59 00 ftdiv cr7,f10,f11 | |
3307 | + 144: fc 00 51 40 ftsqrt cr0,f10 | |
3308 | + 148: ff 80 51 40 ftsqrt cr7,f10 | |
3309 | + 14c: 7e 08 4a 2c dcbtt r8,r9 | |
3310 | + 150: 7e 08 49 ec dcbtstt r8,r9 | |
3311 | + 154: ed 40 66 44 dcffix f10,f12 | |
3312 | + 158: ee 80 b6 45 dcffix\. f20,f22 | |
3313 | + 15c: 7d 4b 60 68 lbarx r10,r11,r12 | |
3314 | + 160: 7d 4b 60 68 lbarx r10,r11,r12 | |
3315 | + 164: 7d 4b 60 69 lbarx r10,r11,r12,1 | |
3316 | + 168: 7e 95 b0 e8 lharx r20,r21,r22 | |
3317 | + 16c: 7e 95 b0 e8 lharx r20,r21,r22 | |
3318 | + 170: 7e 95 b0 e9 lharx r20,r21,r22,1 | |
3319 | + 174: 7d 4b 65 6d stbcx\. r10,r11,r12 | |
3320 | + 178: 7d 4b 65 ad sthcx\. r10,r11,r12 | |
3321 | + 17c: fd c0 78 30 fre f14,f15 | |
3322 | + 180: fd c0 78 31 fre\. f14,f15 | |
3323 | + 184: ed c0 78 30 fres f14,f15 | |
3324 | + 188: ed c0 78 31 fres\. f14,f15 | |
3325 | + 18c: fd c0 78 34 frsqrte f14,f15 | |
3326 | + 190: fd c0 78 35 frsqrte\. f14,f15 | |
3327 | + 194: ed c0 78 34 frsqrtes f14,f15 | |
3328 | + 198: ed c0 78 35 frsqrtes\. f14,f15 | |
3329 | + 19c: 7c 43 27 1e isel r2,r3,r4,28 | |
3330 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/power7.s binutils-2.19.1/gas/testsuite/gas/ppc/power7.s | |
3331 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/power7.s 2008-08-01 21:38:51.000000000 -0700 | |
3332 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/power7.s 2009-03-02 05:59:36.000000000 -0800 | |
3333 | @@ -1,9 +1,4 @@ | |
3334 | - .file "power7.c" | |
3335 | .section ".text" | |
3336 | - .align 2 | |
3337 | - .p2align 4,,15 | |
3338 | - .globl power7 | |
3339 | - .type power7, @function | |
3340 | power7: | |
3341 | lxvd2x 3,4,5 | |
3342 | lxvd2ux 3,4,5 | |
3343 | @@ -31,6 +26,12 @@ | |
3344 | xvcpsgndp 43,44,44 | |
3345 | xvcpsgndp 3,4,5 | |
3346 | xvcpsgndp 43,44,45 | |
3347 | + wait | |
3348 | + wait 0 | |
3349 | + waitrsv | |
3350 | + wait 1 | |
3351 | + waitimpl | |
3352 | + wait 2 | |
3353 | doze | |
3354 | nap | |
3355 | sleep | |
3356 | @@ -40,10 +41,7 @@ | |
3357 | mfcfar 10 | |
3358 | mtcfar 11 | |
3359 | cmpb 3,4,5 | |
3360 | - mffgpr 6,7 | |
3361 | - mftgpr 8,9 | |
3362 | lwzcix 10,11,12 | |
3363 | - lfdpx 13,14,15 | |
3364 | dadd 16,17,18 | |
3365 | daddq 20,22,24 | |
3366 | dss 3 | |
3367 | @@ -52,7 +50,57 @@ | |
3368 | dstt 8,7,0 | |
3369 | dstst 5,6,3 | |
3370 | dststt 4,5,2 | |
3371 | - blr | |
3372 | - .size power7,.-power7 | |
3373 | - .ident "GCC: (GNU) 4.1.2 20070115 (prerelease) (SUSE Linux)" | |
3374 | - .section .note.GNU-stack,"",@progbits | |
3375 | + divwe 10,11,12 | |
3376 | + divwe. 11,12,13 | |
3377 | + divweo 12,13,14 | |
3378 | + divweo. 13,14,15 | |
3379 | + divweu 10,11,12 | |
3380 | + divweu. 11,12,13 | |
3381 | + divweuo 12,13,14 | |
3382 | + divweuo. 13,14,15 | |
3383 | + bpermd 7,17,27 | |
3384 | + popcntw 10,20 | |
3385 | + popcntd 10,20 | |
3386 | + ldbrx 20,21,22 | |
3387 | + stdbrx 20,21,22 | |
3388 | + lfiwzx 10,0,10 | |
3389 | + lfiwzx 10,9,10 | |
3390 | + fcfids 4,5 | |
3391 | + fcfids. 4,5 | |
3392 | + fcfidus 4,5 | |
3393 | + fcfidus. 4,5 | |
3394 | + fctiwu 4,5 | |
3395 | + fctiwu. 4,5 | |
3396 | + fctiwuz 4,5 | |
3397 | + fctiwuz. 4,5 | |
3398 | + fctidu 4,5 | |
3399 | + fctidu. 4,5 | |
3400 | + fctiduz 4,5 | |
3401 | + fctiduz. 4,5 | |
3402 | + fcfidu 4,5 | |
3403 | + fcfidu. 4,5 | |
3404 | + ftdiv 0,10,11 | |
3405 | + ftdiv 7,10,11 | |
3406 | + ftsqrt 0,10 | |
3407 | + ftsqrt 7,10 | |
3408 | + dcbtt 8,9 | |
3409 | + dcbtstt 8,9 | |
3410 | + dcffix 10,12 | |
3411 | + dcffix. 20,22 | |
3412 | + lbarx 10,11,12 | |
3413 | + lbarx 10,11,12,0 | |
3414 | + lbarx 10,11,12,1 | |
3415 | + lharx 20,21,22 | |
3416 | + lharx 20,21,22,0 | |
3417 | + lharx 20,21,22,1 | |
3418 | + stbcx. 10,11,12 | |
3419 | + sthcx. 10,11,12 | |
3420 | + fre 14,15 | |
3421 | + fre. 14,15 | |
3422 | + fres 14,15 | |
3423 | + fres. 14,15 | |
3424 | + frsqrte 14,15 | |
3425 | + frsqrte. 14,15 | |
3426 | + frsqrtes 14,15 | |
3427 | + frsqrtes. 14,15 | |
3428 | + isel 2,3,4,28 | |
3429 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/ppc.exp binutils-2.19.1/gas/testsuite/gas/ppc/ppc.exp | |
3430 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/ppc.exp 2008-08-01 21:38:51.000000000 -0700 | |
3431 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/ppc.exp 2009-03-02 05:59:36.000000000 -0800 | |
3432 | @@ -45,7 +45,10 @@ | |
3433 | run_dump_test "ppc750ps" | |
3434 | run_dump_test "e500mc" | |
3435 | run_dump_test "cell" | |
3436 | + run_dump_test "common" | |
3437 | + run_dump_test "power4_32" | |
3438 | run_dump_test "power6" | |
3439 | run_dump_test "power7" | |
3440 | + run_dump_test "vsx" | |
3441 | } | |
3442 | } | |
3443 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/vsx.d binutils-2.19.1/gas/testsuite/gas/ppc/vsx.d | |
3444 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/vsx.d 1969-12-31 16:00:00.000000000 -0800 | |
3445 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/vsx.d 2009-03-02 05:59:36.000000000 -0800 | |
3446 | @@ -0,0 +1,174 @@ | |
3447 | +#as: -mvsx | |
3448 | +#objdump: -d -Mvsx | |
3449 | +#name: VSX tests | |
3450 | + | |
3451 | +.*: +file format elf(32)?(64)?-powerpc.* | |
3452 | + | |
3453 | + | |
3454 | +Disassembly of section \.text: | |
3455 | + | |
3456 | +0+00 <start>: | |
3457 | + 0: 7d 0a a4 99 lxsdx vs40,r10,r20 | |
3458 | + 4: 7d 0a a4 d9 lxsdux vs40,r10,r20 | |
3459 | + 8: 7d 0a a6 99 lxvd2x vs40,r10,r20 | |
3460 | + c: 7d 0a a6 d9 lxvd2ux vs40,r10,r20 | |
3461 | + 10: 7d 0a a2 99 lxvdsx vs40,r10,r20 | |
3462 | + 14: 7d 0a a6 19 lxvw4x vs40,r10,r20 | |
3463 | + 18: 7d 0a a6 59 lxvw4ux vs40,r10,r20 | |
3464 | + 1c: 7d 0a a5 99 stxsdx vs40,r10,r20 | |
3465 | + 20: 7d 0a a5 d9 stxsdux vs40,r10,r20 | |
3466 | + 24: 7d 0a a7 99 stxvd2x vs40,r10,r20 | |
3467 | + 28: 7d 0a a7 d9 stxvd2ux vs40,r10,r20 | |
3468 | + 2c: 7d 0a a7 19 stxvw4x vs40,r10,r20 | |
3469 | + 30: 7d 0a a7 59 stxvw4ux vs40,r10,r20 | |
3470 | + 34: f1 00 e5 67 xsabsdp vs40,vs60 | |
3471 | + 38: f1 12 e1 07 xsadddp vs40,vs50,vs60 | |
3472 | + 3c: f0 92 e1 5e xscmpodp cr1,vs50,vs60 | |
3473 | + 40: f0 92 e1 1e xscmpudp cr1,vs50,vs60 | |
3474 | + 44: f1 12 e5 87 xscpsgndp vs40,vs50,vs60 | |
3475 | + 48: f1 00 e4 27 xscvdpsp vs40,vs60 | |
3476 | + 4c: f1 00 e5 63 xscvdpsxds vs40,vs60 | |
3477 | + 50: f1 00 e1 63 xscvdpsxws vs40,vs60 | |
3478 | + 54: f1 00 e5 23 xscvdpuxds vs40,vs60 | |
3479 | + 58: f1 00 e1 23 xscvdpuxws vs40,vs60 | |
3480 | + 5c: f1 00 e5 27 xscvspdp vs40,vs60 | |
3481 | + 60: f1 00 e5 e3 xscvsxddp vs40,vs60 | |
3482 | + 64: f1 00 e5 a3 xscvuxddp vs40,vs60 | |
3483 | + 68: f1 12 e1 c7 xsdivdp vs40,vs50,vs60 | |
3484 | + 6c: f1 12 e1 0f xsmaddadp vs40,vs50,vs60 | |
3485 | + 70: f1 12 e1 4f xsmaddmdp vs40,vs50,vs60 | |
3486 | + 74: f1 12 e5 07 xsmaxdp vs40,vs50,vs60 | |
3487 | + 78: f1 12 e5 47 xsmindp vs40,vs50,vs60 | |
3488 | + 7c: f1 12 e1 8f xsmsubadp vs40,vs50,vs60 | |
3489 | + 80: f1 12 e1 cf xsmsubmdp vs40,vs50,vs60 | |
3490 | + 84: f1 12 e1 87 xsmuldp vs40,vs50,vs60 | |
3491 | + 88: f1 00 e5 a7 xsnabsdp vs40,vs60 | |
3492 | + 8c: f1 00 e5 e7 xsnegdp vs40,vs60 | |
3493 | + 90: f1 12 e5 0f xsnmaddadp vs40,vs50,vs60 | |
3494 | + 94: f1 12 e5 4f xsnmaddmdp vs40,vs50,vs60 | |
3495 | + 98: f1 12 e5 8f xsnmsubadp vs40,vs50,vs60 | |
3496 | + 9c: f1 12 e5 cf xsnmsubmdp vs40,vs50,vs60 | |
3497 | + a0: f1 00 e1 27 xsrdpi vs40,vs60 | |
3498 | + a4: f1 00 e1 af xsrdpic vs40,vs60 | |
3499 | + a8: f1 00 e1 e7 xsrdpim vs40,vs60 | |
3500 | + ac: f1 00 e1 a7 xsrdpip vs40,vs60 | |
3501 | + b0: f1 00 e1 67 xsrdpiz vs40,vs60 | |
3502 | + b4: f1 00 e1 6b xsredp vs40,vs60 | |
3503 | + b8: f1 00 e1 2b xsrsqrtedp vs40,vs60 | |
3504 | + bc: f1 00 e1 2f xssqrtdp vs40,vs60 | |
3505 | + c0: f1 12 e1 47 xssubdp vs40,vs50,vs60 | |
3506 | + c4: f0 92 e1 ee xstdivdp cr1,vs50,vs60 | |
3507 | + c8: f0 80 e1 aa xstsqrtdp cr1,vs60 | |
3508 | + cc: f1 00 e7 67 xvabsdp vs40,vs60 | |
3509 | + d0: f1 00 e6 67 xvabssp vs40,vs60 | |
3510 | + d4: f1 12 e3 07 xvadddp vs40,vs50,vs60 | |
3511 | + d8: f1 12 e2 07 xvaddsp vs40,vs50,vs60 | |
3512 | + dc: f1 12 e3 1f xvcmpeqdp vs40,vs50,vs60 | |
3513 | + e0: f1 12 e7 1f xvcmpeqdp. vs40,vs50,vs60 | |
3514 | + e4: f1 12 e2 1f xvcmpeqsp vs40,vs50,vs60 | |
3515 | + e8: f1 12 e6 1f xvcmpeqsp. vs40,vs50,vs60 | |
3516 | + ec: f1 12 e3 9f xvcmpgedp vs40,vs50,vs60 | |
3517 | + f0: f1 12 e7 9f xvcmpgedp. vs40,vs50,vs60 | |
3518 | + f4: f1 12 e2 9f xvcmpgesp vs40,vs50,vs60 | |
3519 | + f8: f1 12 e6 9f xvcmpgesp. vs40,vs50,vs60 | |
3520 | + fc: f1 12 e3 5f xvcmpgtdp vs40,vs50,vs60 | |
3521 | + 100: f1 12 e7 5f xvcmpgtdp. vs40,vs50,vs60 | |
3522 | + 104: f1 12 e2 5f xvcmpgtsp vs40,vs50,vs60 | |
3523 | + 108: f1 12 e6 5f xvcmpgtsp. vs40,vs50,vs60 | |
3524 | + 10c: f1 12 e7 87 xvcpsgndp vs40,vs50,vs60 | |
3525 | + 110: f1 1c e7 87 xvmovdp vs40,vs60 | |
3526 | + 114: f1 1c e7 87 xvmovdp vs40,vs60 | |
3527 | + 118: f1 12 e6 87 xvcpsgnsp vs40,vs50,vs60 | |
3528 | + 11c: f1 1c e6 87 xvmovsp vs40,vs60 | |
3529 | + 120: f1 1c e6 87 xvmovsp vs40,vs60 | |
3530 | + 124: f1 00 e6 27 xvcvdpsp vs40,vs60 | |
3531 | + 128: f1 00 e7 63 xvcvdpsxds vs40,vs60 | |
3532 | + 12c: f1 00 e3 63 xvcvdpsxws vs40,vs60 | |
3533 | + 130: f1 00 e7 23 xvcvdpuxds vs40,vs60 | |
3534 | + 134: f1 00 e3 23 xvcvdpuxws vs40,vs60 | |
3535 | + 138: f1 00 e7 27 xvcvspdp vs40,vs60 | |
3536 | + 13c: f1 00 e6 63 xvcvspsxds vs40,vs60 | |
3537 | + 140: f1 00 e2 63 xvcvspsxws vs40,vs60 | |
3538 | + 144: f1 00 e6 23 xvcvspuxds vs40,vs60 | |
3539 | + 148: f1 00 e2 23 xvcvspuxws vs40,vs60 | |
3540 | + 14c: f1 00 e7 e3 xvcvsxddp vs40,vs60 | |
3541 | + 150: f1 00 e6 e3 xvcvsxdsp vs40,vs60 | |
3542 | + 154: f1 00 e3 e3 xvcvsxwdp vs40,vs60 | |
3543 | + 158: f1 00 e2 e3 xvcvsxwsp vs40,vs60 | |
3544 | + 15c: f1 00 e7 a3 xvcvuxddp vs40,vs60 | |
3545 | + 160: f1 00 e6 a3 xvcvuxdsp vs40,vs60 | |
3546 | + 164: f1 00 e3 a3 xvcvuxwdp vs40,vs60 | |
3547 | + 168: f1 00 e2 a3 xvcvuxwsp vs40,vs60 | |
3548 | + 16c: f1 12 e3 c7 xvdivdp vs40,vs50,vs60 | |
3549 | + 170: f1 12 e2 c7 xvdivsp vs40,vs50,vs60 | |
3550 | + 174: f1 12 e3 0f xvmaddadp vs40,vs50,vs60 | |
3551 | + 178: f1 12 e3 4f xvmaddmdp vs40,vs50,vs60 | |
3552 | + 17c: f1 12 e2 0f xvmaddasp vs40,vs50,vs60 | |
3553 | + 180: f1 12 e2 4f xvmaddmsp vs40,vs50,vs60 | |
3554 | + 184: f1 12 e7 07 xvmaxdp vs40,vs50,vs60 | |
3555 | + 188: f1 12 e6 07 xvmaxsp vs40,vs50,vs60 | |
3556 | + 18c: f1 12 e7 47 xvmindp vs40,vs50,vs60 | |
3557 | + 190: f1 12 e6 47 xvminsp vs40,vs50,vs60 | |
3558 | + 194: f1 12 e3 8f xvmsubadp vs40,vs50,vs60 | |
3559 | + 198: f1 12 e3 cf xvmsubmdp vs40,vs50,vs60 | |
3560 | + 19c: f1 12 e2 8f xvmsubasp vs40,vs50,vs60 | |
3561 | + 1a0: f1 12 e2 cf xvmsubmsp vs40,vs50,vs60 | |
3562 | + 1a4: f1 12 e3 87 xvmuldp vs40,vs50,vs60 | |
3563 | + 1a8: f1 12 e2 87 xvmulsp vs40,vs50,vs60 | |
3564 | + 1ac: f1 00 e7 a7 xvnabsdp vs40,vs60 | |
3565 | + 1b0: f1 00 e6 a7 xvnabssp vs40,vs60 | |
3566 | + 1b4: f1 00 e7 e7 xvnegdp vs40,vs60 | |
3567 | + 1b8: f1 00 e6 e7 xvnegsp vs40,vs60 | |
3568 | + 1bc: f1 12 e7 0f xvnmaddadp vs40,vs50,vs60 | |
3569 | + 1c0: f1 12 e7 4f xvnmaddmdp vs40,vs50,vs60 | |
3570 | + 1c4: f1 12 e6 0f xvnmaddasp vs40,vs50,vs60 | |
3571 | + 1c8: f1 12 e6 4f xvnmaddmsp vs40,vs50,vs60 | |
3572 | + 1cc: f1 12 e7 8f xvnmsubadp vs40,vs50,vs60 | |
3573 | + 1d0: f1 12 e7 cf xvnmsubmdp vs40,vs50,vs60 | |
3574 | + 1d4: f1 12 e6 8f xvnmsubasp vs40,vs50,vs60 | |
3575 | + 1d8: f1 12 e6 cf xvnmsubmsp vs40,vs50,vs60 | |
3576 | + 1dc: f1 00 e3 27 xvrdpi vs40,vs60 | |
3577 | + 1e0: f1 00 e3 af xvrdpic vs40,vs60 | |
3578 | + 1e4: f1 00 e3 e7 xvrdpim vs40,vs60 | |
3579 | + 1e8: f1 00 e3 a7 xvrdpip vs40,vs60 | |
3580 | + 1ec: f1 00 e3 67 xvrdpiz vs40,vs60 | |
3581 | + 1f0: f1 00 e3 6b xvredp vs40,vs60 | |
3582 | + 1f4: f1 00 e2 6b xvresp vs40,vs60 | |
3583 | + 1f8: f1 00 e2 27 xvrspi vs40,vs60 | |
3584 | + 1fc: f1 00 e2 af xvrspic vs40,vs60 | |
3585 | + 200: f1 00 e2 e7 xvrspim vs40,vs60 | |
3586 | + 204: f1 00 e2 a7 xvrspip vs40,vs60 | |
3587 | + 208: f1 00 e2 67 xvrspiz vs40,vs60 | |
3588 | + 20c: f1 00 e3 2b xvrsqrtedp vs40,vs60 | |
3589 | + 210: f1 00 e2 2b xvrsqrtesp vs40,vs60 | |
3590 | + 214: f1 00 e3 2f xvsqrtdp vs40,vs60 | |
3591 | + 218: f1 00 e2 2f xvsqrtsp vs40,vs60 | |
3592 | + 21c: f1 12 e3 47 xvsubdp vs40,vs50,vs60 | |
3593 | + 220: f1 12 e2 47 xvsubsp vs40,vs50,vs60 | |
3594 | + 224: f0 92 e3 ee xvtdivdp cr1,vs50,vs60 | |
3595 | + 228: f0 92 e2 ee xvtdivsp cr1,vs50,vs60 | |
3596 | + 22c: f0 80 e3 aa xvtsqrtdp cr1,vs60 | |
3597 | + 230: f0 80 e2 aa xvtsqrtsp cr1,vs60 | |
3598 | + 234: f1 12 e4 17 xxland vs40,vs50,vs60 | |
3599 | + 238: f1 12 e4 57 xxlandc vs40,vs50,vs60 | |
3600 | + 23c: f1 12 e5 17 xxlnor vs40,vs50,vs60 | |
3601 | + 240: f1 12 e4 97 xxlor vs40,vs50,vs60 | |
3602 | + 244: f1 12 e4 d7 xxlxor vs40,vs50,vs60 | |
3603 | + 248: f1 12 e0 97 xxmrghw vs40,vs50,vs60 | |
3604 | + 24c: f1 12 e1 97 xxmrglw vs40,vs50,vs60 | |
3605 | + 250: f1 12 e0 57 xxmrghd vs40,vs50,vs60 | |
3606 | + 254: f1 12 e1 57 xxpermdi vs40,vs50,vs60,1 | |
3607 | + 258: f1 12 e2 57 xxpermdi vs40,vs50,vs60,2 | |
3608 | + 25c: f1 12 e3 57 xxmrgld vs40,vs50,vs60 | |
3609 | + 260: f1 12 90 57 xxspltd vs40,vs50,0 | |
3610 | + 264: f1 12 90 57 xxspltd vs40,vs50,0 | |
3611 | + 268: f1 12 93 57 xxspltd vs40,vs50,1 | |
3612 | + 26c: f1 12 93 57 xxspltd vs40,vs50,1 | |
3613 | + 270: f1 12 e0 57 xxmrghd vs40,vs50,vs60 | |
3614 | + 274: f1 12 e0 57 xxmrghd vs40,vs50,vs60 | |
3615 | + 278: f1 12 e3 57 xxmrgld vs40,vs50,vs60 | |
3616 | + 27c: f1 12 92 57 xxswapd vs40,vs50 | |
3617 | + 280: f1 12 92 57 xxswapd vs40,vs50 | |
3618 | + 284: f1 12 e7 bf xxsel vs40,vs50,vs60,vs62 | |
3619 | + 288: f1 12 e2 17 xxsldwi vs40,vs50,vs60,2 | |
3620 | + 28c: f1 02 e2 93 xxspltw vs40,vs60,2 | |
3621 | diff -Naur binutils-2.19.1.orig/gas/testsuite/gas/ppc/vsx.s binutils-2.19.1/gas/testsuite/gas/ppc/vsx.s | |
3622 | --- binutils-2.19.1.orig/gas/testsuite/gas/ppc/vsx.s 1969-12-31 16:00:00.000000000 -0800 | |
3623 | +++ binutils-2.19.1/gas/testsuite/gas/ppc/vsx.s 2009-03-02 05:59:36.000000000 -0800 | |
3624 | @@ -0,0 +1,166 @@ | |
3625 | + .section ".text" | |
3626 | +start: | |
3627 | + lxsdx 40,10,20 | |
3628 | + lxsdux 40,10,20 | |
3629 | + lxvd2x 40,10,20 | |
3630 | + lxvd2ux 40,10,20 | |
3631 | + lxvdsx 40,10,20 | |
3632 | + lxvw4x 40,10,20 | |
3633 | + lxvw4ux 40,10,20 | |
3634 | + stxsdx 40,10,20 | |
3635 | + stxsdux 40,10,20 | |
3636 | + stxvd2x 40,10,20 | |
3637 | + stxvd2ux 40,10,20 | |
3638 | + stxvw4x 40,10,20 | |
3639 | + stxvw4ux 40,10,20 | |
3640 | + xsabsdp 40,60 | |
3641 | + xsadddp 40,50,60 | |
3642 | + xscmpodp 1,50,60 | |
3643 | + xscmpudp 1,50,60 | |
3644 | + xscpsgndp 40,50,60 | |
3645 | + xscvdpsp 40,60 | |
3646 | + xscvdpsxds 40,60 | |
3647 | + xscvdpsxws 40,60 | |
3648 | + xscvdpuxds 40,60 | |
3649 | + xscvdpuxws 40,60 | |
3650 | + xscvspdp 40,60 | |
3651 | + xscvsxddp 40,60 | |
3652 | + xscvuxddp 40,60 | |
3653 | + xsdivdp 40,50,60 | |
3654 | + xsmaddadp 40,50,60 | |
3655 | + xsmaddmdp 40,50,60 | |
3656 | + xsmaxdp 40,50,60 | |
3657 | + xsmindp 40,50,60 | |
3658 | + xsmsubadp 40,50,60 | |
3659 | + xsmsubmdp 40,50,60 | |
3660 | + xsmuldp 40,50,60 | |
3661 | + xsnabsdp 40,60 | |
3662 | + xsnegdp 40,60 | |
3663 | + xsnmaddadp 40,50,60 | |
3664 | + xsnmaddmdp 40,50,60 | |
3665 | + xsnmsubadp 40,50,60 | |
3666 | + xsnmsubmdp 40,50,60 | |
3667 | + xsrdpi 40,60 | |
3668 | + xsrdpic 40,60 | |
3669 | + xsrdpim 40,60 | |
3670 | + xsrdpip 40,60 | |
3671 | + xsrdpiz 40,60 | |
3672 | + xsredp 40,60 | |
3673 | + xsrsqrtedp 40,60 | |
3674 | + xssqrtdp 40,60 | |
3675 | + xssubdp 40,50,60 | |
3676 | + xstdivdp 1,50,60 | |
3677 | + xstsqrtdp 1,60 | |
3678 | + xvabsdp 40,60 | |
3679 | + xvabssp 40,60 | |
3680 | + xvadddp 40,50,60 | |
3681 | + xvaddsp 40,50,60 | |
3682 | + xvcmpeqdp 40,50,60 | |
3683 | + xvcmpeqdp. 40,50,60 | |
3684 | + xvcmpeqsp 40,50,60 | |
3685 | + xvcmpeqsp. 40,50,60 | |
3686 | + xvcmpgedp 40,50,60 | |
3687 | + xvcmpgedp. 40,50,60 | |
3688 | + xvcmpgesp 40,50,60 | |
3689 | + xvcmpgesp. 40,50,60 | |
3690 | + xvcmpgtdp 40,50,60 | |
3691 | + xvcmpgtdp. 40,50,60 | |
3692 | + xvcmpgtsp 40,50,60 | |
3693 | + xvcmpgtsp. 40,50,60 | |
3694 | + xvcpsgndp 40,50,60 | |
3695 | + xvmovdp 40,60 | |
3696 | + xvcpsgndp 40,60,60 | |
3697 | + xvcpsgnsp 40,50,60 | |
3698 | + xvmovsp 40,60 | |
3699 | + xvcpsgnsp 40,60,60 | |
3700 | + xvcvdpsp 40,60 | |
3701 | + xvcvdpsxds 40,60 | |
3702 | + xvcvdpsxws 40,60 | |
3703 | + xvcvdpuxds 40,60 | |
3704 | + xvcvdpuxws 40,60 | |
3705 | + xvcvspdp 40,60 | |
3706 | + xvcvspsxds 40,60 | |
3707 | + xvcvspsxws 40,60 | |
3708 | + xvcvspuxds 40,60 | |
3709 | + xvcvspuxws 40,60 | |
3710 | + xvcvsxddp 40,60 | |
3711 | + xvcvsxdsp 40,60 | |
3712 | + xvcvsxwdp 40,60 | |
3713 | + xvcvsxwsp 40,60 | |
3714 | + xvcvuxddp 40,60 | |
3715 | + xvcvuxdsp 40,60 | |
3716 | + xvcvuxwdp 40,60 | |
3717 | + xvcvuxwsp 40,60 | |
3718 | + xvdivdp 40,50,60 | |
3719 | + xvdivsp 40,50,60 | |
3720 | + xvmaddadp 40,50,60 | |
3721 | + xvmaddmdp 40,50,60 | |
3722 | + xvmaddasp 40,50,60 | |
3723 | + xvmaddmsp 40,50,60 | |
3724 | + xvmaxdp 40,50,60 | |
3725 | + xvmaxsp 40,50,60 | |
3726 | + xvmindp 40,50,60 | |
3727 | + xvminsp 40,50,60 | |
3728 | + xvmsubadp 40,50,60 | |
3729 | + xvmsubmdp 40,50,60 | |
3730 | + xvmsubasp 40,50,60 | |
3731 | + xvmsubmsp 40,50,60 | |
3732 | + xvmuldp 40,50,60 | |
3733 | + xvmulsp 40,50,60 | |
3734 | + xvnabsdp 40,60 | |
3735 | + xvnabssp 40,60 | |
3736 | + xvnegdp 40,60 | |
3737 | + xvnegsp 40,60 | |
3738 | + xvnmaddadp 40,50,60 | |
3739 | + xvnmaddmdp 40,50,60 | |
3740 | + xvnmaddasp 40,50,60 | |
3741 | + xvnmaddmsp 40,50,60 | |
3742 | + xvnmsubadp 40,50,60 | |
3743 | + xvnmsubmdp 40,50,60 | |
3744 | + xvnmsubasp 40,50,60 | |
3745 | + xvnmsubmsp 40,50,60 | |
3746 | + xvrdpi 40,60 | |
3747 | + xvrdpic 40,60 | |
3748 | + xvrdpim 40,60 | |
3749 | + xvrdpip 40,60 | |
3750 | + xvrdpiz 40,60 | |
3751 | + xvredp 40,60 | |
3752 | + xvresp 40,60 | |
3753 | + xvrspi 40,60 | |
3754 | + xvrspic 40,60 | |
3755 | + xvrspim 40,60 | |
3756 | + xvrspip 40,60 | |
3757 | + xvrspiz 40,60 | |
3758 | + xvrsqrtedp 40,60 | |
3759 | + xvrsqrtesp 40,60 | |
3760 | + xvsqrtdp 40,60 | |
3761 | + xvsqrtsp 40,60 | |
3762 | + xvsubdp 40,50,60 | |
3763 | + xvsubsp 40,50,60 | |
3764 | + xvtdivdp 1,50,60 | |
3765 | + xvtdivsp 1,50,60 | |
3766 | + xvtsqrtdp 1,60 | |
3767 | + xvtsqrtsp 1,60 | |
3768 | + xxland 40,50,60 | |
3769 | + xxlandc 40,50,60 | |
3770 | + xxlnor 40,50,60 | |
3771 | + xxlor 40,50,60 | |
3772 | + xxlxor 40,50,60 | |
3773 | + xxmrghw 40,50,60 | |
3774 | + xxmrglw 40,50,60 | |
3775 | + xxpermdi 40,50,60,0b00 | |
3776 | + xxpermdi 40,50,60,0b01 | |
3777 | + xxpermdi 40,50,60,0b10 | |
3778 | + xxpermdi 40,50,60,0b11 | |
3779 | + xxspltd 40,50,0 | |
3780 | + xxpermdi 40,50,50,0b00 | |
3781 | + xxspltd 40,50,1 | |
3782 | + xxpermdi 40,50,50,0b11 | |
3783 | + xxmrghd 40,50,60 | |
3784 | + xxpermdi 40,50,60,0b00 | |
3785 | + xxmrgld 40,50,60 | |
3786 | + xxpermdi 40,50,50,0b10 | |
3787 | + xxswapd 40,50 | |
3788 | + xxsel 40,50,60,62 | |
3789 | + xxsldwi 40,50,60,2 | |
3790 | + xxspltw 40,60,2 | |
3791 | diff -Naur binutils-2.19.1.orig/include/elf/ChangeLog binutils-2.19.1/include/elf/ChangeLog | |
3792 | --- binutils-2.19.1.orig/include/elf/ChangeLog 2008-08-20 16:28:58.000000000 -0700 | |
3793 | +++ binutils-2.19.1/include/elf/ChangeLog 2009-03-02 05:41:07.000000000 -0800 | |
3794 | @@ -1,3 +1,11 @@ | |
3795 | +2009-03-02 Alan Modra <amodra@bigpond.net.au> | |
3796 | + | |
3797 | + 2008-11-14 Nathan Sidwell <nathan@codesourcery.com> | |
3798 | + * internal.h (struct elf_segment_map): Add header_size field. | |
3799 | + | |
3800 | + 2008-10-10 Nathan Froyd <froydnj@codesourcery.com> | |
3801 | + * ppc.h: Add Tag_GNU_Power_ABI_Struct_Return. | |
3802 | + | |
3803 | 2008-08-20 Bob Wilson <bob.wilson@acm.org> | |
3804 | ||
3805 | * xtensa.h (R_XTENSA_TLSDESC_FN, R_XTENSA_TLSDESC_ARG) | |
3806 | diff -Naur binutils-2.19.1.orig/include/elf/internal.h binutils-2.19.1/include/elf/internal.h | |
3807 | --- binutils-2.19.1.orig/include/elf/internal.h 2008-03-12 22:27:41.000000000 -0700 | |
3808 | +++ binutils-2.19.1/include/elf/internal.h 2009-03-02 05:41:07.000000000 -0800 | |
3809 | @@ -266,6 +266,8 @@ | |
3810 | bfd_vma p_align; | |
3811 | /* Segment size in file and memory */ | |
3812 | bfd_vma p_size; | |
3813 | + /* Required size of filehdr + phdrs, if non-zero */ | |
3814 | + bfd_vma header_size; | |
3815 | /* Whether the p_flags field is valid; if not, the flags are based | |
3816 | on the section flags. */ | |
3817 | unsigned int p_flags_valid : 1; | |
3818 | diff -Naur binutils-2.19.1.orig/include/elf/ppc.h binutils-2.19.1/include/elf/ppc.h | |
3819 | --- binutils-2.19.1.orig/include/elf/ppc.h 2008-07-26 06:10:47.000000000 -0700 | |
3820 | +++ binutils-2.19.1/include/elf/ppc.h 2009-03-02 05:35:25.000000000 -0800 | |
3821 | @@ -186,6 +186,11 @@ | |
3822 | registers, 3 for SPE registers; 0 for not tagged or not using any | |
3823 | ABIs affected by the differences. */ | |
3824 | Tag_GNU_Power_ABI_Vector = 8, | |
3825 | + | |
3826 | + /* Value 1 for ABIs using r3/r4 for returning structures <= 8 bytes, | |
3827 | + 2 for ABIs using memory; 0 for not tagged or not using any ABIs | |
3828 | + affected by the differences. */ | |
3829 | + Tag_GNU_Power_ABI_Struct_Return = 12 | |
3830 | }; | |
3831 | ||
3832 | #endif /* _ELF_PPC_H */ | |
3833 | diff -Naur binutils-2.19.1.orig/include/opcode/ChangeLog binutils-2.19.1/include/opcode/ChangeLog | |
3834 | --- binutils-2.19.1.orig/include/opcode/ChangeLog 2008-08-28 07:07:48.000000000 -0700 | |
3835 | +++ binutils-2.19.1/include/opcode/ChangeLog 2009-03-02 05:59:36.000000000 -0800 | |
3836 | @@ -1,3 +1,12 @@ | |
3837 | +2009-03-02 Alan Modra <amodra@bigpond.net.au> | |
3838 | + | |
3839 | + 2009-02-26 Peter Bergner <bergner@vnet.ibm.com> | |
3840 | + * ppc.h (PPC_OPCODE_POWER7): New. | |
3841 | + | |
3842 | + 2009-01-09 Peter Bergner <bergner@vnet.ibm.com> | |
3843 | + * ppc.h (struct powerpc_opcode): New field "deprecated". | |
3844 | + (PPC_OPCODE_NOPOWER4): Delete. | |
3845 | + | |
3846 | 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> | |
3847 | ||
3848 | * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update | |
3849 | diff -Naur binutils-2.19.1.orig/include/opcode/ppc.h binutils-2.19.1/include/opcode/ppc.h | |
3850 | --- binutils-2.19.1.orig/include/opcode/ppc.h 2008-08-01 21:38:51.000000000 -0700 | |
3851 | +++ binutils-2.19.1/include/opcode/ppc.h 2009-03-02 05:59:36.000000000 -0800 | |
3852 | @@ -46,6 +46,11 @@ | |
3853 | are listed below. */ | |
3854 | ppc_cpu_t flags; | |
3855 | ||
3856 | + /* One bit flags for the opcode. These are used to indicate which | |
3857 | + specific processors no longer support the instructions. The defined | |
3858 | + values are listed below. */ | |
3859 | + ppc_cpu_t deprecated; | |
3860 | + | |
3861 | /* An array of operand codes. Each code is an index into the | |
3862 | operand table. They appear in the order which the operands must | |
3863 | appear in assembly code, and are terminated by a zero. */ | |
3864 | @@ -109,8 +114,8 @@ | |
3865 | /* Opcode is only supported by Power4 architecture. */ | |
3866 | #define PPC_OPCODE_POWER4 0x4000 | |
3867 | ||
3868 | -/* Opcode isn't supported by Power4 architecture. */ | |
3869 | -#define PPC_OPCODE_NOPOWER4 0x8000 | |
3870 | +/* Opcode is only supported by Power7 architecture. */ | |
3871 | +#define PPC_OPCODE_POWER7 0x8000 | |
3872 | ||
3873 | /* Opcode is only supported by POWERPC Classic architecture. */ | |
3874 | #define PPC_OPCODE_CLASSIC 0x10000 | |
3875 | diff -Naur binutils-2.19.1.orig/ld/ChangeLog binutils-2.19.1/ld/ChangeLog | |
3876 | --- binutils-2.19.1.orig/ld/ChangeLog 2009-02-02 02:31:31.000000000 -0800 | |
3877 | +++ binutils-2.19.1/ld/ChangeLog 2009-03-02 05:56:19.000000000 -0800 | |
3878 | @@ -1,3 +1,65 @@ | |
3879 | +2009-03-02 Alan Modra <amodra@bigpond.net.au> | |
3880 | + | |
3881 | + 2009-02-16 Alan Modra <amodra@bigpond.net.au> | |
3882 | + * ldlang.c (push_stat_ptr, pop_stat_ptr): New functions. | |
3883 | + (stat_save, stat_save_ptr): New variables. | |
3884 | + (lang_insert_orphan): Use push_stat_ptr and pop_stat_ptr. | |
3885 | + (load_symbols): Likewise. Delete dead "bad_load" code. | |
3886 | + (open_input_bfds): Warn on script containing output sections. | |
3887 | + (lang_enter_output_section_statement): Use push_stat_ptr. | |
3888 | + (lang_enter_group): Likewise. | |
3889 | + (lang_leave_output_section_statement): Use pop_stat_ptr. | |
3890 | + (lang_leave_group): Likewise. | |
3891 | + * ldlang.h (push_stat_ptr, pop_stat_ptr): Declare. | |
3892 | + * ldctor.c (ldctor_build_sets): Use push_stat_ptr and pop_stat_ptr. | |
3893 | + * emultempl/beos.em (gld_${EMULATION_NAME}_set_symbols): Likewise. | |
3894 | + * emultempl/pe.em (gld_${EMULATION_NAME}_set_symbols): Likewise. | |
3895 | + * emultempl/pep.em (gld_${EMULATION_NAME}_set_symbols): Likewise. | |
3896 | + * emultempl/xtensaelf.em (ld_xtensa_insert_page_offsets): Likewise. | |
3897 | + | |
3898 | + 2008-10-04 Alan Modra <amodra@bigpond.net.au> | |
3899 | + PR 6931 | |
3900 | + * ldemul.c (ldemul_place_orphan): Add "constraint" param. | |
3901 | + * ldemul.h (ldemul_place_orphan): Update prototype. | |
3902 | + (struct ld_emulation_xfer_struct <place_orphan>): Likewise add param. | |
3903 | + * ldlang.c (unique_section_p): Make static. | |
3904 | + (lang_output_section_statement_lookup): Optimise creation of SPECIAL | |
3905 | + sections. | |
3906 | + (lang_insert_orphan): Add "constraint" param. Pass to | |
3907 | + lang_enter_output_section_statement. | |
3908 | + (init_os): Don't use an existing bfd section for SPECIAL sections. | |
3909 | + (lang_place_orphans): Don't rename unique output sections, instead | |
3910 | + mark their output section statements SPECIAL. | |
3911 | + * ldlang.h (lang_insert_orphan): Update prototype. | |
3912 | + (unique_section_p): Delete. | |
3913 | + * emultempl/beos.em (place_orphan): Add "constraint" param. | |
3914 | + * emultempl/elf32.em (place_orphan): Likewise. Don't match existing | |
3915 | + output sections if set. | |
3916 | + * emultempl/pe.em (place_orphan): Likewise. | |
3917 | + * emultempl/pep.em (place_orphan): Likewise. | |
3918 | + * emultempl/mmo.em (mmo_place_orphan): Update. | |
3919 | + * emultempl/spuelf.em (spu_place_special_section): Update. | |
3920 | + | |
3921 | + 2008-10-03 Alan Modra <amodra@bigpond.net.au> | |
3922 | + PR 6931 | |
3923 | + * ldemul.c (ldemul_place_orphan): Add "name" param. | |
3924 | + * ldemul.h (ldemul_place_orphan): Update prototype. | |
3925 | + (struct ld_emulation_xfer_struct <place_orphan>): Likewise. | |
3926 | + * ldlang.c (lang_place_orphans): Generate unique section names here.. | |
3927 | + * emultempl/elf32.em (place_orphan): ..rather than here. Don't | |
3928 | + directly use an existing output section statement that has no | |
3929 | + bfd section. | |
3930 | + * emultempl/pe.em (place_orphan): Likewise. | |
3931 | + * emultempl/pep.em (place_orphan): Likewise. | |
3932 | + * emultempl/beos.em (place_orphan): Adjust. | |
3933 | + * emultempl/spuelf.em (spu_place_special_section): Adjust | |
3934 | + place_orphan call. | |
3935 | + * emultempl/genelf.em (gld${EMULATION_NAME}_after_open): New function. | |
3936 | + (LDEMUL_AFTER_OPEN): Define. | |
3937 | + | |
3938 | + 2008-09-25 Alan Modra <amodra@bigpond.net.au> | |
3939 | + * ldexp.c (fold_binary): Evaluate rhs when lhs not valid. | |
3940 | + | |
3941 | 2009-02-02 Tristan Gingold <gingold@adacore.com> | |
3942 | ||
3943 | * deffilep.c: Add autogenerated file. | |
3944 | diff -Naur binutils-2.19.1.orig/ld/emultempl/beos.em binutils-2.19.1/ld/emultempl/beos.em | |
3945 | --- binutils-2.19.1.orig/ld/emultempl/beos.em 2008-09-08 17:10:16.000000000 -0700 | |
3946 | +++ binutils-2.19.1/ld/emultempl/beos.em 2009-03-02 05:56:19.000000000 -0800 | |
3947 | @@ -8,7 +8,7 @@ | |
3948 | fragment <<EOF | |
3949 | /* This file is part of GLD, the Gnu Linker. | |
3950 | Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, | |
3951 | - 2005, 2006, 2007, 2008 Free Software Foundation, Inc. | |
3952 | + 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. | |
3953 | ||
3954 | This file is part of the GNU Binutils. | |
3955 | ||
3956 | @@ -330,7 +330,6 @@ | |
3957 | /* Run through and invent symbols for all the | |
3958 | names and insert the defaults. */ | |
3959 | int j; | |
3960 | - lang_statement_list_type *save; | |
3961 | ||
3962 | if (!init[IMAGEBASEOFF].inited) | |
3963 | { | |
3964 | @@ -347,9 +346,7 @@ | |
3965 | return; | |
3966 | ||
3967 | /* Glue the assignments into the abs section */ | |
3968 | - save = stat_ptr; | |
3969 | - | |
3970 | - stat_ptr = &(abs_output_section->children); | |
3971 | + push_stat_ptr (&abs_output_section->children); | |
3972 | ||
3973 | for (j = 0; init[j].ptr; j++) | |
3974 | { | |
3975 | @@ -367,7 +364,7 @@ | |
3976 | else abort(); | |
3977 | } | |
3978 | /* Restore the pointer. */ | |
3979 | - stat_ptr = save; | |
3980 | + pop_stat_ptr (); | |
3981 | ||
3982 | if (pe.FileAlignment > | |
3983 | pe.SectionAlignment) | |
3984 | @@ -609,8 +606,6 @@ | |
3985 | static void | |
3986 | gld_${EMULATION_NAME}_before_allocation (void) | |
3987 | { | |
3988 | - extern lang_statement_list_type *stat_ptr; | |
3989 | - | |
3990 | #ifdef TARGET_IS_ppcpe | |
3991 | /* Here we rummage through the found bfds to collect toc information */ | |
3992 | { | |
3993 | @@ -665,9 +660,10 @@ | |
3994 | which are not mentioned in the linker script. */ | |
3995 | ||
3996 | static bfd_boolean | |
3997 | -gld${EMULATION_NAME}_place_orphan (asection *s) | |
3998 | +gld${EMULATION_NAME}_place_orphan (asection *s, | |
3999 | + const char *secname, | |
4000 | + int constraint) | |
4001 | { | |
4002 | - const char *secname; | |
4003 | char *output_secname, *ps; | |
4004 | lang_output_section_statement_type *os; | |
4005 | lang_statement_union_type *l; | |
4006 | @@ -682,8 +678,6 @@ | |
4007 | if (link_info.relocatable) | |
4008 | return FALSE; | |
4009 | ||
4010 | - secname = bfd_get_section_name (s->owner, s); | |
4011 | - | |
4012 | /* Everything from the '\$' on gets deleted so don't allow '\$' as the | |
4013 | first character. */ | |
4014 | if (*secname == '\$') | |
4015 | @@ -697,7 +691,7 @@ | |
4016 | output_secname = xstrdup (secname); | |
4017 | ps = strchr (output_secname + 1, '\$'); | |
4018 | *ps = 0; | |
4019 | - os = lang_output_section_statement_lookup (output_secname, 0, TRUE); | |
4020 | + os = lang_output_section_statement_lookup (output_secname, constraint, TRUE); | |
4021 | ||
4022 | /* Find the '\$' wild statement for this section. We currently require the | |
4023 | linker script to explicitly mention "*(.foo\$)". | |
4024 | diff -Naur binutils-2.19.1.orig/ld/emultempl/elf32.em binutils-2.19.1/ld/emultempl/elf32.em | |
4025 | --- binutils-2.19.1.orig/ld/emultempl/elf32.em 2008-09-06 21:02:31.000000000 -0700 | |
4026 | +++ binutils-2.19.1/ld/emultempl/elf32.em 2009-03-02 05:34:03.000000000 -0800 | |
4027 | @@ -62,7 +62,8 @@ | |
4028 | static void gld${EMULATION_NAME}_before_parse (void); | |
4029 | static void gld${EMULATION_NAME}_after_open (void); | |
4030 | static void gld${EMULATION_NAME}_before_allocation (void); | |
4031 | -static bfd_boolean gld${EMULATION_NAME}_place_orphan (asection *s); | |
4032 | +static bfd_boolean gld${EMULATION_NAME}_place_orphan | |
4033 | + (asection *, const char *, int); | |
4034 | static void gld${EMULATION_NAME}_finish (void); | |
4035 | ||
4036 | EOF | |
4037 | @@ -1635,7 +1636,9 @@ | |
4038 | sections in the right segment. */ | |
4039 | ||
4040 | static bfd_boolean | |
4041 | -gld${EMULATION_NAME}_place_orphan (asection *s) | |
4042 | +gld${EMULATION_NAME}_place_orphan (asection *s, | |
4043 | + const char *secname, | |
4044 | + int constraint) | |
4045 | { | |
4046 | static struct orphan_save hold[] = | |
4047 | { | |
4048 | @@ -1673,15 +1676,12 @@ | |
4049 | }; | |
4050 | static int orphan_init_done = 0; | |
4051 | struct orphan_save *place; | |
4052 | - const char *secname; | |
4053 | lang_output_section_statement_type *after; | |
4054 | lang_output_section_statement_type *os; | |
4055 | int isdyn = 0; | |
4056 | int iself = s->owner->xvec->flavour == bfd_target_elf_flavour; | |
4057 | unsigned int sh_type = iself ? elf_section_type (s) : SHT_NULL; | |
4058 | ||
4059 | - secname = bfd_get_section_name (s->owner, s); | |
4060 | - | |
4061 | if (! link_info.relocatable | |
4062 | && link_info.combreloc | |
4063 | && (s->flags & SEC_ALLOC)) | |
4064 | @@ -1707,28 +1707,23 @@ | |
4065 | } | |
4066 | } | |
4067 | ||
4068 | - if (isdyn || (!config.unique_orphan_sections && !unique_section_p (s))) | |
4069 | - { | |
4070 | - /* Look through the script to see where to place this section. */ | |
4071 | - os = lang_output_section_find (secname); | |
4072 | - | |
4073 | - if (os != NULL | |
4074 | - && (os->bfd_section == NULL | |
4075 | - || os->bfd_section->flags == 0 | |
4076 | - || (_bfd_elf_match_sections_by_type (link_info.output_bfd, | |
4077 | - os->bfd_section, | |
4078 | - s->owner, s) | |
4079 | - && ((s->flags ^ os->bfd_section->flags) | |
4080 | - & (SEC_LOAD | SEC_ALLOC)) == 0))) | |
4081 | - { | |
4082 | - /* We already have an output section statement with this | |
4083 | - name, and its bfd section, if any, has compatible flags. | |
4084 | - If the section already exists but does not have any flags | |
4085 | - set, then it has been created by the linker, probably as a | |
4086 | - result of a --section-start command line switch. */ | |
4087 | - lang_add_section (&os->children, s, os); | |
4088 | - return TRUE; | |
4089 | - } | |
4090 | + /* Look through the script to see where to place this section. */ | |
4091 | + if (constraint == 0 | |
4092 | + && (os = lang_output_section_find (secname)) != NULL | |
4093 | + && os->bfd_section != NULL | |
4094 | + && (os->bfd_section->flags == 0 | |
4095 | + || (_bfd_elf_match_sections_by_type (link_info.output_bfd, | |
4096 | + os->bfd_section, s->owner, s) | |
4097 | + && ((s->flags ^ os->bfd_section->flags) | |
4098 | + & (SEC_LOAD | SEC_ALLOC)) == 0))) | |
4099 | + { | |
4100 | + /* We already have an output section statement with this | |
4101 | + name, and its bfd section has compatible flags. | |
4102 | + If the section already exists but does not have any flags | |
4103 | + set, then it has been created by the linker, probably as a | |
4104 | + result of a --section-start command line switch. */ | |
4105 | + lang_add_section (&os->children, s, os); | |
4106 | + return TRUE; | |
4107 | } | |
4108 | ||
4109 | if (!orphan_init_done) | |
4110 | @@ -1748,7 +1743,7 @@ | |
4111 | sections into the .text section to get them out of the way. */ | |
4112 | if (link_info.executable | |
4113 | && ! link_info.relocatable | |
4114 | - && CONST_STRNEQ (secname, ".gnu.warning.") | |
4115 | + && CONST_STRNEQ (s->name, ".gnu.warning.") | |
4116 | && hold[orphan_text].os != NULL) | |
4117 | { | |
4118 | lang_add_section (&hold[orphan_text].os->children, s, | |
4119 | @@ -1803,19 +1798,7 @@ | |
4120 | after = &lang_output_section_statement.head->output_section_statement; | |
4121 | } | |
4122 | ||
4123 | - /* Choose a unique name for the section. This will be needed if the | |
4124 | - same section name appears in the input file with different | |
4125 | - loadable or allocatable characteristics. */ | |
4126 | - if (bfd_get_section_by_name (link_info.output_bfd, secname) != NULL) | |
4127 | - { | |
4128 | - static int count = 1; | |
4129 | - secname = bfd_get_unique_section_name (link_info.output_bfd, | |
4130 | - secname, &count); | |
4131 | - if (secname == NULL) | |
4132 | - einfo ("%F%P: place_orphan failed: %E\n"); | |
4133 | - } | |
4134 | - | |
4135 | - lang_insert_orphan (s, secname, after, place, NULL, NULL); | |
4136 | + lang_insert_orphan (s, secname, constraint, after, place, NULL, NULL); | |
4137 | ||
4138 | return TRUE; | |
4139 | } | |
4140 | diff -Naur binutils-2.19.1.orig/ld/emultempl/genelf.em binutils-2.19.1/ld/emultempl/genelf.em | |
4141 | --- binutils-2.19.1.orig/ld/emultempl/genelf.em 2007-07-19 12:56:10.000000000 -0700 | |
4142 | +++ binutils-2.19.1/ld/emultempl/genelf.em 2009-03-02 05:32:55.000000000 -0800 | |
4143 | @@ -34,7 +34,27 @@ | |
4144 | gld${EMULATION_NAME}_map_segments (FALSE); | |
4145 | finish_default (); | |
4146 | } | |
4147 | + | |
4148 | +static void | |
4149 | +gld${EMULATION_NAME}_after_open (void) | |
4150 | +{ | |
4151 | + bfd *ibfd; | |
4152 | + asection *sec; | |
4153 | + asymbol **syms; | |
4154 | + | |
4155 | + if (link_info.relocatable) | |
4156 | + for (ibfd = link_info.input_bfds; ibfd != NULL; ibfd = ibfd->link_next) | |
4157 | + if ((syms = bfd_get_outsymbols (ibfd)) != NULL | |
4158 | + && bfd_get_flavour (ibfd) == bfd_target_elf_flavour) | |
4159 | + for (sec = ibfd->sections; sec != NULL; sec = sec->next) | |
4160 | + if ((sec->flags & (SEC_GROUP | SEC_LINKER_CREATED)) == SEC_GROUP) | |
4161 | + { | |
4162 | + struct bfd_elf_section_data *sec_data = elf_section_data (sec); | |
4163 | + elf_group_id (sec) = syms[sec_data->this_hdr.sh_info - 1]; | |
4164 | + } | |
4165 | +} | |
4166 | EOF | |
4167 | # Put these extra routines in ld_${EMULATION_NAME}_emulation | |
4168 | # | |
4169 | LDEMUL_FINISH=gld${EMULATION_NAME}_finish | |
4170 | +LDEMUL_AFTER_OPEN=gld${EMULATION_NAME}_after_open | |
4171 | diff -Naur binutils-2.19.1.orig/ld/emultempl/mmo.em binutils-2.19.1/ld/emultempl/mmo.em | |
4172 | --- binutils-2.19.1.orig/ld/emultempl/mmo.em 2008-02-14 19:35:53.000000000 -0800 | |
4173 | +++ binutils-2.19.1/ld/emultempl/mmo.em 2009-03-02 05:34:03.000000000 -0800 | |
4174 | @@ -47,7 +47,9 @@ | |
4175 | from elf32.em. */ | |
4176 | ||
4177 | static bfd_boolean | |
4178 | -mmo_place_orphan (asection *s) | |
4179 | +mmo_place_orphan (asection *s, | |
4180 | + const char *secname, | |
4181 | + int constraint ATTRIBUTE_UNUSED) | |
4182 | { | |
4183 | static struct orphan_save hold_text = | |
4184 | { | |
4185 | @@ -56,7 +58,6 @@ | |
4186 | 0, 0, 0, 0 | |
4187 | }; | |
4188 | struct orphan_save *place; | |
4189 | - const char *secname; | |
4190 | lang_output_section_statement_type *after; | |
4191 | lang_output_section_statement_type *os; | |
4192 | ||
4193 | @@ -66,7 +67,6 @@ | |
4194 | return FALSE; | |
4195 | ||
4196 | /* Only care for sections we're going to load. */ | |
4197 | - secname = s->name; | |
4198 | os = lang_output_section_find (secname); | |
4199 | ||
4200 | /* We have an output section by this name. Place the section inside it | |
4201 | @@ -93,7 +93,7 @@ | |
4202 | ||
4203 | /* If there's an output section by this name, we'll use it, regardless | |
4204 | of section flags, in contrast to what's done in elf32.em. */ | |
4205 | - os = lang_insert_orphan (s, secname, after, place, NULL, NULL); | |
4206 | + os = lang_insert_orphan (s, secname, 0, after, place, NULL, NULL); | |
4207 | ||
4208 | /* We need an output section for .text as a root, so if there was none | |
4209 | (might happen with a peculiar linker script such as in "map | |
4210 | diff -Naur binutils-2.19.1.orig/ld/emultempl/pe.em binutils-2.19.1/ld/emultempl/pe.em | |
4211 | --- binutils-2.19.1.orig/ld/emultempl/pe.em 2008-09-09 02:49:56.000000000 -0700 | |
4212 | +++ binutils-2.19.1/ld/emultempl/pe.em 2009-03-02 05:56:19.000000000 -0800 | |
4213 | @@ -10,7 +10,7 @@ | |
4214 | (echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-) | |
4215 | fragment <<EOF | |
4216 | /* Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, | |
4217 | - 2005, 2006, 2007, 2008 Free Software Foundation, Inc. | |
4218 | + 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. | |
4219 | ||
4220 | This file is part of the GNU Binutils. | |
4221 | ||
4222 | @@ -697,7 +697,6 @@ | |
4223 | /* Run through and invent symbols for all the | |
4224 | names and insert the defaults. */ | |
4225 | int j; | |
4226 | - lang_statement_list_type *save; | |
4227 | ||
4228 | if (!init[IMAGEBASEOFF].inited) | |
4229 | { | |
4230 | @@ -720,9 +719,7 @@ | |
4231 | return; | |
4232 | ||
4233 | /* Glue the assignments into the abs section. */ | |
4234 | - save = stat_ptr; | |
4235 | - | |
4236 | - stat_ptr = &(abs_output_section->children); | |
4237 | + push_stat_ptr (&abs_output_section->children); | |
4238 | ||
4239 | for (j = 0; init[j].ptr; j++) | |
4240 | { | |
4241 | @@ -744,7 +741,7 @@ | |
4242 | image_base_statement = rv; | |
4243 | } | |
4244 | /* Restore the pointer. */ | |
4245 | - stat_ptr = save; | |
4246 | + pop_stat_ptr (); | |
4247 | ||
4248 | if (pe.FileAlignment > | |
4249 | pe.SectionAlignment) | |
4250 | @@ -1613,40 +1610,37 @@ | |
4251 | sort_sections. */ | |
4252 | ||
4253 | static bfd_boolean | |
4254 | -gld_${EMULATION_NAME}_place_orphan (asection *s) | |
4255 | +gld_${EMULATION_NAME}_place_orphan (asection *s, | |
4256 | + const char *secname, | |
4257 | + int constraint) | |
4258 | { | |
4259 | - const char *secname; | |
4260 | - const char *orig_secname; | |
4261 | + const char *orig_secname = secname; | |
4262 | char *dollar = NULL; | |
4263 | lang_output_section_statement_type *os; | |
4264 | lang_statement_list_type add_child; | |
4265 | ||
4266 | - secname = bfd_get_section_name (s->owner, s); | |
4267 | - | |
4268 | /* Look through the script to see where to place this section. */ | |
4269 | - orig_secname = secname; | |
4270 | if (!link_info.relocatable | |
4271 | && (dollar = strchr (secname, '$')) != NULL) | |
4272 | { | |
4273 | - size_t len = dollar - orig_secname; | |
4274 | + size_t len = dollar - secname; | |
4275 | char *newname = xmalloc (len + 1); | |
4276 | - memcpy (newname, orig_secname, len); | |
4277 | + memcpy (newname, secname, len); | |
4278 | newname[len] = '\0'; | |
4279 | secname = newname; | |
4280 | } | |
4281 | ||
4282 | - os = lang_output_section_find (secname); | |
4283 | - | |
4284 | lang_list_init (&add_child); | |
4285 | ||
4286 | - if (os != NULL | |
4287 | - && (os->bfd_section == NULL | |
4288 | - || os->bfd_section->flags == 0 | |
4289 | + if (constraint == 0 | |
4290 | + && (os = lang_output_section_find (secname)) != NULL | |
4291 | + && os->bfd_section != NULL | |
4292 | + && (os->bfd_section->flags == 0 | |
4293 | || ((s->flags ^ os->bfd_section->flags) | |
4294 | & (SEC_LOAD | SEC_ALLOC)) == 0)) | |
4295 | { | |
4296 | /* We already have an output section statement with this | |
4297 | - name, and its bfd section, if any, has compatible flags. | |
4298 | + name, and its bfd section has compatible flags. | |
4299 | If the section already exists but does not have any flags set, | |
4300 | then it has been created by the linker, probably as a result of | |
4301 | a --section-start command line switch. */ | |
4302 | @@ -1723,21 +1717,10 @@ | |
4303 | ->output_section_statement); | |
4304 | } | |
4305 | ||
4306 | - /* Choose a unique name for the section. This will be needed if the | |
4307 | - same section name appears in the input file with different | |
4308 | - loadable or allocatable characteristics. */ | |
4309 | - if (bfd_get_section_by_name (link_info.output_bfd, secname) != NULL) | |
4310 | - { | |
4311 | - static int count = 1; | |
4312 | - secname = bfd_get_unique_section_name (link_info.output_bfd, | |
4313 | - secname, &count); | |
4314 | - if (secname == NULL) | |
4315 | - einfo ("%F%P: place_orphan failed: %E\n"); | |
4316 | - } | |
4317 | - | |
4318 | /* All sections in an executable must be aligned to a page boundary. */ | |
4319 | address = exp_unop (ALIGN_K, exp_nameop (NAME, "__section_alignment__")); | |
4320 | - os = lang_insert_orphan (s, secname, after, place, address, &add_child); | |
4321 | + os = lang_insert_orphan (s, secname, constraint, after, place, address, | |
4322 | + &add_child); | |
4323 | } | |
4324 | ||
4325 | { | |
4326 | diff -Naur binutils-2.19.1.orig/ld/emultempl/pep.em binutils-2.19.1/ld/emultempl/pep.em | |
4327 | --- binutils-2.19.1.orig/ld/emultempl/pep.em 2008-09-09 02:49:56.000000000 -0700 | |
4328 | +++ binutils-2.19.1/ld/emultempl/pep.em 2009-03-02 05:56:19.000000000 -0800 | |
4329 | @@ -9,7 +9,7 @@ | |
4330 | rm -f e${EMULATION_NAME}.c | |
4331 | (echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-) | |
4332 | fragment <<EOF | |
4333 | -/* Copyright 2006, 2007, 2008 Free Software Foundation, Inc. | |
4334 | +/* Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. | |
4335 | Written by Kai Tietz, OneVision Software GmbH&CoKg. | |
4336 | ||
4337 | This file is part of the GNU Binutils. | |
4338 | @@ -657,7 +657,6 @@ | |
4339 | /* Run through and invent symbols for all the | |
4340 | names and insert the defaults. */ | |
4341 | int j; | |
4342 | - lang_statement_list_type *save; | |
4343 | ||
4344 | if (!init[IMAGEBASEOFF].inited) | |
4345 | { | |
4346 | @@ -680,9 +679,7 @@ | |
4347 | return; | |
4348 | ||
4349 | /* Glue the assignments into the abs section. */ | |
4350 | - save = stat_ptr; | |
4351 | - | |
4352 | - stat_ptr = &(abs_output_section->children); | |
4353 | + push_stat_ptr (&abs_output_section->children); | |
4354 | ||
4355 | for (j = 0; init[j].ptr; j++) | |
4356 | { | |
4357 | @@ -704,7 +701,7 @@ | |
4358 | image_base_statement = rv; | |
4359 | } | |
4360 | /* Restore the pointer. */ | |
4361 | - stat_ptr = save; | |
4362 | + pop_stat_ptr (); | |
4363 | ||
4364 | if (pep.FileAlignment > pep.SectionAlignment) | |
4365 | { | |
4366 | @@ -1372,40 +1369,37 @@ | |
4367 | sort_sections. */ | |
4368 | ||
4369 | static bfd_boolean | |
4370 | -gld_${EMULATION_NAME}_place_orphan (asection *s) | |
4371 | +gld_${EMULATION_NAME}_place_orphan (asection *s, | |
4372 | + const char *secname, | |
4373 | + int constraint) | |
4374 | { | |
4375 | - const char *secname; | |
4376 | - const char *orig_secname; | |
4377 | + const char *orig_secname = secname; | |
4378 | char *dollar = NULL; | |
4379 | lang_output_section_statement_type *os; | |
4380 | lang_statement_list_type add_child; | |
4381 | ||
4382 | - secname = bfd_get_section_name (s->owner, s); | |
4383 | - | |
4384 | /* Look through the script to see where to place this section. */ | |
4385 | - orig_secname = secname; | |
4386 | if (!link_info.relocatable | |
4387 | && (dollar = strchr (secname, '$')) != NULL) | |
4388 | { | |
4389 | - size_t len = dollar - orig_secname; | |
4390 | + size_t len = dollar - secname; | |
4391 | char *newname = xmalloc (len + 1); | |
4392 | - memcpy (newname, orig_secname, len); | |
4393 | + memcpy (newname, secname, len); | |
4394 | newname[len] = '\0'; | |
4395 | secname = newname; | |
4396 | } | |
4397 | ||
4398 | - os = lang_output_section_find (secname); | |
4399 | - | |
4400 | lang_list_init (&add_child); | |
4401 | ||
4402 | - if (os != NULL | |
4403 | - && (os->bfd_section == NULL | |
4404 | - || os->bfd_section->flags == 0 | |
4405 | + if (constraint == 0 | |
4406 | + && (os = lang_output_section_find (secname)) != NULL | |
4407 | + && os->bfd_section != NULL | |
4408 | + && (os->bfd_section->flags == 0 | |
4409 | || ((s->flags ^ os->bfd_section->flags) | |
4410 | & (SEC_LOAD | SEC_ALLOC)) == 0)) | |
4411 | { | |
4412 | /* We already have an output section statement with this | |
4413 | - name, and its bfd section, if any, has compatible flags. | |
4414 | + name, and its bfd section has compatible flags. | |
4415 | If the section already exists but does not have any flags set, | |
4416 | then it has been created by the linker, probably as a result of | |
4417 | a --section-start command line switch. */ | |
4418 | @@ -1482,21 +1476,10 @@ | |
4419 | ->output_section_statement); | |
4420 | } | |
4421 | ||
4422 | - /* Choose a unique name for the section. This will be needed if the | |
4423 | - same section name appears in the input file with different | |
4424 | - loadable or allocatable characteristics. */ | |
4425 | - if (bfd_get_section_by_name (link_info.output_bfd, secname) != NULL) | |
4426 | - { | |
4427 | - static int count = 1; | |
4428 | - secname = bfd_get_unique_section_name (link_info.output_bfd, | |
4429 | - secname, &count); | |
4430 | - if (secname == NULL) | |
4431 | - einfo ("%F%P: place_orphan failed: %E\n"); | |
4432 | - } | |
4433 | - | |
4434 | /* All sections in an executable must be aligned to a page boundary. */ | |
4435 | address = exp_unop (ALIGN_K, exp_nameop (NAME, "__section_alignment__")); | |
4436 | - os = lang_insert_orphan (s, secname, after, place, address, &add_child); | |
4437 | + os = lang_insert_orphan (s, secname, constraint, after, place, address, | |
4438 | + &add_child); | |
4439 | } | |
4440 | ||
4441 | { | |
4442 | diff -Naur binutils-2.19.1.orig/ld/emultempl/spuelf.em binutils-2.19.1/ld/emultempl/spuelf.em | |
4443 | --- binutils-2.19.1.orig/ld/emultempl/spuelf.em 2008-08-02 09:25:44.000000000 -0700 | |
4444 | +++ binutils-2.19.1/ld/emultempl/spuelf.em 2009-03-02 05:34:03.000000000 -0800 | |
4445 | @@ -114,12 +114,7 @@ | |
4446 | ||
4447 | os = lang_output_section_find (o != NULL ? o->name : output_name); | |
4448 | if (os == NULL) | |
4449 | - { | |
4450 | - const char *save = s->name; | |
4451 | - s->name = output_name; | |
4452 | - gld${EMULATION_NAME}_place_orphan (s); | |
4453 | - s->name = save; | |
4454 | - } | |
4455 | + gld${EMULATION_NAME}_place_orphan (s, output_name, 0); | |
4456 | else if (o != NULL && os->children.head != NULL) | |
4457 | { | |
4458 | lang_statement_list_type add; | |
4459 | diff -Naur binutils-2.19.1.orig/ld/emultempl/xtensaelf.em binutils-2.19.1/ld/emultempl/xtensaelf.em | |
4460 | --- binutils-2.19.1.orig/ld/emultempl/xtensaelf.em 2008-02-14 19:35:53.000000000 -0800 | |
4461 | +++ binutils-2.19.1/ld/emultempl/xtensaelf.em 2009-03-02 05:56:19.000000000 -0800 | |
4462 | @@ -1,5 +1,5 @@ | |
4463 | # This shell script emits a C file. -*- C -*- | |
4464 | -# Copyright 2003, 2004, 2005, 2006, 2007, 2008 | |
4465 | +# Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009 | |
4466 | # Free Software Foundation, Inc. | |
4467 | # | |
4468 | # This file is part of the GNU Binutils. | |
4469 | @@ -1951,20 +1951,17 @@ | |
4470 | lang_assignment_statement_type *assign_stmt; | |
4471 | lang_statement_union_type *assign_union; | |
4472 | lang_statement_list_type tmplist; | |
4473 | - lang_statement_list_type *old_stat_ptr = stat_ptr; | |
4474 | ||
4475 | /* There is hidden state in "lang_add_assignment". It | |
4476 | appends the new assignment statement to the stat_ptr | |
4477 | list. Thus, we swap it before and after the call. */ | |
4478 | ||
4479 | - tmplist.head = NULL; | |
4480 | - tmplist.tail = &tmplist.head; | |
4481 | - | |
4482 | - stat_ptr = &tmplist; | |
4483 | + lang_list_init (&tmplist); | |
4484 | + push_stat_ptr (&tmplist); | |
4485 | /* Warning: side effect; statement appended to stat_ptr. */ | |
4486 | assign_stmt = lang_add_assignment (assign_op); | |
4487 | assign_union = (lang_statement_union_type *) assign_stmt; | |
4488 | - stat_ptr = old_stat_ptr; | |
4489 | + pop_stat_ptr (); | |
4490 | ||
4491 | assign_union->header.next = l; | |
4492 | *(*stack_p)->iterloc.loc = assign_union; | |
4493 | diff -Naur binutils-2.19.1.orig/ld/ldctor.c binutils-2.19.1/ld/ldctor.c | |
4494 | --- binutils-2.19.1.orig/ld/ldctor.c 2008-02-14 19:35:53.000000000 -0800 | |
4495 | +++ binutils-2.19.1/ld/ldctor.c 2009-03-02 05:56:19.000000000 -0800 | |
4496 | @@ -1,6 +1,7 @@ | |
4497 | /* ldctor.c -- constructor support routines | |
4498 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, | |
4499 | - 2002, 2003, 2004, 2006, 2007, 2008 Free Software Foundation, Inc. | |
4500 | + 2002, 2003, 2004, 2006, 2007, 2008, 2009 | |
4501 | + Free Software Foundation, Inc. | |
4502 | By Steve Chamberlain <sac@cygnus.com> | |
4503 | ||
4504 | This file is part of the GNU Binutils. | |
4505 | @@ -198,7 +199,6 @@ | |
4506 | ldctor_build_sets (void) | |
4507 | { | |
4508 | static bfd_boolean called; | |
4509 | - lang_statement_list_type *old; | |
4510 | bfd_boolean header_printed; | |
4511 | struct set_info *p; | |
4512 | ||
4513 | @@ -244,10 +244,8 @@ | |
4514 | } | |
4515 | } | |
4516 | ||
4517 | - old = stat_ptr; | |
4518 | - stat_ptr = &constructor_list; | |
4519 | - | |
4520 | - lang_list_init (stat_ptr); | |
4521 | + lang_list_init (&constructor_list); | |
4522 | + push_stat_ptr (&constructor_list); | |
4523 | ||
4524 | header_printed = FALSE; | |
4525 | for (p = sets; p != NULL; p = p->next) | |
4526 | @@ -372,5 +370,5 @@ | |
4527 | lang_add_data (size, exp_intop (0)); | |
4528 | } | |
4529 | ||
4530 | - stat_ptr = old; | |
4531 | + pop_stat_ptr (); | |
4532 | } | |
4533 | diff -Naur binutils-2.19.1.orig/ld/ldemul.c binutils-2.19.1/ld/ldemul.c | |
4534 | --- binutils-2.19.1.orig/ld/ldemul.c 2008-02-14 19:35:53.000000000 -0800 | |
4535 | +++ binutils-2.19.1/ld/ldemul.c 2009-03-02 05:34:02.000000000 -0800 | |
4536 | @@ -120,10 +120,10 @@ | |
4537 | } | |
4538 | ||
4539 | bfd_boolean | |
4540 | -ldemul_place_orphan (asection *s) | |
4541 | +ldemul_place_orphan (asection *s, const char *name, int constraint) | |
4542 | { | |
4543 | if (ld_emulation->place_orphan) | |
4544 | - return (*ld_emulation->place_orphan) (s); | |
4545 | + return (*ld_emulation->place_orphan) (s, name, constraint); | |
4546 | return FALSE; | |
4547 | } | |
4548 | ||
4549 | diff -Naur binutils-2.19.1.orig/ld/ldemul.h binutils-2.19.1/ld/ldemul.h | |
4550 | --- binutils-2.19.1.orig/ld/ldemul.h 2007-07-06 07:09:41.000000000 -0700 | |
4551 | +++ binutils-2.19.1/ld/ldemul.h 2009-03-02 05:34:02.000000000 -0800 | |
4552 | @@ -59,7 +59,7 @@ | |
4553 | extern void ldemul_create_output_section_statements | |
4554 | (void); | |
4555 | extern bfd_boolean ldemul_place_orphan | |
4556 | - (asection *); | |
4557 | + (asection *, const char *, int); | |
4558 | extern bfd_boolean ldemul_parse_args | |
4559 | (int, char **); | |
4560 | extern void ldemul_add_options | |
4561 | @@ -152,7 +152,7 @@ | |
4562 | the default action should be taken. This field may be NULL, in | |
4563 | which case the default action will always be taken. */ | |
4564 | bfd_boolean (*place_orphan) | |
4565 | - (asection *); | |
4566 | + (asection *, const char *, int); | |
4567 | ||
4568 | /* Run after assigning parsing with the args, but before | |
4569 | reading the script. Used to initialize symbols used in the script. */ | |
4570 | diff -Naur binutils-2.19.1.orig/ld/ldexp.c binutils-2.19.1/ld/ldexp.c | |
4571 | --- binutils-2.19.1.orig/ld/ldexp.c 2008-08-21 06:10:54.000000000 -0700 | |
4572 | +++ binutils-2.19.1/ld/ldexp.c 2009-03-02 05:29:32.000000000 -0800 | |
4573 | @@ -282,6 +282,7 @@ | |
4574 | static void | |
4575 | fold_binary (etree_type *tree) | |
4576 | { | |
4577 | + etree_value_type lhs; | |
4578 | exp_fold_tree_1 (tree->binary.lhs); | |
4579 | ||
4580 | /* The SEGMENT_START operator is special because its first | |
4581 | @@ -304,169 +305,167 @@ | |
4582 | expld.result.section = expld.section; | |
4583 | break; | |
4584 | } | |
4585 | + return; | |
4586 | } | |
4587 | - else if (expld.result.valid_p) | |
4588 | - { | |
4589 | - etree_value_type lhs = expld.result; | |
4590 | ||
4591 | - exp_fold_tree_1 (tree->binary.rhs); | |
4592 | - if (expld.result.valid_p) | |
4593 | - { | |
4594 | - /* If the values are from different sections, or this is an | |
4595 | - absolute expression, make both the source arguments | |
4596 | - absolute. However, adding or subtracting an absolute | |
4597 | - value from a relative value is meaningful, and is an | |
4598 | - exception. */ | |
4599 | - if (expld.section != bfd_abs_section_ptr | |
4600 | - && lhs.section == bfd_abs_section_ptr | |
4601 | - && tree->type.node_code == '+') | |
4602 | - { | |
4603 | - /* Keep the section of the rhs term. */ | |
4604 | - expld.result.value = lhs.value + expld.result.value; | |
4605 | - return; | |
4606 | - } | |
4607 | - else if (expld.section != bfd_abs_section_ptr | |
4608 | - && expld.result.section == bfd_abs_section_ptr | |
4609 | - && (tree->type.node_code == '+' | |
4610 | - || tree->type.node_code == '-')) | |
4611 | - { | |
4612 | - /* Keep the section of the lhs term. */ | |
4613 | - expld.result.section = lhs.section; | |
4614 | - } | |
4615 | - else if (expld.result.section != lhs.section | |
4616 | - || expld.section == bfd_abs_section_ptr) | |
4617 | - { | |
4618 | - make_abs (); | |
4619 | - lhs.value += lhs.section->vma; | |
4620 | - } | |
4621 | - | |
4622 | - switch (tree->type.node_code) | |
4623 | - { | |
4624 | - case '%': | |
4625 | - if (expld.result.value != 0) | |
4626 | - expld.result.value = ((bfd_signed_vma) lhs.value | |
4627 | - % (bfd_signed_vma) expld.result.value); | |
4628 | - else if (expld.phase != lang_mark_phase_enum) | |
4629 | - einfo (_("%F%S %% by zero\n")); | |
4630 | - break; | |
4631 | + lhs = expld.result; | |
4632 | + exp_fold_tree_1 (tree->binary.rhs); | |
4633 | + expld.result.valid_p &= lhs.valid_p; | |
4634 | ||
4635 | - case '/': | |
4636 | - if (expld.result.value != 0) | |
4637 | - expld.result.value = ((bfd_signed_vma) lhs.value | |
4638 | - / (bfd_signed_vma) expld.result.value); | |
4639 | - else if (expld.phase != lang_mark_phase_enum) | |
4640 | - einfo (_("%F%S / by zero\n")); | |
4641 | - break; | |
4642 | + if (expld.result.valid_p) | |
4643 | + { | |
4644 | + /* If the values are from different sections, or this is an | |
4645 | + absolute expression, make both the source arguments | |
4646 | + absolute. However, adding or subtracting an absolute | |
4647 | + value from a relative value is meaningful, and is an | |
4648 | + exception. */ | |
4649 | + if (expld.section != bfd_abs_section_ptr | |
4650 | + && lhs.section == bfd_abs_section_ptr | |
4651 | + && tree->type.node_code == '+') | |
4652 | + { | |
4653 | + /* Keep the section of the rhs term. */ | |
4654 | + expld.result.value = lhs.value + expld.result.value; | |
4655 | + return; | |
4656 | + } | |
4657 | + else if (expld.section != bfd_abs_section_ptr | |
4658 | + && expld.result.section == bfd_abs_section_ptr | |
4659 | + && (tree->type.node_code == '+' | |
4660 | + || tree->type.node_code == '-')) | |
4661 | + { | |
4662 | + /* Keep the section of the lhs term. */ | |
4663 | + expld.result.section = lhs.section; | |
4664 | + } | |
4665 | + else if (expld.result.section != lhs.section | |
4666 | + || expld.section == bfd_abs_section_ptr) | |
4667 | + { | |
4668 | + make_abs (); | |
4669 | + lhs.value += lhs.section->vma; | |
4670 | + } | |
4671 | + | |
4672 | + switch (tree->type.node_code) | |
4673 | + { | |
4674 | + case '%': | |
4675 | + if (expld.result.value != 0) | |
4676 | + expld.result.value = ((bfd_signed_vma) lhs.value | |
4677 | + % (bfd_signed_vma) expld.result.value); | |
4678 | + else if (expld.phase != lang_mark_phase_enum) | |
4679 | + einfo (_("%F%S %% by zero\n")); | |
4680 | + break; | |
4681 | + | |
4682 | + case '/': | |
4683 | + if (expld.result.value != 0) | |
4684 | + expld.result.value = ((bfd_signed_vma) lhs.value | |
4685 | + / (bfd_signed_vma) expld.result.value); | |
4686 | + else if (expld.phase != lang_mark_phase_enum) | |
4687 | + einfo (_("%F%S / by zero\n")); | |
4688 | + break; | |
4689 | ||
4690 | #define BOP(x, y) \ | |
4691 | case x: \ | |
4692 | expld.result.value = lhs.value y expld.result.value; \ | |
4693 | break; | |
4694 | ||
4695 | - BOP ('+', +); | |
4696 | - BOP ('*', *); | |
4697 | - BOP ('-', -); | |
4698 | - BOP (LSHIFT, <<); | |
4699 | - BOP (RSHIFT, >>); | |
4700 | - BOP (EQ, ==); | |
4701 | - BOP (NE, !=); | |
4702 | - BOP ('<', <); | |
4703 | - BOP ('>', >); | |
4704 | - BOP (LE, <=); | |
4705 | - BOP (GE, >=); | |
4706 | - BOP ('&', &); | |
4707 | - BOP ('^', ^); | |
4708 | - BOP ('|', |); | |
4709 | - BOP (ANDAND, &&); | |
4710 | - BOP (OROR, ||); | |
4711 | - | |
4712 | - case MAX_K: | |
4713 | - if (lhs.value > expld.result.value) | |
4714 | - expld.result.value = lhs.value; | |
4715 | - break; | |
4716 | - | |
4717 | - case MIN_K: | |
4718 | - if (lhs.value < expld.result.value) | |
4719 | - expld.result.value = lhs.value; | |
4720 | - break; | |
4721 | - | |
4722 | - case ALIGN_K: | |
4723 | - expld.result.value = align_n (lhs.value, expld.result.value); | |
4724 | - break; | |
4725 | - | |
4726 | - case DATA_SEGMENT_ALIGN: | |
4727 | - expld.dataseg.relro = exp_dataseg_relro_start; | |
4728 | - if (expld.phase != lang_first_phase_enum | |
4729 | - && expld.section == bfd_abs_section_ptr | |
4730 | - && (expld.dataseg.phase == exp_dataseg_none | |
4731 | - || expld.dataseg.phase == exp_dataseg_adjust | |
4732 | - || expld.dataseg.phase == exp_dataseg_relro_adjust | |
4733 | - || expld.phase == lang_final_phase_enum)) | |
4734 | + BOP ('+', +); | |
4735 | + BOP ('*', *); | |
4736 | + BOP ('-', -); | |
4737 | + BOP (LSHIFT, <<); | |
4738 | + BOP (RSHIFT, >>); | |
4739 | + BOP (EQ, ==); | |
4740 | + BOP (NE, !=); | |
4741 | + BOP ('<', <); | |
4742 | + BOP ('>', >); | |
4743 | + BOP (LE, <=); | |
4744 | + BOP (GE, >=); | |
4745 | + BOP ('&', &); | |
4746 | + BOP ('^', ^); | |
4747 | + BOP ('|', |); | |
4748 | + BOP (ANDAND, &&); | |
4749 | + BOP (OROR, ||); | |
4750 | + | |
4751 | + case MAX_K: | |
4752 | + if (lhs.value > expld.result.value) | |
4753 | + expld.result.value = lhs.value; | |
4754 | + break; | |
4755 | + | |
4756 | + case MIN_K: | |
4757 | + if (lhs.value < expld.result.value) | |
4758 | + expld.result.value = lhs.value; | |
4759 | + break; | |
4760 | + | |
4761 | + case ALIGN_K: | |
4762 | + expld.result.value = align_n (lhs.value, expld.result.value); | |
4763 | + break; | |
4764 | + | |
4765 | + case DATA_SEGMENT_ALIGN: | |
4766 | + expld.dataseg.relro = exp_dataseg_relro_start; | |
4767 | + if (expld.phase != lang_first_phase_enum | |
4768 | + && expld.section == bfd_abs_section_ptr | |
4769 | + && (expld.dataseg.phase == exp_dataseg_none | |
4770 | + || expld.dataseg.phase == exp_dataseg_adjust | |
4771 | + || expld.dataseg.phase == exp_dataseg_relro_adjust | |
4772 | + || expld.phase == lang_final_phase_enum)) | |
4773 | + { | |
4774 | + bfd_vma maxpage = lhs.value; | |
4775 | + bfd_vma commonpage = expld.result.value; | |
4776 | + | |
4777 | + expld.result.value = align_n (expld.dot, maxpage); | |
4778 | + if (expld.dataseg.phase == exp_dataseg_relro_adjust) | |
4779 | + expld.result.value = expld.dataseg.base; | |
4780 | + else if (expld.dataseg.phase != exp_dataseg_adjust) | |
4781 | { | |
4782 | - bfd_vma maxpage = lhs.value; | |
4783 | - bfd_vma commonpage = expld.result.value; | |
4784 | - | |
4785 | - expld.result.value = align_n (expld.dot, maxpage); | |
4786 | - if (expld.dataseg.phase == exp_dataseg_relro_adjust) | |
4787 | - expld.result.value = expld.dataseg.base; | |
4788 | - else if (expld.dataseg.phase != exp_dataseg_adjust) | |
4789 | + expld.result.value += expld.dot & (maxpage - 1); | |
4790 | + if (expld.phase == lang_allocating_phase_enum) | |
4791 | { | |
4792 | - expld.result.value += expld.dot & (maxpage - 1); | |
4793 | - if (expld.phase == lang_allocating_phase_enum) | |
4794 | - { | |
4795 | - expld.dataseg.phase = exp_dataseg_align_seen; | |
4796 | - expld.dataseg.min_base = expld.dot; | |
4797 | - expld.dataseg.base = expld.result.value; | |
4798 | - expld.dataseg.pagesize = commonpage; | |
4799 | - expld.dataseg.maxpagesize = maxpage; | |
4800 | - expld.dataseg.relro_end = 0; | |
4801 | - } | |
4802 | + expld.dataseg.phase = exp_dataseg_align_seen; | |
4803 | + expld.dataseg.min_base = expld.dot; | |
4804 | + expld.dataseg.base = expld.result.value; | |
4805 | + expld.dataseg.pagesize = commonpage; | |
4806 | + expld.dataseg.maxpagesize = maxpage; | |
4807 | + expld.dataseg.relro_end = 0; | |
4808 | } | |
4809 | - else if (commonpage < maxpage) | |
4810 | - expld.result.value += ((expld.dot + commonpage - 1) | |
4811 | - & (maxpage - commonpage)); | |
4812 | } | |
4813 | - else | |
4814 | - expld.result.valid_p = FALSE; | |
4815 | - break; | |
4816 | + else if (commonpage < maxpage) | |
4817 | + expld.result.value += ((expld.dot + commonpage - 1) | |
4818 | + & (maxpage - commonpage)); | |
4819 | + } | |
4820 | + else | |
4821 | + expld.result.valid_p = FALSE; | |
4822 | + break; | |
4823 | ||
4824 | - case DATA_SEGMENT_RELRO_END: | |
4825 | - expld.dataseg.relro = exp_dataseg_relro_end; | |
4826 | - if (expld.phase != lang_first_phase_enum | |
4827 | - && (expld.dataseg.phase == exp_dataseg_align_seen | |
4828 | - || expld.dataseg.phase == exp_dataseg_adjust | |
4829 | - || expld.dataseg.phase == exp_dataseg_relro_adjust | |
4830 | - || expld.phase == lang_final_phase_enum)) | |
4831 | + case DATA_SEGMENT_RELRO_END: | |
4832 | + expld.dataseg.relro = exp_dataseg_relro_end; | |
4833 | + if (expld.phase != lang_first_phase_enum | |
4834 | + && (expld.dataseg.phase == exp_dataseg_align_seen | |
4835 | + || expld.dataseg.phase == exp_dataseg_adjust | |
4836 | + || expld.dataseg.phase == exp_dataseg_relro_adjust | |
4837 | + || expld.phase == lang_final_phase_enum)) | |
4838 | + { | |
4839 | + if (expld.dataseg.phase == exp_dataseg_align_seen | |
4840 | + || expld.dataseg.phase == exp_dataseg_relro_adjust) | |
4841 | + expld.dataseg.relro_end = lhs.value + expld.result.value; | |
4842 | + | |
4843 | + if (expld.dataseg.phase == exp_dataseg_relro_adjust | |
4844 | + && (expld.dataseg.relro_end | |
4845 | + & (expld.dataseg.pagesize - 1))) | |
4846 | { | |
4847 | - if (expld.dataseg.phase == exp_dataseg_align_seen | |
4848 | - || expld.dataseg.phase == exp_dataseg_relro_adjust) | |
4849 | - expld.dataseg.relro_end = lhs.value + expld.result.value; | |
4850 | - | |
4851 | - if (expld.dataseg.phase == exp_dataseg_relro_adjust | |
4852 | - && (expld.dataseg.relro_end | |
4853 | - & (expld.dataseg.pagesize - 1))) | |
4854 | - { | |
4855 | - expld.dataseg.relro_end += expld.dataseg.pagesize - 1; | |
4856 | - expld.dataseg.relro_end &= ~(expld.dataseg.pagesize - 1); | |
4857 | - expld.result.value = (expld.dataseg.relro_end | |
4858 | - - expld.result.value); | |
4859 | - } | |
4860 | - else | |
4861 | - expld.result.value = lhs.value; | |
4862 | - | |
4863 | - if (expld.dataseg.phase == exp_dataseg_align_seen) | |
4864 | - expld.dataseg.phase = exp_dataseg_relro_seen; | |
4865 | + expld.dataseg.relro_end += expld.dataseg.pagesize - 1; | |
4866 | + expld.dataseg.relro_end &= ~(expld.dataseg.pagesize - 1); | |
4867 | + expld.result.value = (expld.dataseg.relro_end | |
4868 | + - expld.result.value); | |
4869 | } | |
4870 | else | |
4871 | - expld.result.valid_p = FALSE; | |
4872 | - break; | |
4873 | + expld.result.value = lhs.value; | |
4874 | ||
4875 | - default: | |
4876 | - FAIL (); | |
4877 | + if (expld.dataseg.phase == exp_dataseg_align_seen) | |
4878 | + expld.dataseg.phase = exp_dataseg_relro_seen; | |
4879 | } | |
4880 | + else | |
4881 | + expld.result.valid_p = FALSE; | |
4882 | + break; | |
4883 | + | |
4884 | + default: | |
4885 | + FAIL (); | |
4886 | } | |
4887 | - else | |
4888 | - expld.result.valid_p = FALSE; | |
4889 | } | |
4890 | } | |
4891 | ||
4892 | diff -Naur binutils-2.19.1.orig/ld/ldlang.c binutils-2.19.1/ld/ldlang.c | |
4893 | --- binutils-2.19.1.orig/ld/ldlang.c 2008-09-06 21:02:30.000000000 -0700 | |
4894 | +++ binutils-2.19.1/ld/ldlang.c 2009-03-02 05:56:19.000000000 -0800 | |
4895 | @@ -1,6 +1,6 @@ | |
4896 | /* Linker command language support. | |
4897 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, | |
4898 | - 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 | |
4899 | + 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 | |
4900 | Free Software Foundation, Inc. | |
4901 | ||
4902 | This file is part of the GNU Binutils. | |
4903 | @@ -64,6 +64,8 @@ | |
4904 | static const char *output_target; | |
4905 | static lang_statement_list_type statement_list; | |
4906 | static struct bfd_hash_table lang_definedness_table; | |
4907 | +static lang_statement_list_type *stat_save[10]; | |
4908 | +static lang_statement_list_type **stat_save_ptr = &stat_save[0]; | |
4909 | ||
4910 | /* Forward declarations. */ | |
4911 | static void exp_init_os (etree_type *); | |
4912 | @@ -193,7 +195,7 @@ | |
4913 | return match; | |
4914 | } | |
4915 | ||
4916 | -bfd_boolean | |
4917 | +static bfd_boolean | |
4918 | unique_section_p (const asection *sec) | |
4919 | { | |
4920 | struct unique_sections *unam; | |
4921 | @@ -925,6 +927,23 @@ | |
4922 | list->tail = &list->head; | |
4923 | } | |
4924 | ||
4925 | +void | |
4926 | +push_stat_ptr (lang_statement_list_type *new_ptr) | |
4927 | +{ | |
4928 | + if (stat_save_ptr >= stat_save + sizeof (stat_save) / sizeof (stat_save[0])) | |
4929 | + abort (); | |
4930 | + *stat_save_ptr++ = stat_ptr; | |
4931 | + stat_ptr = new_ptr; | |
4932 | +} | |
4933 | + | |
4934 | +void | |
4935 | +pop_stat_ptr (void) | |
4936 | +{ | |
4937 | + if (stat_save_ptr <= stat_save) | |
4938 | + abort (); | |
4939 | + stat_ptr = *--stat_save_ptr; | |
4940 | +} | |
4941 | + | |
4942 | /* Build a new statement node for the parse tree. */ | |
4943 | ||
4944 | static lang_statement_union_type * | |
4945 | @@ -1278,19 +1297,25 @@ | |
4946 | struct out_section_hash_entry *last_ent; | |
4947 | unsigned long hash = entry->root.hash; | |
4948 | ||
4949 | - do | |
4950 | - { | |
4951 | - if (entry->s.output_section_statement.constraint >= 0 | |
4952 | - && (constraint == 0 | |
4953 | - || (constraint == entry->s.output_section_statement.constraint | |
4954 | - && constraint != SPECIAL))) | |
4955 | - return &entry->s.output_section_statement; | |
4956 | - last_ent = entry; | |
4957 | - entry = (struct out_section_hash_entry *) entry->root.next; | |
4958 | - } | |
4959 | - while (entry != NULL | |
4960 | - && entry->root.hash == hash | |
4961 | - && strcmp (name, entry->s.output_section_statement.name) == 0); | |
4962 | + if (create && constraint == SPECIAL) | |
4963 | + /* Not traversing to the end reverses the order of the second | |
4964 | + and subsequent SPECIAL sections in the hash table chain, | |
4965 | + but that shouldn't matter. */ | |
4966 | + last_ent = entry; | |
4967 | + else | |
4968 | + do | |
4969 | + { | |
4970 | + if (entry->s.output_section_statement.constraint >= 0 | |
4971 | + && (constraint == 0 | |
4972 | + || (constraint | |
4973 | + == entry->s.output_section_statement.constraint))) | |
4974 | + return &entry->s.output_section_statement; | |
4975 | + last_ent = entry; | |
4976 | + entry = (struct out_section_hash_entry *) entry->root.next; | |
4977 | + } | |
4978 | + while (entry != NULL | |
4979 | + && entry->root.hash == hash | |
4980 | + && strcmp (name, entry->s.output_section_statement.name) == 0); | |
4981 | ||
4982 | if (!create) | |
4983 | return NULL; | |
4984 | @@ -1556,28 +1581,24 @@ | |
4985 | lang_output_section_statement_type * | |
4986 | lang_insert_orphan (asection *s, | |
4987 | const char *secname, | |
4988 | + int constraint, | |
4989 | lang_output_section_statement_type *after, | |
4990 | struct orphan_save *place, | |
4991 | etree_type *address, | |
4992 | lang_statement_list_type *add_child) | |
4993 | { | |
4994 | - lang_statement_list_type *old; | |
4995 | lang_statement_list_type add; | |
4996 | const char *ps; | |
4997 | lang_output_section_statement_type *os; | |
4998 | lang_output_section_statement_type **os_tail; | |
4999 | ||
5000 | - /* Start building a list of statements for this section. | |
5001 | - First save the current statement pointer. */ | |
5002 | - old = stat_ptr; | |
5003 | - | |
5004 | /* If we have found an appropriate place for the output section | |
5005 | statements for this orphan, add them to our own private list, | |
5006 | inserting them later into the global statement list. */ | |
5007 | if (after != NULL) | |
5008 | { | |
5009 | - stat_ptr = &add; | |
5010 | - lang_list_init (stat_ptr); | |
5011 | + lang_list_init (&add); | |
5012 | + push_stat_ptr (&add); | |
5013 | } | |
5014 | ||
5015 | ps = NULL; | |
5016 | @@ -1611,7 +1632,7 @@ | |
5017 | os_tail = ((lang_output_section_statement_type **) | |
5018 | lang_output_section_statement.tail); | |
5019 | os = lang_enter_output_section_statement (secname, address, 0, NULL, NULL, | |
5020 | - NULL, 0); | |
5021 | + NULL, constraint); | |
5022 | ||
5023 | if (add_child == NULL) | |
5024 | add_child = &os->children; | |
5025 | @@ -1623,11 +1644,6 @@ | |
5026 | { | |
5027 | char *symname; | |
5028 | ||
5029 | - /* lang_leave_ouput_section_statement resets stat_ptr. | |
5030 | - Put stat_ptr back where we want it. */ | |
5031 | - if (after != NULL) | |
5032 | - stat_ptr = &add; | |
5033 | - | |
5034 | symname = (char *) xmalloc (ps - secname + sizeof "__stop_" + 1); | |
5035 | symname[0] = bfd_get_symbol_leading_char (link_info.output_bfd); | |
5036 | sprintf (symname + (symname[0] != 0), "__stop_%s", secname); | |
5037 | @@ -1638,7 +1654,7 @@ | |
5038 | ||
5039 | /* Restore the global list pointer. */ | |
5040 | if (after != NULL) | |
5041 | - stat_ptr = old; | |
5042 | + pop_stat_ptr (); | |
5043 | ||
5044 | if (after != NULL && os->bfd_section != NULL) | |
5045 | { | |
5046 | @@ -1724,8 +1740,8 @@ | |
5047 | ||
5048 | /* Fix the global list pointer if we happened to tack our | |
5049 | new list at the tail. */ | |
5050 | - if (*old->tail == add.head) | |
5051 | - old->tail = add.tail; | |
5052 | + if (*stat_ptr->tail == add.head) | |
5053 | + stat_ptr->tail = add.tail; | |
5054 | ||
5055 | /* Save the end of this list. */ | |
5056 | place->stmt = add.tail; | |
5057 | @@ -1914,10 +1930,11 @@ | |
5058 | if (strcmp (s->name, DISCARD_SECTION_NAME) == 0) | |
5059 | einfo (_("%P%F: Illegal use of `%s' section\n"), DISCARD_SECTION_NAME); | |
5060 | ||
5061 | - s->bfd_section = bfd_get_section_by_name (link_info.output_bfd, s->name); | |
5062 | + if (s->constraint != SPECIAL) | |
5063 | + s->bfd_section = bfd_get_section_by_name (link_info.output_bfd, s->name); | |
5064 | if (s->bfd_section == NULL) | |
5065 | - s->bfd_section = bfd_make_section_with_flags (link_info.output_bfd, | |
5066 | - s->name, flags); | |
5067 | + s->bfd_section = bfd_make_section_anyway_with_flags (link_info.output_bfd, | |
5068 | + s->name, flags); | |
5069 | if (s->bfd_section == NULL) | |
5070 | { | |
5071 | einfo (_("%P%F: output format %s cannot represent section called %s\n"), | |
5072 | @@ -2455,8 +2472,6 @@ | |
5073 | && ! bfd_check_format_matches (entry->the_bfd, bfd_object, &matching)) | |
5074 | { | |
5075 | bfd_error_type err; | |
5076 | - lang_statement_list_type *hold; | |
5077 | - bfd_boolean bad_load = TRUE; | |
5078 | bfd_boolean save_ldlang_sysrooted_script; | |
5079 | bfd_boolean save_as_needed, save_add_needed; | |
5080 | ||
5081 | @@ -2479,8 +2494,6 @@ | |
5082 | else if (err != bfd_error_file_not_recognized | |
5083 | || place == NULL) | |
5084 | einfo (_("%F%B: file not recognized: %E\n"), entry->the_bfd); | |
5085 | - else | |
5086 | - bad_load = FALSE; | |
5087 | ||
5088 | bfd_close (entry->the_bfd); | |
5089 | entry->the_bfd = NULL; | |
5090 | @@ -2488,8 +2501,7 @@ | |
5091 | /* Try to interpret the file as a linker script. */ | |
5092 | ldfile_open_command_file (entry->filename); | |
5093 | ||
5094 | - hold = stat_ptr; | |
5095 | - stat_ptr = place; | |
5096 | + push_stat_ptr (place); | |
5097 | save_ldlang_sysrooted_script = ldlang_sysrooted_script; | |
5098 | ldlang_sysrooted_script = entry->sysrooted; | |
5099 | save_as_needed = as_needed; | |
5100 | @@ -2508,9 +2520,9 @@ | |
5101 | ldlang_sysrooted_script = save_ldlang_sysrooted_script; | |
5102 | as_needed = save_as_needed; | |
5103 | add_needed = save_add_needed; | |
5104 | - stat_ptr = hold; | |
5105 | + pop_stat_ptr (); | |
5106 | ||
5107 | - return ! bad_load; | |
5108 | + return TRUE; | |
5109 | } | |
5110 | ||
5111 | if (ldemul_recognized_file (entry)) | |
5112 | @@ -2982,6 +2994,7 @@ | |
5113 | case lang_input_statement_enum: | |
5114 | if (s->input_statement.real) | |
5115 | { | |
5116 | + lang_statement_union_type **os_tail; | |
5117 | lang_statement_list_type add; | |
5118 | ||
5119 | s->input_statement.target = current_target; | |
5120 | @@ -2997,6 +3010,7 @@ | |
5121 | bfd_archive)) | |
5122 | s->input_statement.loaded = FALSE; | |
5123 | ||
5124 | + os_tail = lang_output_section_statement.tail; | |
5125 | lang_list_init (&add); | |
5126 | ||
5127 | if (! load_symbols (&s->input_statement, &add)) | |
5128 | @@ -3004,8 +3018,25 @@ | |
5129 | ||
5130 | if (add.head != NULL) | |
5131 | { | |
5132 | - *add.tail = s->header.next; | |
5133 | - s->header.next = add.head; | |
5134 | + /* If this was a script with output sections then | |
5135 | + tack any added statements on to the end of the | |
5136 | + list. This avoids having to reorder the output | |
5137 | + section statement list. Very likely the user | |
5138 | + forgot -T, and whatever we do here will not meet | |
5139 | + naive user expectations. */ | |
5140 | + if (os_tail != lang_output_section_statement.tail) | |
5141 | + { | |
5142 | + einfo (_("%P: warning: %s contains output sections;" | |
5143 | + " did you forget -T?\n"), | |
5144 | + s->input_statement.filename); | |
5145 | + *stat_ptr->tail = add.head; | |
5146 | + stat_ptr->tail = add.tail; | |
5147 | + } | |
5148 | + else | |
5149 | + { | |
5150 | + *add.tail = s->header.next; | |
5151 | + s->header.next = add.head; | |
5152 | + } | |
5153 | } | |
5154 | } | |
5155 | break; | |
5156 | @@ -5652,14 +5683,22 @@ | |
5157 | default_common_section); | |
5158 | } | |
5159 | } | |
5160 | - else if (ldemul_place_orphan (s)) | |
5161 | - ; | |
5162 | else | |
5163 | { | |
5164 | - lang_output_section_statement_type *os; | |
5165 | + const char *name = s->name; | |
5166 | + int constraint = 0; | |
5167 | ||
5168 | - os = lang_output_section_statement_lookup (s->name, 0, TRUE); | |
5169 | - lang_add_section (&os->children, s, os); | |
5170 | + if (config.unique_orphan_sections || unique_section_p (s)) | |
5171 | + constraint = SPECIAL; | |
5172 | + | |
5173 | + if (!ldemul_place_orphan (s, name, constraint)) | |
5174 | + { | |
5175 | + lang_output_section_statement_type *os; | |
5176 | + os = lang_output_section_statement_lookup (name, | |
5177 | + constraint, | |
5178 | + TRUE); | |
5179 | + lang_add_section (&os->children, s, os); | |
5180 | + } | |
5181 | } | |
5182 | } | |
5183 | } | |
5184 | @@ -5821,7 +5860,7 @@ | |
5185 | os->block_value = 1; | |
5186 | ||
5187 | /* Make next things chain into subchain of this. */ | |
5188 | - stat_ptr = &os->children; | |
5189 | + push_stat_ptr (&os->children); | |
5190 | ||
5191 | os->subsection_alignment = | |
5192 | topower (exp_get_value_int (subalign, -1, "subsection alignment")); | |
5193 | @@ -6430,7 +6469,7 @@ | |
5194 | current_section->addr_tree != NULL); | |
5195 | current_section->fill = fill; | |
5196 | current_section->phdrs = phdrs; | |
5197 | - stat_ptr = &statement_list; | |
5198 | + pop_stat_ptr (); | |
5199 | } | |
5200 | ||
5201 | /* Create an absolute symbol with the given name with the value of the | |
5202 | @@ -6547,7 +6586,7 @@ | |
5203 | ||
5204 | g = new_stat (lang_group_statement, stat_ptr); | |
5205 | lang_list_init (&g->children); | |
5206 | - stat_ptr = &g->children; | |
5207 | + push_stat_ptr (&g->children); | |
5208 | } | |
5209 | ||
5210 | /* Leave a group. This just resets stat_ptr to start writing to the | |
5211 | @@ -6558,7 +6597,7 @@ | |
5212 | void | |
5213 | lang_leave_group (void) | |
5214 | { | |
5215 | - stat_ptr = &statement_list; | |
5216 | + pop_stat_ptr (); | |
5217 | } | |
5218 | ||
5219 | /* Add a new program header. This is called for each entry in a PHDRS | |
5220 | diff -Naur binutils-2.19.1.orig/ld/ldlang.h binutils-2.19.1/ld/ldlang.h | |
5221 | --- binutils-2.19.1.orig/ld/ldlang.h 2008-09-06 21:02:30.000000000 -0700 | |
5222 | +++ binutils-2.19.1/ld/ldlang.h 2009-03-02 05:56:19.000000000 -0800 | |
5223 | @@ -1,6 +1,6 @@ | |
5224 | /* ldlang.h - linker command language support | |
5225 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, | |
5226 | - 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 | |
5227 | + 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 | |
5228 | Free Software Foundation, Inc. | |
5229 | ||
5230 | This file is part of the GNU Binutils. | |
5231 | @@ -536,7 +536,7 @@ | |
5232 | (const asection *, lang_output_section_statement_type **, | |
5233 | lang_match_sec_type_func); | |
5234 | extern lang_output_section_statement_type *lang_insert_orphan | |
5235 | - (asection *, const char *, lang_output_section_statement_type *, | |
5236 | + (asection *, const char *, int, lang_output_section_statement_type *, | |
5237 | struct orphan_save *, etree_type *, lang_statement_list_type *); | |
5238 | extern lang_input_statement_type *lang_add_input_file | |
5239 | (const char *, lang_input_file_enum_type, const char *); | |
5240 | @@ -550,6 +550,10 @@ | |
5241 | (const char *, const char *, const char *, int); | |
5242 | extern void lang_list_init | |
5243 | (lang_statement_list_type *); | |
5244 | +extern void push_stat_ptr | |
5245 | + (lang_statement_list_type *); | |
5246 | +extern void pop_stat_ptr | |
5247 | + (void); | |
5248 | extern void lang_add_data | |
5249 | (int type, union etree_union *); | |
5250 | extern void lang_add_reloc | |
5251 | @@ -604,8 +608,6 @@ | |
5252 | extern void lang_append_dynamic_list (struct bfd_elf_version_expr *); | |
5253 | extern void lang_append_dynamic_list_cpp_typeinfo (void); | |
5254 | extern void lang_append_dynamic_list_cpp_new (void); | |
5255 | -bfd_boolean unique_section_p | |
5256 | - (const asection *); | |
5257 | extern void lang_add_unique | |
5258 | (const char *); | |
5259 | extern const char *lang_get_output_target | |
5260 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ChangeLog binutils-2.19.1/ld/testsuite/ChangeLog | |
5261 | --- binutils-2.19.1.orig/ld/testsuite/ChangeLog 2009-01-14 01:04:14.000000000 -0800 | |
5262 | +++ binutils-2.19.1/ld/testsuite/ChangeLog 2009-03-02 05:53:31.000000000 -0800 | |
5263 | @@ -1,3 +1,26 @@ | |
5264 | +2009-03-02 Alan Modra <amodra@bigpond.net.au> | |
5265 | + | |
5266 | + 2009-02-01 Jan Kratochvil <jan.kratochvil@redhat.com> | |
5267 | + * ld-elf/eh-group2.s: New `.cfi_lsda' referencing `.gcc_except_table'. | |
5268 | + * ld-elf/eh-group.exp: New test and conditional defininiton of `ELF64'. | |
5269 | + | |
5270 | + 2009-01-26 Nathan Sidwell <nathan@codesourcery.com> | |
5271 | + * ld-powerpc/powerpc.exp: Add vxworks relax testcase. | |
5272 | + * ld-powerpc/vxworks-relax.s, ld-powerpc/vxworks-relax.rd: New. | |
5273 | + * ld-powerpc/vxworks1.ld: Add .pad and .far input sections. | |
5274 | + * ld-powerpc/vxworks1.rd: Correct regexp for undefined symbols. | |
5275 | + | |
5276 | + 2009-01-11 Jan Kratochvil <jan.kratochvil@redhat.com> | |
5277 | + * ld-elf/linkoncerdiff.d, ld-elf/linkoncerdiff1.s, | |
5278 | + ld-elf/linkoncerdiff2.s: New. | |
5279 | + | |
5280 | + 2008-10-10 Nathan Froyd <froydnj@codesourcery.com> | |
5281 | + * ld-powerpc/attr-gnu-12-1.s: New file. | |
5282 | + * ld-powerpc/attr-gnu-12-2.s: New file. | |
5283 | + * ld-powerpc/attr-gnu-12-11.d: New file. | |
5284 | + * ld-powerpc/attr-gnu-12-21.d: New file. | |
5285 | + * ld-powerpc/powerpc.exp: Run new dump tests. | |
5286 | + | |
5287 | 2009-01-14 Joseph Myers <joseph@codesourcery.com> | |
5288 | ||
5289 | * ld-arm/thumb2-bl-undefweak.d, ld-arm/thumb2-bl-undefweak.s: New. | |
5290 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/eh-group2.s binutils-2.19.1/ld/testsuite/ld-elf/eh-group2.s | |
5291 | --- binutils-2.19.1.orig/ld/testsuite/ld-elf/eh-group2.s 2008-10-02 03:10:26.000000000 -0700 | |
5292 | +++ binutils-2.19.1/ld/testsuite/ld-elf/eh-group2.s 2009-03-02 05:53:31.000000000 -0800 | |
5293 | @@ -1,4 +1,15 @@ | |
5294 | .section sect, "axG", %progbits, sectgroup, comdat | |
5295 | .cfi_startproc | |
5296 | +# Test intention is that LSDA must be provided by the discarded FDE. | |
5297 | +# DW_EH_PE_udata8 = 4 | |
5298 | +# DW_EH_PE_udata4 = 3 | |
5299 | + .ifdef ELF64 | |
5300 | + .cfi_lsda 4, lsda | |
5301 | + .else | |
5302 | + .cfi_lsda 3, lsda | |
5303 | + .endif | |
5304 | .skip 16 | |
5305 | .cfi_endproc | |
5306 | + | |
5307 | + .section .gcc_except_table, "a", %progbits | |
5308 | +lsda: | |
5309 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/eh-group.exp binutils-2.19.1/ld/testsuite/ld-elf/eh-group.exp | |
5310 | --- binutils-2.19.1.orig/ld/testsuite/ld-elf/eh-group.exp 2008-10-02 03:10:26.000000000 -0700 | |
5311 | +++ binutils-2.19.1/ld/testsuite/ld-elf/eh-group.exp 2009-03-02 05:53:31.000000000 -0800 | |
5312 | @@ -35,12 +35,28 @@ | |
5313 | return | |
5314 | } | |
5315 | ||
5316 | -set build_tests_ld { | |
5317 | - {"Build eh-group1.o" | |
5318 | - "-r" "" | |
5319 | - {eh-group1.s eh-group2.s} {} "eh-group.o"} | |
5320 | +# alpha-linux-gnu does not support 64-bit relocations: | |
5321 | +# relocation truncated to fit: REFLONG against `.gcc_except_table' | |
5322 | +# arm-eabi does not support 64-bit relocations: | |
5323 | +# bad relocation fixup type (1) | |
5324 | +set testname "Guess the target size from eh-group1size.o" | |
5325 | +if [ld_assemble $as "$srcdir/$subdir/eh-group1.s" "tmpdir/eh-group1size.o"] { | |
5326 | + pass $testname | |
5327 | +} else { | |
5328 | + fail $testname | |
5329 | } | |
5330 | ||
5331 | +set as_options "" | |
5332 | +if [is_elf64 "tmpdir/eh-group1size.o"] { | |
5333 | + set as_options "$as_options --defsym ELF64=1" | |
5334 | +} | |
5335 | + | |
5336 | +set build_tests_ld [list \ | |
5337 | + [list "Build eh-group1.o" \ | |
5338 | + "-r" "$as_options" \ | |
5339 | + {eh-group1.s eh-group2.s} {} "eh-group.o"] \ | |
5340 | +] | |
5341 | + | |
5342 | run_ld_link_tests $build_tests_ld | |
5343 | ||
5344 | set testname "Link eh-group.o to eh-group" | |
5345 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff1.s binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff1.s | |
5346 | --- binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff1.s 1969-12-31 16:00:00.000000000 -0800 | |
5347 | +++ binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff1.s 2009-03-02 05:48:42.000000000 -0800 | |
5348 | @@ -0,0 +1,7 @@ | |
5349 | + .section .gnu.linkonce.t.foo, "a", %progbits | |
5350 | + .globl symfoo | |
5351 | +symfoo: | |
5352 | + | |
5353 | + .section .gnu.linkonce.t.bar, "a", %progbits | |
5354 | + .globl symbar | |
5355 | +symbar: | |
5356 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff2.s binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff2.s | |
5357 | --- binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff2.s 1969-12-31 16:00:00.000000000 -0800 | |
5358 | +++ binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff2.s 2009-03-02 05:48:42.000000000 -0800 | |
5359 | @@ -0,0 +1,22 @@ | |
5360 | + .section .gnu.linkonce.t.foo, "a", %progbits | |
5361 | +1: | |
5362 | + .globl symfoo | |
5363 | +symfoo: | |
5364 | + .long 0 | |
5365 | + | |
5366 | + .section .gnu.linkonce.t.bar, "a", %progbits | |
5367 | +2: | |
5368 | + .globl symbar | |
5369 | +symbar: | |
5370 | + .long 0 | |
5371 | + | |
5372 | + .section .gnu.linkonce.r.foo, "a", %progbits | |
5373 | + .long 1b | |
5374 | + .long symfoo | |
5375 | +/* ld currently incorrectly silently discards this relocation. Just such | |
5376 | + relocations are never produced by g++-3.4 so this suppressed error message | |
5377 | + is not a problem: | |
5378 | + #error: `.gnu.linkonce.t.bar' referenced in section `.gnu.linkonce.r.foo' of tmpdir/dump1.o: defined in discarded section `.gnu.linkonce.t.bar' of tmpdir/dump1.o | |
5379 | + */ | |
5380 | + .long 2b | |
5381 | + .long symbar | |
5382 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff.d binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff.d | |
5383 | --- binutils-2.19.1.orig/ld/testsuite/ld-elf/linkoncerdiff.d 1969-12-31 16:00:00.000000000 -0800 | |
5384 | +++ binutils-2.19.1/ld/testsuite/ld-elf/linkoncerdiff.d 2009-03-02 05:48:42.000000000 -0800 | |
5385 | @@ -0,0 +1,6 @@ | |
5386 | +#source: linkoncerdiff1.s | |
5387 | +#source: linkoncerdiff2.s | |
5388 | +#ld: -r | |
5389 | +#readelf: -r | |
5390 | +There are no relocations in this file. | |
5391 | +#pass | |
5392 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-11.d binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-11.d | |
5393 | --- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-11.d 1969-12-31 16:00:00.000000000 -0800 | |
5394 | +++ binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-11.d 2009-03-02 05:37:44.000000000 -0800 | |
5395 | @@ -0,0 +1,10 @@ | |
5396 | +#source: attr-gnu-12-1.s | |
5397 | +#source: attr-gnu-12-1.s | |
5398 | +#as: -a32 | |
5399 | +#ld: -r -melf32ppc | |
5400 | +#readelf: -A | |
5401 | +#target: powerpc*-*-* | |
5402 | + | |
5403 | +Attribute Section: gnu | |
5404 | +File Attributes | |
5405 | + Tag_GNU_Power_ABI_Struct_Return: r3/r4 | |
5406 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-1.s binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-1.s | |
5407 | --- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-1.s 1969-12-31 16:00:00.000000000 -0800 | |
5408 | +++ binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-1.s 2009-03-02 05:37:44.000000000 -0800 | |
5409 | @@ -0,0 +1 @@ | |
5410 | +.gnu_attribute 12,1 | |
5411 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-21.d binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-21.d | |
5412 | --- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-21.d 1969-12-31 16:00:00.000000000 -0800 | |
5413 | +++ binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-21.d 2009-03-02 05:37:44.000000000 -0800 | |
5414 | @@ -0,0 +1,6 @@ | |
5415 | +#source: attr-gnu-12-2.s | |
5416 | +#source: attr-gnu-12-1.s | |
5417 | +#as: -a32 | |
5418 | +#ld: -r -melf32ppc | |
5419 | +#warning: Warning: .* uses r3/r4 for small structure returns, .* uses memory | |
5420 | +#target: powerpc*-*-* | |
5421 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-2.s binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-2.s | |
5422 | --- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/attr-gnu-12-2.s 1969-12-31 16:00:00.000000000 -0800 | |
5423 | +++ binutils-2.19.1/ld/testsuite/ld-powerpc/attr-gnu-12-2.s 2009-03-02 05:37:44.000000000 -0800 | |
5424 | @@ -0,0 +1 @@ | |
5425 | +.gnu_attribute 12,2 | |
5426 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/powerpc.exp binutils-2.19.1/ld/testsuite/ld-powerpc/powerpc.exp | |
5427 | --- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/powerpc.exp 2008-07-26 06:10:48.000000000 -0700 | |
5428 | +++ binutils-2.19.1/ld/testsuite/ld-powerpc/powerpc.exp 2009-03-02 05:52:34.000000000 -0800 | |
5429 | @@ -49,6 +49,11 @@ | |
5430 | "-mregnames" {vxworks2.s} | |
5431 | {{readelf --segments vxworks2-static.sd}} | |
5432 | "vxworks2"} | |
5433 | + {"VxWorks relax test" | |
5434 | + "-Tvxworks1.ld --relax -q" | |
5435 | + "-mregnames" {vxworks-relax.s} | |
5436 | + {{readelf --relocs vxworks-relax.rd}} | |
5437 | + "vxworks-relax"} | |
5438 | } | |
5439 | run_ld_link_tests $ppcvxtests | |
5440 | run_dump_test "vxworks1-static" | |
5441 | @@ -177,3 +182,6 @@ | |
5442 | run_dump_test "attr-gnu-8-11" | |
5443 | run_dump_test "attr-gnu-8-23" | |
5444 | run_dump_test "attr-gnu-8-31" | |
5445 | + | |
5446 | +run_dump_test "attr-gnu-12-11" | |
5447 | +run_dump_test "attr-gnu-12-21" | |
5448 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks1.ld binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks1.ld | |
5449 | --- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks1.ld 2007-05-15 05:22:34.000000000 -0700 | |
5450 | +++ binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks1.ld 2009-03-02 05:52:34.000000000 -0800 | |
5451 | @@ -14,7 +14,7 @@ | |
5452 | .plt : { *(.plt) } | |
5453 | ||
5454 | . = ALIGN (0x400); | |
5455 | - .text : { *(.text) } | |
5456 | + .text : { *(.text) *(.pad) *(.far) } | |
5457 | ||
5458 | . = ALIGN (0x10000); | |
5459 | .dynamic : { *(.dynamic) } | |
5460 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks1.rd binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks1.rd | |
5461 | --- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks1.rd 2006-03-02 07:16:27.000000000 -0800 | |
5462 | +++ binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks1.rd 2009-03-02 05:52:34.000000000 -0800 | |
5463 | @@ -1,8 +1,8 @@ | |
5464 | ||
5465 | Relocation section '\.rela\.plt' at offset .* contains 2 entries: | |
5466 | Offset Info Type Sym\.Value Sym\. Name \+ Addend | |
5467 | -0009040c .*15 R_PPC_JMP_SLOT 00080820 sglobal \+ 0 | |
5468 | -00090410 .*15 R_PPC_JMP_SLOT 00080840 foo \+ 0 | |
5469 | +0009040c .*15 R_PPC_JMP_SLOT 00000000 sglobal \+ 0 | |
5470 | +00090410 .*15 R_PPC_JMP_SLOT 00000000 foo \+ 0 | |
5471 | ||
5472 | Relocation section '\.rela\.text' at offset .* contains 3 entries: | |
5473 | Offset Info Type Sym\.Value Sym\. Name \+ Addend | |
5474 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks-relax.rd binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks-relax.rd | |
5475 | --- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks-relax.rd 1969-12-31 16:00:00.000000000 -0800 | |
5476 | +++ binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks-relax.rd 2009-03-02 05:52:34.000000000 -0800 | |
5477 | @@ -0,0 +1,9 @@ | |
5478 | + | |
5479 | +Relocation section '.rela.text' at offset 0x4010150 contains 6 entries: | |
5480 | + Offset Info Type Sym.Value Sym. Name \+ Addend | |
5481 | +00080012 00000106 R_PPC_ADDR16_HA 00080000 .text \+ 4000020 | |
5482 | +00080016 00000104 R_PPC_ADDR16_LO 00080000 .text \+ 4000020 | |
5483 | +00080006 00000106 R_PPC_ADDR16_HA 00080000 .text \+ 4000020 | |
5484 | +0008000a 00000104 R_PPC_ADDR16_LO 00080000 .text \+ 4000020 | |
5485 | +0408002a 00000306 R_PPC_ADDR16_HA 00080000 _start \+ 0 | |
5486 | +0408002e 00000304 R_PPC_ADDR16_LO 00080000 _start \+ 0 | |
5487 | diff -Naur binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks-relax.s binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks-relax.s | |
5488 | --- binutils-2.19.1.orig/ld/testsuite/ld-powerpc/vxworks-relax.s 1969-12-31 16:00:00.000000000 -0800 | |
5489 | +++ binutils-2.19.1/ld/testsuite/ld-powerpc/vxworks-relax.s 2009-03-02 05:52:34.000000000 -0800 | |
5490 | @@ -0,0 +1,13 @@ | |
5491 | + .globl _start | |
5492 | +_start: | |
5493 | + bl elsewhere | |
5494 | + lis 9,elsewhere@ha | |
5495 | + la 0,elsewhere@l(9) | |
5496 | + | |
5497 | + | |
5498 | + .section .far,"ax",@progbits | |
5499 | +elsewhere: | |
5500 | + bl _start | |
5501 | + | |
5502 | + .section .pad | |
5503 | + .space 0x4000000 | |
5504 | diff -Naur binutils-2.19.1.orig/opcodes/ChangeLog binutils-2.19.1/opcodes/ChangeLog | |
5505 | --- binutils-2.19.1.orig/opcodes/ChangeLog 2008-12-23 05:54:52.000000000 -0800 | |
5506 | +++ binutils-2.19.1/opcodes/ChangeLog 2009-03-03 17:08:22.000000000 -0800 | |
5507 | @@ -1,3 +1,93 @@ | |
5508 | +2009-03-03 Peter Bergner <bergner@vnet.ibm.com> | |
5509 | + | |
5510 | + * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that | |
5511 | + instructions from newer processors are listed before older ones. | |
5512 | + | |
5513 | +2009-03-02 Alan Modra <amodra@bigpond.net.au> | |
5514 | + | |
5515 | + 2009-02-26 Peter Bergner <bergner@vnet.ibm.com> | |
5516 | + * ppc-dis.c (powerpc_init_dialect): Extend -Mpower7 to disassemble | |
5517 | + the power7 and the isel instructions. | |
5518 | + * ppc-opc.c (insert_xc6, extract_xc6): New static functions. | |
5519 | + (insert_dm, extract_dm): Likewise. | |
5520 | + (XB6): Update comment to include XX2 form. | |
5521 | + (WC, XC6, SHW, DMEX, UIM, XX2, XX3RC, XX4, XX2_MASK, XX2UIM_MASK, | |
5522 | + XX2BF_MASK, XX3BF_MASK, XX3SHW_MASK, XX4_MASK, XWC_MASK, POWER7): New. | |
5523 | + (RemoveXX3DM): Delete. | |
5524 | + (powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr", | |
5525 | + "mftgpr">: Deprecate for POWER7. | |
5526 | + <"fres", "fres.", "frsqrtes", "frsqrtes.", "fre", "fre.", "frsqrte", | |
5527 | + "frsqrte.">: Deprecate the three operand form and enable the two | |
5528 | + operand form for POWER7 and later. | |
5529 | + <"wait">: Extend to accept optional parameter. Enable for POWER7. | |
5530 | + <"waitsrv", "waitimpl">: Add extended opcodes. | |
5531 | + <"ldbrx", "stdbrx">: Enable for POWER7. | |
5532 | + <"cdtbcd", "cbcdtd", "addg6s">: Add POWER6 opcodes. | |
5533 | + <"bpermd", "dcbtstt", "dcbtt", "dcffix.", "dcffix", "divde.", "divde", | |
5534 | + "divdeo.", "divdeo", "divdeu.", "divdeu", "divdeuo.", "divdeuo", | |
5535 | + "divwe.", "divwe", "divweo.", "divweo", "divweu.", "divweu", "divweuo.", | |
5536 | + "divweuo", "fcfids.", "fcfids", "fcfidu.", "fcfidu", "fcfidus.", | |
5537 | + "fcfidus", "fctidu.", "fctidu", "fctiduz.", "fctiduz", "fctiwu.", | |
5538 | + "fctiwu", "fctiwuz.", "fctiwuz", "ftdiv", "ftsqrt", "lbarx", "lfiwzx", | |
5539 | + "lharx", "popcntd", "popcntw", "stbcx.", "sthcx.">: Add POWER7 opcodes. | |
5540 | + <"lxsdux", "lxsdx", "lxvdsx", "lxvw4ux", "lxvw4x", "stxsdux", "stxsdx", | |
5541 | + "stxvw4ux", "stxvw4x", "xsabsdp", "xsadddp", "xscmpodp", "xscmpudp", | |
5542 | + "xscpsgndp", "xscvdpsp", "xscvdpsxds", "xscvdpsxws", "xscvdpuxds", | |
5543 | + "xscvdpuxws", "xscvspdp", "xscvsxddp", "xscvuxddp", "xsdivdp", | |
5544 | + "xsmaddadp", "xsmaddmdp", "xsmaxdp", "xsmindp", "xsmsubadp", | |
5545 | + "xsmsubmdp", "xsmuldp", "xsnabsdp", "xsnegdp", "xsnmaddadp", | |
5546 | + "xsnmaddmdp", "xsnmsubadp", "xsnmsubmdp", "xsrdpi", "xsrdpic", | |
5547 | + "xsrdpim", "xsrdpip", "xsrdpiz", "xsredp", "xsrsqrtedp", "xssqrtdp", | |
5548 | + "xssubdp", "xstdivdp", "xstsqrtdp", "xvabsdp", "xvabssp", "xvadddp", | |
5549 | + "xvaddsp", "xvcmpeqdp.", "xvcmpeqdp", "xvcmpeqsp.", "xvcmpeqsp", | |
5550 | + "xvcmpgedp.", "xvcmpgedp", "xvcmpgesp.", "xvcmpgesp", "xvcmpgtdp.", | |
5551 | + "xvcmpgtdp", "xvcmpgtsp.", "xvcmpgtsp", "xvcpsgnsp", "xvcvdpsp", | |
5552 | + "xvcvdpsxds", "xvcvdpsxws", "xvcvdpuxds", "xvcvdpuxws", "xvcvspdp", | |
5553 | + "xvcvspsxds", "xvcvspsxws", "xvcvspuxds", "xvcvspuxws", "xvcvsxddp", | |
5554 | + "xvcvsxdsp", "xvcvsxwdp", "xvcvsxwsp", "xvcvuxddp", "xvcvuxdsp", | |
5555 | + "xvcvuxwdp", "xvcvuxwsp", "xvdivdp", "xvdivsp", "xvmaddadp", | |
5556 | + "xvmaddasp", "xvmaddmdp", "xvmaddmsp", "xvmaxdp", "xvmaxsp", | |
5557 | + "xvmindp", "xvminsp", "xvmovsp", "xvmsubadp", "xvmsubasp", "xvmsubmdp", | |
5558 | + "xvmsubmsp", "xvmuldp", "xvmulsp", "xvnabsdp", "xvnabssp", "xvnegdp", | |
5559 | + "xvnegsp", "xvnmaddadp", "xvnmaddasp", "xvnmaddmdp", "xvnmaddmsp", | |
5560 | + "xvnmsubadp", "xvnmsubasp", "xvnmsubmdp", "xvnmsubmsp", "xvrdpi", | |
5561 | + "xvrdpic", "xvrdpim", "xvrdpip", "xvrdpiz", "xvredp", "xvresp", | |
5562 | + "xvrspi", "xvrspic", "xvrspim", "xvrspip", "xvrspiz", "xvrsqrtedp", | |
5563 | + "xvrsqrtesp", "xvsqrtdp", "xvsqrtsp", "xvsubdp", "xvsubsp", "xvtdivdp", | |
5564 | + "xvtdivsp", "xvtsqrtdp", "xvtsqrtsp", "xxland", "xxlandc", "xxlnor", | |
5565 | + "xxlor", "xxlxor", "xxmrghw", "xxmrglw", "xxsel", "xxsldwi", "xxspltd", | |
5566 | + "xxspltw", "xxswapd">: Add VSX opcodes. | |
5567 | + | |
5568 | + 2009-02-19 Peter Bergner <bergner@vnet.ibm.com> | |
5569 | + * ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first | |
5570 | + operand to be a float point register (FRT/FRS). | |
5571 | + | |
5572 | + 2009-02-05 Peter Bergner <bergner@vnet.ibm.com> | |
5573 | + * ppc-opc.c: Update copyright year. | |
5574 | + (powerpc_opcodes) <"dcbt", "dcbtst">: Deprecate the Embedded operand | |
5575 | + ordering for POWER4 and later and use the correct Server ordering. | |
5576 | + | |
5577 | + 2009-01-14 Peter Bergner <bergner@vnet.ibm.com> | |
5578 | + * ppc-dis.c (print_insn_powerpc): Skip insn if it is deprecated. | |
5579 | + * ppc-opc.c (powerpc_opcodes) <mtfsf, mtfsf.>: Deprecate the two | |
5580 | + operand form and enable the four operand form for POWER6 and later. | |
5581 | + <mtfsfi, mtfsfi.>: Deprecate the two operand form and enable the | |
5582 | + three operand form for POWER6 and later. | |
5583 | + | |
5584 | + 2009-01-09 Peter Bergner <bergner@vnet.ibm.com> | |
5585 | + * ppc-opc.c (PPCNONE): Define. | |
5586 | + (NOPOWER4): Delete. | |
5587 | + (powerpc_opcodes): Initialize the new "deprecated" field. | |
5588 | + | |
5589 | + 2008-12-04 Ben Elliston <bje@au.ibm.com> | |
5590 | + * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE | |
5591 | + for -Mbooke. | |
5592 | + (print_ppc_disassembler_options): Update usage. | |
5593 | + * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove. | |
5594 | + (BOOKE64): Remove. | |
5595 | + (PPCCHLK64): Likewise. | |
5596 | + (powerpc_opcodes): Remove all BOOKE64 instructions. | |
5597 | + | |
5598 | 2008-11-27 Alan Modra <amodra@bigpond.net.au> | |
5599 | ||
5600 | * ppc-opc.c (extract_sprg): Correct operand range check. | |
5601 | diff -Naur binutils-2.19.1.orig/opcodes/ppc-dis.c binutils-2.19.1/opcodes/ppc-dis.c | |
5602 | --- binutils-2.19.1.orig/opcodes/ppc-dis.c 2008-08-01 21:38:51.000000000 -0700 | |
5603 | +++ binutils-2.19.1/opcodes/ppc-dis.c 2009-03-02 05:59:36.000000000 -0800 | |
5604 | @@ -63,7 +63,7 @@ | |
5605 | dialect |= PPC_OPCODE_PPCPS; | |
5606 | else if (info->disassembler_options | |
5607 | && strstr (info->disassembler_options, "booke") != NULL) | |
5608 | - dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; | |
5609 | + dialect |= PPC_OPCODE_BOOKE; | |
5610 | else if ((info->mach == bfd_mach_ppc_e500mc) | |
5611 | || (info->disassembler_options | |
5612 | && strstr (info->disassembler_options, "e500mc") != NULL)) | |
5613 | @@ -112,8 +112,9 @@ | |
5614 | ||
5615 | if (info->disassembler_options | |
5616 | && strstr (info->disassembler_options, "power7") != NULL) | |
5617 | - dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | |
5618 | - | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX; | |
5619 | + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | |
5620 | + | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | |
5621 | + | PPC_OPCODE_ISEL | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX; | |
5622 | ||
5623 | if (info->disassembler_options | |
5624 | && strstr (info->disassembler_options, "vsx") != NULL) | |
5625 | @@ -266,7 +267,8 @@ | |
5626 | continue; | |
5627 | ||
5628 | if ((insn & opcode->mask) != opcode->opcode | |
5629 | - || (opcode->flags & dialect) == 0) | |
5630 | + || (opcode->flags & dialect) == 0 | |
5631 | + || (opcode->deprecated & dialect) != 0) | |
5632 | continue; | |
5633 | ||
5634 | /* Make two passes over the operands. First see if any of them | |
5635 | @@ -402,7 +404,7 @@ | |
5636 | The following PPC specific disassembler options are supported for use with\n\ | |
5637 | the -M switch:\n"); | |
5638 | ||
5639 | - fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n"); | |
5640 | + fprintf (stream, " booke Disassemble the BookE instructions\n"); | |
5641 | fprintf (stream, " e300 Disassemble the e300 instructions\n"); | |
5642 | fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n"); | |
5643 | fprintf (stream, " e500mc Disassemble the e500mc instructions\n"); | |
5644 | diff -Naur binutils-2.19.1.orig/opcodes/ppc-opc.c binutils-2.19.1/opcodes/ppc-opc.c | |
5645 | --- binutils-2.19.1.orig/opcodes/ppc-opc.c 2008-12-23 05:54:52.000000000 -0800 | |
5646 | +++ binutils-2.19.1/opcodes/ppc-opc.c 2009-03-03 17:08:22.000000000 -0800 | |
5647 | @@ -1,6 +1,6 @@ | |
5648 | /* ppc-opc.c -- PowerPC opcode list | |
5649 | Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, | |
5650 | - 2005, 2006, 2007, 2008 Free Software Foundation, Inc. | |
5651 | + 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. | |
5652 | Written by Ian Lance Taylor, Cygnus Support | |
5653 | ||
5654 | This file is part of the GNU opcodes library. | |
5655 | @@ -81,6 +81,10 @@ | |
5656 | static long extract_xb6 (unsigned long, ppc_cpu_t, int *); | |
5657 | static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **); | |
5658 | static long extract_xb6s (unsigned long, ppc_cpu_t, int *); | |
5659 | +static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **); | |
5660 | +static long extract_xc6 (unsigned long, ppc_cpu_t, int *); | |
5661 | +static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **); | |
5662 | +static long extract_dm (unsigned long, ppc_cpu_t, int *); | |
5663 | \f | |
5664 | /* The operands table. | |
5665 | ||
5666 | @@ -223,19 +227,9 @@ | |
5667 | #define D CT + 1 | |
5668 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
5669 | ||
5670 | - /* The DE field in a DE form instruction. This is like D, but is 12 | |
5671 | - bits only. */ | |
5672 | -#define DE D + 1 | |
5673 | - { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
5674 | - | |
5675 | - /* The DES field in a DES form instruction. This is like DS, but is 14 | |
5676 | - bits only (12 stored.) */ | |
5677 | -#define DES DE + 1 | |
5678 | - { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, | |
5679 | - | |
5680 | /* The DQ field in a DQ form instruction. This is like D, but the | |
5681 | lower four bits are forced to zero. */ | |
5682 | -#define DQ DES + 1 | |
5683 | +#define DQ D + 1 | |
5684 | { 0xfff0, 0, NULL, NULL, | |
5685 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, | |
5686 | ||
5687 | @@ -320,8 +314,9 @@ | |
5688 | #define LIA LI + 1 | |
5689 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
5690 | ||
5691 | - /* The LS field in an X (sync) form instruction. */ | |
5692 | + /* The LS or WC field in an X (sync or wait) form instruction. */ | |
5693 | #define LS LIA + 1 | |
5694 | +#define WC LS | |
5695 | { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, | |
5696 | ||
5697 | /* The ME field in an M form instruction. */ | |
5698 | @@ -617,7 +612,7 @@ | |
5699 | #define XA6 XT6 + 1 | |
5700 | { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, | |
5701 | ||
5702 | - /* The XB field in an XX3 form instruction. This is split. */ | |
5703 | + /* The XB field in an XX2 or XX3 form instruction. This is split. */ | |
5704 | #define XB6 XA6 + 1 | |
5705 | { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, | |
5706 | ||
5707 | @@ -627,9 +622,22 @@ | |
5708 | #define XB6S XB6 + 1 | |
5709 | { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, | |
5710 | ||
5711 | - /* The DM field in an XX3 form instruction. */ | |
5712 | -#define DM XB6S + 1 | |
5713 | + /* The XC field in an XX4 form instruction. This is split. */ | |
5714 | +#define XC6 XB6S + 1 | |
5715 | + { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, | |
5716 | + | |
5717 | + /* The DM or SHW field in an XX3 form instruction. */ | |
5718 | +#define DM XC6 + 1 | |
5719 | +#define SHW DM | |
5720 | { 0x3, 8, NULL, NULL, 0 }, | |
5721 | + | |
5722 | + /* The DM field in an extended mnemonic XX3 form instruction. */ | |
5723 | +#define DMEX DM + 1 | |
5724 | + { 0x3, 8, insert_dm, extract_dm, 0 }, | |
5725 | + | |
5726 | + /* The UIM field in an XX2 form instruction. */ | |
5727 | +#define UIM DMEX + 1 | |
5728 | + { 0x3, 16, NULL, NULL, 0 }, | |
5729 | }; | |
5730 | ||
5731 | const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) | |
5732 | @@ -1405,6 +1413,49 @@ | |
5733 | *invalid = 1; | |
5734 | return 0; | |
5735 | } | |
5736 | + | |
5737 | +/* The XC field in an XX4 form instruction. This is split. */ | |
5738 | + | |
5739 | +static unsigned long | |
5740 | +insert_xc6 (unsigned long insn, | |
5741 | + long value, | |
5742 | + ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
5743 | + const char **errmsg ATTRIBUTE_UNUSED) | |
5744 | +{ | |
5745 | + return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); | |
5746 | +} | |
5747 | + | |
5748 | +static long | |
5749 | +extract_xc6 (unsigned long insn, | |
5750 | + ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
5751 | + int *invalid ATTRIBUTE_UNUSED) | |
5752 | +{ | |
5753 | + return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); | |
5754 | +} | |
5755 | + | |
5756 | +static unsigned long | |
5757 | +insert_dm (unsigned long insn, | |
5758 | + long value, | |
5759 | + ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
5760 | + const char **errmsg) | |
5761 | +{ | |
5762 | + if (value != 0 && value != 1) | |
5763 | + *errmsg = _("invalid constant"); | |
5764 | + return insn | (((value) ? 3 : 0) << 8); | |
5765 | +} | |
5766 | + | |
5767 | +static long | |
5768 | +extract_dm (unsigned long insn, | |
5769 | + ppc_cpu_t dialect ATTRIBUTE_UNUSED, | |
5770 | + int *invalid) | |
5771 | +{ | |
5772 | + long value; | |
5773 | + | |
5774 | + value = (insn >> 8) & 3; | |
5775 | + if (value != 0 && value != 3) | |
5776 | + *invalid = 1; | |
5777 | + return (value) ? 1 : 0; | |
5778 | +} | |
5779 | \f | |
5780 | /* Macros used to form opcodes. */ | |
5781 | ||
5782 | @@ -1487,10 +1538,6 @@ | |
5783 | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) | |
5784 | #define DS_MASK DSO (0x3f, 3) | |
5785 | ||
5786 | -/* A DE form instruction. */ | |
5787 | -#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) | |
5788 | -#define DE_MASK DEO (0x3e, 0xf) | |
5789 | - | |
5790 | /* An EVSEL form instruction. */ | |
5791 | #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) | |
5792 | #define EVSEL_MASK EVSEL(0x3f, 0xff) | |
5793 | @@ -1550,11 +1597,17 @@ | |
5794 | /* An X form instruction. */ | |
5795 | #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) | |
5796 | ||
5797 | +/* An XX2 form instruction. */ | |
5798 | +#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) | |
5799 | + | |
5800 | /* An XX3 form instruction. */ | |
5801 | #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) | |
5802 | ||
5803 | -#define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \ | |
5804 | - | ((((unsigned long)(dm)) & 0x3) << 8)) | |
5805 | +/* An XX3 form instruction with the RC bit specified. */ | |
5806 | +#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3)) | |
5807 | + | |
5808 | +/* An XX4 form instruction. */ | |
5809 | +#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4)) | |
5810 | ||
5811 | /* A Z form instruction. */ | |
5812 | #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) | |
5813 | @@ -1571,11 +1624,30 @@ | |
5814 | /* The mask for an XX1 form instruction. */ | |
5815 | #define XX1_MASK X (0x3f, 0x3ff) | |
5816 | ||
5817 | +/* The mask for an XX2 form instruction. */ | |
5818 | +#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) | |
5819 | + | |
5820 | +/* The mask for an XX2 form instruction with the UIM bits specified. */ | |
5821 | +#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) | |
5822 | + | |
5823 | +/* The mask for an XX2 form instruction with the BF bits specified. */ | |
5824 | +#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) | |
5825 | + | |
5826 | /* The mask for an XX3 form instruction. */ | |
5827 | #define XX3_MASK XX3 (0x3f, 0xff) | |
5828 | ||
5829 | -/* The mask for an XX3 form instruction with the DM bits specified. */ | |
5830 | +/* The mask for an XX3 form instruction with the BF bits specified. */ | |
5831 | +#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) | |
5832 | + | |
5833 | +/* The mask for an XX3 form instruction with the DM or SHW bits specified. */ | |
5834 | #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) | |
5835 | +#define XX3SHW_MASK XX3DM_MASK | |
5836 | + | |
5837 | +/* The mask for an XX4 form instruction. */ | |
5838 | +#define XX4_MASK XX4 (0x3f, 0x3) | |
5839 | + | |
5840 | +/* An X form wait instruction with everything filled in except the WC field. */ | |
5841 | +#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) | |
5842 | ||
5843 | /* The mask for a Z form instruction. */ | |
5844 | #define Z_MASK ZRC (0x3f, 0x1ff, 1) | |
5845 | @@ -1810,13 +1882,14 @@ | |
5846 | \f | |
5847 | /* Smaller names for the flags so each entry in the opcodes table will | |
5848 | fit on a single line. */ | |
5849 | +#define PPCNONE 0 | |
5850 | #undef PPC | |
5851 | #define PPC PPC_OPCODE_PPC | |
5852 | #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | |
5853 | -#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM | |
5854 | #define POWER4 PPC_OPCODE_POWER4 | |
5855 | #define POWER5 PPC_OPCODE_POWER5 | |
5856 | #define POWER6 PPC_OPCODE_POWER6 | |
5857 | +#define POWER7 PPC_OPCODE_POWER7 | |
5858 | #define CELL PPC_OPCODE_CELL | |
5859 | #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | |
5860 | #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | |
5861 | @@ -1841,7 +1914,6 @@ | |
5862 | #define MFDEC1 PPC_OPCODE_POWER | |
5863 | #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | |
5864 | #define BOOKE PPC_OPCODE_BOOKE | |
5865 | -#define BOOKE64 PPC_OPCODE_BOOKE64 | |
5866 | #define CLASSIC PPC_OPCODE_CLASSIC | |
5867 | #define PPCE300 PPC_OPCODE_E300 | |
5868 | #define PPCSPE PPC_OPCODE_SPE | |
5869 | @@ -1850,7 +1922,6 @@ | |
5870 | #define PPCBRLK PPC_OPCODE_BRLOCK | |
5871 | #define PPCPMR PPC_OPCODE_PMR | |
5872 | #define PPCCHLK PPC_OPCODE_CACHELCK | |
5873 | -#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 | |
5874 | #define PPCRFMCI PPC_OPCODE_RFMCI | |
5875 | #define E500MC PPC_OPCODE_E500MC | |
5876 | \f | |
5877 | @@ -1876,3253 +1947,3347 @@ | |
5878 | constrained otherwise by disassembler operation. */ | |
5879 | ||
5880 | const struct powerpc_opcode powerpc_opcodes[] = { | |
5881 | -{"attn", X(0,256), X_MASK, POWER4, {0}}, | |
5882 | -{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, {RA, SI}}, | |
5883 | -{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, {RA, SI}}, | |
5884 | -{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, {RA, SI}}, | |
5885 | -{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, {RA, SI}}, | |
5886 | -{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, {RA, SI}}, | |
5887 | -{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, {RA, SI}}, | |
5888 | -{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, {RA, SI}}, | |
5889 | -{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, {RA, SI}}, | |
5890 | -{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, {RA, SI}}, | |
5891 | -{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, {RA, SI}}, | |
5892 | -{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, {RA, SI}}, | |
5893 | -{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, {RA, SI}}, | |
5894 | -{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, {RA, SI}}, | |
5895 | -{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, {RA, SI}}, | |
5896 | -{"tdi", OP(2), OP_MASK, PPC64, {TO, RA, SI}}, | |
5897 | - | |
5898 | -{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5899 | -{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5900 | -{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5901 | -{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5902 | -{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5903 | -{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5904 | -{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5905 | -{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5906 | -{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5907 | -{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5908 | -{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5909 | -{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5910 | -{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5911 | -{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5912 | -{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5913 | -{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5914 | -{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5915 | -{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5916 | -{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5917 | -{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5918 | -{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5919 | -{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5920 | -{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5921 | -{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5922 | -{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5923 | -{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5924 | -{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, {RA, SI}}, | |
5925 | -{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, {RA, SI}}, | |
5926 | -{"twi", OP(3), OP_MASK, PPCCOM, {TO, RA, SI}}, | |
5927 | -{"ti", OP(3), OP_MASK, PWRCOM, {TO, RA, SI}}, | |
5928 | - | |
5929 | -{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, | |
5930 | -{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5931 | -{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5932 | -{"vrlb", VX (4, 4), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5933 | -{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
5934 | -{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5935 | -{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5936 | -{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}}, | |
5937 | -{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5938 | -{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}}, | |
5939 | -{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5940 | -{"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
5941 | -{"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
5942 | -{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5943 | -{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5944 | -{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5945 | -{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5946 | -{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, | |
5947 | -{"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
5948 | -{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, | |
5949 | -{"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
5950 | -{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, | |
5951 | -{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, | |
5952 | -{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5953 | -{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5954 | -{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5955 | -{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5956 | -{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5957 | -{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5958 | -{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5959 | -{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, | |
5960 | -{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5961 | -{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, | |
5962 | -{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5963 | -{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5964 | -{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5965 | -{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, | |
5966 | -{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5967 | -{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, | |
5968 | -{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5969 | -{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, | |
5970 | -{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5971 | -{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, {FRT, FRA, FRB}}, | |
5972 | -{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, {VD, VA, VB, VC}}, | |
5973 | -{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, {VD, VA, VB, SHB}}, | |
5974 | -{"ps_sel", A (4, 23,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5975 | -{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, {VD, VA, VC, VB}}, | |
5976 | -{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5977 | -{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, {VD, VA, VC, VB}}, | |
5978 | -{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, | |
5979 | -{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, | |
5980 | -{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, | |
5981 | -{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, {FRT, FRA, FRC}}, | |
5982 | -{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, | |
5983 | -{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, {FRT, FRB}}, | |
5984 | -{"ps_msub", A (4, 28,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5985 | -{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5986 | -{"ps_madd", A (4, 29,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5987 | -{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5988 | -{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5989 | -{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5990 | -{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5991 | -{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, {FRT, FRA, FRC, FRB}}, | |
5992 | -{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, | |
5993 | -{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5994 | -{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5995 | -{"vrlh", VX (4, 68), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5996 | -{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
5997 | -{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5998 | -{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
5999 | -{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, {FRT,RA,RB,PSWM,PSQM}}, | |
6000 | -{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6001 | -{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, {FRS,RA,RB,PSWM,PSQM}}, | |
6002 | -{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6003 | -{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, {FRT, FRB}}, | |
6004 | -{"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6005 | -{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, {FRT, FRB}}, | |
6006 | -{"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6007 | -{"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6008 | -{"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6009 | -{"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6010 | -{"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6011 | -{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, | |
6012 | -{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6013 | -{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6014 | -{"vrlw", VX (4, 132), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6015 | -{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6016 | -{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6017 | -{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6018 | -{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, {FRT, FRB}}, | |
6019 | -{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, {FRT, FRB}}, | |
6020 | -{"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6021 | -{"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6022 | -{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, {BF, FRA, FRB}}, | |
6023 | -{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6024 | -{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6025 | -{"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6026 | -{"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6027 | -{"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6028 | -{"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6029 | -{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6030 | -{"vslb", VX (4, 260), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6031 | -{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6032 | -{"vrefp", VX (4, 266), VX_MASK, PPCVEC, {VD, VB}}, | |
6033 | -{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6034 | -{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6035 | -{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, {FRT, FRB}}, | |
6036 | -{"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6037 | -{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, {FRT, FRB}}, | |
6038 | -{"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6039 | -{"macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6040 | -{"macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6041 | -{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6042 | -{"vslh", VX (4, 324), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6043 | -{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6044 | -{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, {VD, VB}}, | |
6045 | -{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6046 | -{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6047 | -{"mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6048 | -{"mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6049 | -{"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6050 | -{"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6051 | -{"nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6052 | -{"nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6053 | -{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6054 | -{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6055 | -{"vslw", VX (4, 388), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6056 | -{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, {VD, VB}}, | |
6057 | -{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6058 | -{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6059 | -{"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6060 | -{"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6061 | -{"vsl", VX (4, 452), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6062 | -{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6063 | -{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, {VD, VB}}, | |
6064 | -{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6065 | -{"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6066 | -{"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6067 | -{"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6068 | -{"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6069 | -{"evaddw", VX (4, 512), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6070 | -{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6071 | -{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, {RS, RB, UIMM}}, | |
6072 | -{"vminub", VX (4, 514), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6073 | -{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6074 | -{"evsubw", VX (4, 516), VX_MASK, PPCSPE, {RS, RB, RA}}, | |
6075 | -{"vsrb", VX (4, 516), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6076 | -{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, {RS, UIMM, RB}}, | |
6077 | -{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, {RS, RB, UIMM}}, | |
6078 | -{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6079 | -{"evabs", VX (4, 520), VX_MASK, PPCSPE, {RS, RA}}, | |
6080 | -{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6081 | -{"evneg", VX (4, 521), VX_MASK, PPCSPE, {RS, RA}}, | |
6082 | -{"evextsb", VX (4, 522), VX_MASK, PPCSPE, {RS, RA}}, | |
6083 | -{"vrfin", VX (4, 522), VX_MASK, PPCVEC, {VD, VB}}, | |
6084 | -{"evextsh", VX (4, 523), VX_MASK, PPCSPE, {RS, RA}}, | |
6085 | -{"evrndw", VX (4, 524), VX_MASK, PPCSPE, {RS, RA}}, | |
6086 | -{"vspltb", VX (4, 524), VX_MASK, PPCVEC, {VD, VB, UIMM}}, | |
6087 | -{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, {RS, RA}}, | |
6088 | -{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, {RS, RA}}, | |
6089 | -{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, {VD, VB}}, | |
6090 | -{"brinc", VX (4, 527), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6091 | -{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, {FRT, FRB}}, | |
6092 | -{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, {FRT, FRB}}, | |
6093 | -{"evand", VX (4, 529), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6094 | -{"evandc", VX (4, 530), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6095 | -{"evxor", VX (4, 534), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6096 | -{"evmr", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, BBA}}, | |
6097 | -{"evor", VX (4, 535), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6098 | -{"evnor", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6099 | -{"evnot", VX (4, 536), VX_MASK, PPCSPE, {RS, RA, BBA}}, | |
6100 | -{"get", APU(4, 268,0), APU_RA_MASK, PPC405, {RT, FSL}}, | |
6101 | -{"eveqv", VX (4, 537), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6102 | -{"evorc", VX (4, 539), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6103 | -{"evnand", VX (4, 542), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6104 | -{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6105 | -{"evsrws", VX (4, 545), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6106 | -{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, | |
6107 | -{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, | |
6108 | -{"evslw", VX (4, 548), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6109 | -{"evslwi", VX (4, 550), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, | |
6110 | -{"evrlw", VX (4, 552), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6111 | -{"evsplati", VX (4, 553), VX_MASK, PPCSPE, {RS, SIMM}}, | |
6112 | -{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, {RS, RA, EVUIMM}}, | |
6113 | -{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, {RS, SIMM}}, | |
6114 | -{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6115 | -{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6116 | -{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6117 | -{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6118 | -{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6119 | -{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6120 | -{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6121 | -{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6122 | -{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6123 | -{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, {RT, FSL}}, | |
6124 | -{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6125 | -{"vminuh", VX (4, 578), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6126 | -{"vsrh", VX (4, 580), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6127 | -{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6128 | -{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6129 | -{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, {VD, VB}}, | |
6130 | -{"vsplth", VX (4, 588), VX_MASK, PPCVEC, {VD, VB, UIMM}}, | |
6131 | -{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, {VD, VB}}, | |
6132 | -{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, {RT, FSL}}, | |
6133 | -{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, {RS, RA, RB, CRFS}}, | |
6134 | -{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, {RT, FSL}}, | |
6135 | -{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6136 | -{"vadduws", VX (4, 640), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6137 | -{"evfssub", VX (4, 641), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6138 | -{"vminuw", VX (4, 642), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6139 | -{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, {RS, RA}}, | |
6140 | -{"vsrw", VX (4, 644), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6141 | -{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, {RS, RA}}, | |
6142 | -{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, {RS, RA}}, | |
6143 | -{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6144 | -{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6145 | -{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6146 | -{"vrfip", VX (4, 650), VX_MASK, PPCVEC, {VD, VB}}, | |
6147 | -{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6148 | -{"vspltw", VX (4, 652), VX_MASK, PPCVEC, {VD, VB, UIMM}}, | |
6149 | -{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6150 | -{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6151 | -{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, {VD, VB}}, | |
6152 | -{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, {RS, RB}}, | |
6153 | -{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, {RS, RB}}, | |
6154 | -{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, {RS, RB}}, | |
6155 | -{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, {RS, RB}}, | |
6156 | -{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, {RS, RB}}, | |
6157 | -{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, {RS, RB}}, | |
6158 | -{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, {RS, RB}}, | |
6159 | -{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, {RS, RB}}, | |
6160 | -{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, {RS, RB}}, | |
6161 | -{"put", APU(4, 332,0), APU_RT_MASK, PPC405, {RA, FSL}}, | |
6162 | -{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, {RS, RB}}, | |
6163 | -{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6164 | -{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6165 | -{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, {CRFD, RA, RB}}, | |
6166 | -{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, {RA, FSL}}, | |
6167 | -{"efsadd", VX (4, 704), VX_MASK, PPCEFS, {RS, RA, RB}}, | |
6168 | -{"efssub", VX (4, 705), VX_MASK, PPCEFS, {RS, RA, RB}}, | |
6169 | -{"efsabs", VX (4, 708), VX_MASK, PPCEFS, {RS, RA}}, | |
6170 | -{"vsr", VX (4, 708), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6171 | -{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, {RS, RA}}, | |
6172 | -{"efsneg", VX (4, 710), VX_MASK, PPCEFS, {RS, RA}}, | |
6173 | -{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6174 | -{"efsmul", VX (4, 712), VX_MASK, PPCEFS, {RS, RA, RB}}, | |
6175 | -{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, {RS, RA, RB}}, | |
6176 | -{"vrfim", VX (4, 714), VX_MASK, PPCVEC, {VD, VB}}, | |
6177 | -{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6178 | -{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6179 | -{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6180 | -{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, {VD, VB}}, | |
6181 | -{"efscfd", VX (4, 719), VX_MASK, PPCEFS, {RS, RB}}, | |
6182 | -{"efscfui", VX (4, 720), VX_MASK, PPCEFS, {RS, RB}}, | |
6183 | -{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, {RS, RB}}, | |
6184 | -{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, {RS, RB}}, | |
6185 | -{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, {RS, RB}}, | |
6186 | -{"efsctui", VX (4, 724), VX_MASK, PPCEFS, {RS, RB}}, | |
6187 | -{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, {RS, RB}}, | |
6188 | -{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, {RS, RB}}, | |
6189 | -{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, {RS, RB}}, | |
6190 | -{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, {RS, RB}}, | |
6191 | -{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, {RA, FSL}}, | |
6192 | -{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, {RS, RB}}, | |
6193 | -{"efststgt", VX (4, 732), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6194 | -{"efststlt", VX (4, 733), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6195 | -{"efststeq", VX (4, 734), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6196 | -{"efdadd", VX (4, 736), VX_MASK, PPCEFS, {RS, RA, RB}}, | |
6197 | -{"efdsub", VX (4, 737), VX_MASK, PPCEFS, {RS, RA, RB}}, | |
6198 | -{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, {RS, RB}}, | |
6199 | -{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, {RS, RB}}, | |
6200 | -{"efdabs", VX (4, 740), VX_MASK, PPCEFS, {RS, RA}}, | |
6201 | -{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, {RS, RA}}, | |
6202 | -{"efdneg", VX (4, 742), VX_MASK, PPCEFS, {RS, RA}}, | |
6203 | -{"efdmul", VX (4, 744), VX_MASK, PPCEFS, {RS, RA, RB}}, | |
6204 | -{"efddiv", VX (4, 745), VX_MASK, PPCEFS, {RS, RA, RB}}, | |
6205 | -{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, {RS, RB}}, | |
6206 | -{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, {RS, RB}}, | |
6207 | -{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6208 | -{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6209 | -{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6210 | -{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, {RS, RB}}, | |
6211 | -{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, {RS, RB}}, | |
6212 | -{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, {RS, RB}}, | |
6213 | -{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, {RS, RB}}, | |
6214 | -{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, {RS, RB}}, | |
6215 | -{"efdctui", VX (4, 756), VX_MASK, PPCEFS, {RS, RB}}, | |
6216 | -{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, {RS, RB}}, | |
6217 | -{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, {RS, RB}}, | |
6218 | -{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, {RS, RB}}, | |
6219 | -{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, {RS, RB}}, | |
6220 | -{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, {RA, FSL}}, | |
6221 | -{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, {RS, RB}}, | |
6222 | -{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6223 | -{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6224 | -{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, {CRFD, RA, RB}}, | |
6225 | -{"evlddx", VX (4, 768), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6226 | -{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6227 | -{"evldd", VX (4, 769), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, | |
6228 | -{"evldwx", VX (4, 770), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6229 | -{"vminsb", VX (4, 770), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6230 | -{"evldw", VX (4, 771), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, | |
6231 | -{"evldhx", VX (4, 772), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6232 | -{"vsrab", VX (4, 772), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6233 | -{"evldh", VX (4, 773), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, | |
6234 | -{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6235 | -{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6236 | -{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6237 | -{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}}, | |
6238 | -{"vcfux", VX (4, 778), VX_MASK, PPCVEC, {VD, VB, UIMM}}, | |
6239 | -{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6240 | -{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, {VD, SIMM}}, | |
6241 | -{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}}, | |
6242 | -{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6243 | -{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6244 | -{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, {RS, EVUIMM_2, RA}}, | |
6245 | -{"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6246 | -{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6247 | -{"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6248 | -{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, | |
6249 | -{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6250 | -{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, | |
6251 | -{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6252 | -{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, | |
6253 | -{"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6254 | -{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6255 | -{"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6256 | -{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, | |
6257 | -{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6258 | -{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, | |
6259 | -{"evstddx", VX (4, 800), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6260 | -{"evstdd", VX (4, 801), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, | |
6261 | -{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6262 | -{"evstdw", VX (4, 803), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, | |
6263 | -{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6264 | -{"evstdh", VX (4, 805), VX_MASK, PPCSPE, {RS, EVUIMM_8, RA}}, | |
6265 | -{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6266 | -{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, | |
6267 | -{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6268 | -{"evstwho", VX (4, 821), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, | |
6269 | -{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6270 | -{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, | |
6271 | -{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6272 | -{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, {RS, EVUIMM_4, RA}}, | |
6273 | -{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6274 | -{"vminsh", VX (4, 834), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6275 | -{"vsrah", VX (4, 836), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6276 | -{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6277 | -{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6278 | -{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, {VD, VB, UIMM}}, | |
6279 | -{"vspltish", VX (4, 844), VX_MASK, PPCVEC, {VD, SIMM}}, | |
6280 | -{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, {VD, VB}}, | |
6281 | -{"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6282 | -{"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6283 | -{"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6284 | -{"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6285 | -{"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6286 | -{"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6287 | -{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6288 | -{"vminsw", VX (4, 898), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6289 | -{"vsraw", VX (4, 900), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6290 | -{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6291 | -{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, {VD, VB, UIMM}}, | |
6292 | -{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, {VD, SIMM}}, | |
6293 | -{"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6294 | -{"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6295 | -{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6296 | -{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, {VD, VB, UIMM}}, | |
6297 | -{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, {VD, VB}}, | |
6298 | -{"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6299 | -{"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6300 | -{"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6301 | -{"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6302 | -{"vsububm", VX (4,1024), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6303 | -{"vavgub", VX (4,1026), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6304 | -{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6305 | -{"vand", VX (4,1028), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6306 | -{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6307 | -{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6308 | -{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6309 | -{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6310 | -{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6311 | -{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6312 | -{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6313 | -{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6314 | -{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6315 | -{"vslo", VX (4,1036), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6316 | -{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6317 | -{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6318 | -{"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6319 | -{"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6320 | -{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, | |
6321 | -{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, | |
6322 | -{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6323 | -{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6324 | -{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6325 | -{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6326 | -{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6327 | -{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6328 | -{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6329 | -{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6330 | -{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6331 | -{"vavguh", VX (4,1090), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6332 | -{"vandc", VX (4,1092), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6333 | -{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6334 | -{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6335 | -{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6336 | -{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6337 | -{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6338 | -{"vminfp", VX (4,1098), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6339 | -{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6340 | -{"vsro", VX (4,1100), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6341 | -{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6342 | -{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6343 | -{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6344 | -{"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6345 | -{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6346 | -{"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6347 | -{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6348 | -{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6349 | -{"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6350 | -{"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6351 | -{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, | |
6352 | -{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, | |
6353 | -{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6354 | -{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6355 | -{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6356 | -{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6357 | -{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6358 | -{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6359 | -{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6360 | -{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6361 | -{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6362 | -{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6363 | -{"vavguw", VX (4,1154), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6364 | -{"vor", VX (4,1156), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6365 | -{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6366 | -{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6367 | -{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6368 | -{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6369 | -{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6370 | -{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, | |
6371 | -{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, | |
6372 | -{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, {RS, RA}}, | |
6373 | -{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, {RS, RA}}, | |
6374 | -{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, {RS, RA}}, | |
6375 | -{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, {RS, RA}}, | |
6376 | -{"evmra", VX (4,1220), VX_MASK, PPCSPE, {RS, RA}}, | |
6377 | -{"vxor", VX (4,1220), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6378 | -{"evdivws", VX (4,1222), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6379 | -{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6380 | -{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6381 | -{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6382 | -{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6383 | -{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, {RS, RA}}, | |
6384 | -{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, {RS, RA}}, | |
6385 | -{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, {RS, RA}}, | |
6386 | -{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, {RS, RA}}, | |
6387 | -{"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6388 | -{"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6389 | -{"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6390 | -{"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6391 | -{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, | |
6392 | -{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, {FRT, FRA, FRB}}, | |
6393 | -{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6394 | -{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6395 | -{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6396 | -{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6397 | -{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6398 | -{"vnor", VX (4,1284), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6399 | -{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6400 | -{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6401 | -{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6402 | -{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6403 | -{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6404 | -{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6405 | -{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6406 | -{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6407 | -{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6408 | -{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6409 | -{"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6410 | -{"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6411 | -{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6412 | -{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6413 | -{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6414 | -{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6415 | -{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6416 | -{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6417 | -{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6418 | -{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6419 | -{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6420 | -{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6421 | -{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6422 | -{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6423 | -{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6424 | -{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6425 | -{"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6426 | -{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6427 | -{"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6428 | -{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6429 | -{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6430 | -{"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6431 | -{"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6432 | -{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6433 | -{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6434 | -{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6435 | -{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6436 | -{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6437 | -{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6438 | -{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6439 | -{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6440 | -{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6441 | -{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6442 | -{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6443 | -{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6444 | -{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6445 | -{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6446 | -{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6447 | -{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6448 | -{"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6449 | -{"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6450 | -{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6451 | -{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6452 | -{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6453 | -{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6454 | -{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6455 | -{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6456 | -{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6457 | -{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6458 | -{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6459 | -{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6460 | -{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, {URT, URA, URB}}, | |
6461 | -{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6462 | -{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6463 | -{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6464 | -{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6465 | -{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6466 | -{"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6467 | -{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6468 | -{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, {RS, RA, RB}}, | |
6469 | -{"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6470 | -{"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6471 | -{"vsububs", VX (4,1536), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6472 | -{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, {VD}}, | |
6473 | -{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6474 | -{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, {URT, URA, URB}}, | |
6475 | -{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, {URT, URA, URB}}, | |
6476 | -{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6477 | -{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6478 | -{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, {VB}}, | |
6479 | -{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6480 | -{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6481 | -{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, {URT, URA, URB}}, | |
6482 | -{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, {URT, URA, URB}}, | |
6483 | -{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6484 | -{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6485 | -{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, {URT, URA, URB}}, | |
6486 | -{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, {URT, URA, URB}}, | |
6487 | -{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6488 | -{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6489 | -{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, {URT, URA, URB}}, | |
6490 | -{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, {URT, URA, URB}}, | |
6491 | -{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6492 | -{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6493 | -{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, {URT, URA, URB}}, | |
6494 | -{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, {URT, URA, URB}}, | |
6495 | -{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6496 | -{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6497 | -{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6498 | -{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6499 | -{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6500 | -{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, {URT, URA, URB}}, | |
6501 | -{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, {URT, URA, URB}}, | |
6502 | -{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6503 | -{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6504 | -{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6505 | -{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6506 | -{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6507 | -{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6508 | -{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, {URT, URA, URB}}, | |
6509 | -{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, {URT, URA, URB}}, | |
6510 | -{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, {VD, VA, VB}}, | |
6511 | -{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6512 | -{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6513 | -{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, {VD, VA, VB}}, | |
6514 | -{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, {URT, URA, URB}}, | |
6515 | -{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, {URT, URA, URB}}, | |
6516 | -{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6517 | -{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6518 | -{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6519 | -{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, {RT, RA, RB}}, | |
6520 | -{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, {RA, RB}}, | |
6521 | - | |
6522 | -{"mulli", OP(7), OP_MASK, PPCCOM, {RT, RA, SI}}, | |
6523 | -{"muli", OP(7), OP_MASK, PWRCOM, {RT, RA, SI}}, | |
6524 | - | |
6525 | -{"subfic", OP(8), OP_MASK, PPCCOM, {RT, RA, SI}}, | |
6526 | -{"sfi", OP(8), OP_MASK, PWRCOM, {RT, RA, SI}}, | |
6527 | - | |
6528 | -{"dozi", OP(9), OP_MASK, M601, {RT, RA, SI}}, | |
6529 | - | |
6530 | -{"bce", B(9,0,0), B_MASK, BOOKE64, {BO, BI, BD}}, | |
6531 | -{"bcel", B(9,0,1), B_MASK, BOOKE64, {BO, BI, BD}}, | |
6532 | -{"bcea", B(9,1,0), B_MASK, BOOKE64, {BO, BI, BDA}}, | |
6533 | -{"bcela", B(9,1,1), B_MASK, BOOKE64, {BO, BI, BDA}}, | |
6534 | - | |
6535 | -{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, {OBF, RA, UI}}, | |
6536 | -{"cmpldi", OPL(10,1), OPL_MASK, PPC64, {OBF, RA, UI}}, | |
6537 | -{"cmpli", OP(10), OP_MASK, PPC, {BF, L, RA, UI}}, | |
6538 | -{"cmpli", OP(10), OP_MASK, PWRCOM, {BF, RA, UI}}, | |
6539 | - | |
6540 | -{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, {OBF, RA, SI}}, | |
6541 | -{"cmpdi", OPL(11,1), OPL_MASK, PPC64, {OBF, RA, SI}}, | |
6542 | -{"cmpi", OP(11), OP_MASK, PPC, {BF, L, RA, SI}}, | |
6543 | -{"cmpi", OP(11), OP_MASK, PWRCOM, {BF, RA, SI}}, | |
6544 | - | |
6545 | -{"addic", OP(12), OP_MASK, PPCCOM, {RT, RA, SI}}, | |
6546 | -{"ai", OP(12), OP_MASK, PWRCOM, {RT, RA, SI}}, | |
6547 | -{"subic", OP(12), OP_MASK, PPCCOM, {RT, RA, NSI}}, | |
6548 | - | |
6549 | -{"addic.", OP(13), OP_MASK, PPCCOM, {RT, RA, SI}}, | |
6550 | -{"ai.", OP(13), OP_MASK, PWRCOM, {RT, RA, SI}}, | |
6551 | -{"subic.", OP(13), OP_MASK, PPCCOM, {RT, RA, NSI}}, | |
6552 | - | |
6553 | -{"li", OP(14), DRA_MASK, PPCCOM, {RT, SI}}, | |
6554 | -{"lil", OP(14), DRA_MASK, PWRCOM, {RT, SI}}, | |
6555 | -{"addi", OP(14), OP_MASK, PPCCOM, {RT, RA0, SI}}, | |
6556 | -{"cal", OP(14), OP_MASK, PWRCOM, {RT, D, RA0}}, | |
6557 | -{"subi", OP(14), OP_MASK, PPCCOM, {RT, RA0, NSI}}, | |
6558 | -{"la", OP(14), OP_MASK, PPCCOM, {RT, D, RA0}}, | |
6559 | - | |
6560 | -{"lis", OP(15), DRA_MASK, PPCCOM, {RT, SISIGNOPT}}, | |
6561 | -{"liu", OP(15), DRA_MASK, PWRCOM, {RT, SISIGNOPT}}, | |
6562 | -{"addis", OP(15), OP_MASK, PPCCOM, {RT, RA0, SISIGNOPT}}, | |
6563 | -{"cau", OP(15), OP_MASK, PWRCOM, {RT, RA0, SISIGNOPT}}, | |
6564 | -{"subis", OP(15), OP_MASK, PPCCOM, {RT, RA0, NSI}}, | |
6565 | - | |
6566 | -{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}}, | |
6567 | -{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}}, | |
6568 | -{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, {BD}}, | |
6569 | -{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, {BD}}, | |
6570 | -{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}}, | |
6571 | -{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}}, | |
6572 | -{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, {BD}}, | |
6573 | -{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, {BD}}, | |
6574 | -{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}}, | |
6575 | -{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}}, | |
6576 | -{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, {BDA}}, | |
6577 | -{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, {BDA}}, | |
6578 | -{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}}, | |
6579 | -{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}}, | |
6580 | -{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, {BDA}}, | |
6581 | -{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, {BDA}}, | |
6582 | -{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDM}}, | |
6583 | -{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, {BDP}}, | |
6584 | -{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, {BD}}, | |
6585 | -{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDM}}, | |
6586 | -{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, {BDP}}, | |
6587 | -{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, {BD}}, | |
6588 | -{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDMA}}, | |
6589 | -{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, {BDPA}}, | |
6590 | -{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, {BDA}}, | |
6591 | -{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDMA}}, | |
6592 | -{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, {BDPA}}, | |
6593 | -{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, {BDA}}, | |
6594 | - | |
6595 | -{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6596 | -{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6597 | -{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6598 | -{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6599 | -{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6600 | -{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6601 | -{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6602 | -{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6603 | -{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6604 | -{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6605 | -{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6606 | -{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6607 | -{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6608 | -{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6609 | -{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6610 | -{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6611 | -{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6612 | -{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6613 | -{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6614 | -{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6615 | -{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6616 | -{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6617 | -{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6618 | -{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6619 | -{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6620 | -{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6621 | -{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6622 | -{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6623 | -{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6624 | -{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6625 | -{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6626 | -{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6627 | -{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6628 | -{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6629 | -{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6630 | -{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6631 | -{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6632 | -{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6633 | -{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6634 | -{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6635 | -{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6636 | -{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6637 | -{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6638 | -{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6639 | -{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6640 | -{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6641 | -{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6642 | -{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6643 | -{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6644 | -{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6645 | -{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6646 | -{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6647 | -{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6648 | -{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6649 | -{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6650 | -{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6651 | -{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6652 | -{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6653 | -{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6654 | -{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6655 | -{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6656 | -{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6657 | -{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6658 | -{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6659 | -{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6660 | -{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}}, | |
6661 | -{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6662 | -{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6663 | -{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6664 | -{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6665 | -{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6666 | -{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}}, | |
6667 | -{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6668 | -{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6669 | -{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6670 | -{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6671 | -{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6672 | -{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}}, | |
6673 | -{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6674 | -{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6675 | -{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6676 | -{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6677 | -{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6678 | -{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}}, | |
6679 | - | |
6680 | -{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6681 | -{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6682 | -{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6683 | -{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6684 | -{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6685 | -{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6686 | -{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6687 | -{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6688 | -{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6689 | -{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6690 | -{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6691 | -{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6692 | -{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6693 | -{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6694 | -{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6695 | -{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6696 | -{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6697 | -{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6698 | -{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6699 | -{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6700 | -{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6701 | -{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6702 | -{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6703 | -{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6704 | -{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6705 | -{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6706 | -{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6707 | -{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6708 | -{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6709 | -{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6710 | -{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6711 | -{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6712 | -{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6713 | -{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6714 | -{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6715 | -{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6716 | -{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6717 | -{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6718 | -{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, {CR, BD}}, | |
6719 | -{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6720 | -{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6721 | -{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, {CR, BD}}, | |
6722 | -{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6723 | -{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6724 | -{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, {CR, BD}}, | |
6725 | -{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDM}}, | |
6726 | -{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BDP}}, | |
6727 | -{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, {CR, BD}}, | |
6728 | -{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6729 | -{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6730 | -{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, {CR, BDA}}, | |
6731 | -{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6732 | -{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6733 | -{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, {CR, BDA}}, | |
6734 | -{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6735 | -{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6736 | -{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, {CR, BDA}}, | |
6737 | -{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDMA}}, | |
6738 | -{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDPA}}, | |
6739 | -{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, {CR, BDA}}, | |
6740 | - | |
6741 | -{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, | |
6742 | -{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, | |
6743 | -{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, | |
6744 | -{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, | |
6745 | -{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, | |
6746 | -{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, | |
6747 | -{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, | |
6748 | -{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, | |
6749 | -{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, | |
6750 | -{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, | |
6751 | -{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, | |
6752 | -{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, | |
6753 | -{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, | |
6754 | -{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, | |
6755 | -{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, | |
6756 | -{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, | |
6757 | -{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, | |
6758 | -{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, | |
6759 | -{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, | |
6760 | -{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, | |
6761 | -{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, | |
6762 | -{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, | |
6763 | -{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, | |
6764 | -{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, | |
6765 | - | |
6766 | -{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}}, | |
6767 | -{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}}, | |
6768 | -{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, {BI, BD}}, | |
6769 | -{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, {BI, BD}}, | |
6770 | -{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}}, | |
6771 | -{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}}, | |
6772 | -{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, {BI, BD}}, | |
6773 | -{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, {BI, BD}}, | |
6774 | -{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}}, | |
6775 | -{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}}, | |
6776 | -{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}}, | |
6777 | -{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}}, | |
6778 | -{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}}, | |
6779 | -{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}}, | |
6780 | -{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}}, | |
6781 | -{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}}, | |
6782 | - | |
6783 | -{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, | |
6784 | -{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, | |
6785 | -{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, | |
6786 | -{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, | |
6787 | -{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, | |
6788 | -{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, | |
6789 | -{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, | |
6790 | -{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, | |
6791 | -{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, | |
6792 | -{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, | |
6793 | -{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, | |
6794 | -{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, | |
6795 | -{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDM}}, | |
6796 | -{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, {BI, BDP}}, | |
6797 | -{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, {BI, BD}}, | |
6798 | -{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDM}}, | |
6799 | -{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, {BI, BDP}}, | |
6800 | -{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, {BI, BD}}, | |
6801 | -{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDMA}}, | |
6802 | -{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, {BI, BDPA}}, | |
6803 | -{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, {BI, BDA}}, | |
6804 | -{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDMA}}, | |
6805 | -{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, {BI, BDPA}}, | |
6806 | -{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, {BI, BDA}}, | |
6807 | - | |
6808 | -{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDM}}, | |
6809 | -{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BDP}}, | |
6810 | -{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, {BI, BD}}, | |
6811 | -{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, {BI, BD}}, | |
6812 | -{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDM}}, | |
6813 | -{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BDP}}, | |
6814 | -{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, {BI, BD}}, | |
6815 | -{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, {BI, BD}}, | |
6816 | -{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDMA}}, | |
6817 | -{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDPA}}, | |
6818 | -{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, {BI, BDA}}, | |
6819 | -{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, {BI, BDA}}, | |
6820 | -{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDMA}}, | |
6821 | -{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDPA}}, | |
6822 | -{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, {BI, BDA}}, | |
6823 | -{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, {BI, BDA}}, | |
6824 | - | |
6825 | -{"bc-", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDM}}, | |
6826 | -{"bc+", B(16,0,0), B_MASK, PPCCOM, {BOE, BI, BDP}}, | |
6827 | -{"bc", B(16,0,0), B_MASK, COM, {BO, BI, BD}}, | |
6828 | -{"bcl-", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDM}}, | |
6829 | -{"bcl+", B(16,0,1), B_MASK, PPCCOM, {BOE, BI, BDP}}, | |
6830 | -{"bcl", B(16,0,1), B_MASK, COM, {BO, BI, BD}}, | |
6831 | -{"bca-", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDMA}}, | |
6832 | -{"bca+", B(16,1,0), B_MASK, PPCCOM, {BOE, BI, BDPA}}, | |
6833 | -{"bca", B(16,1,0), B_MASK, COM, {BO, BI, BDA}}, | |
6834 | -{"bcla-", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDMA}}, | |
6835 | -{"bcla+", B(16,1,1), B_MASK, PPCCOM, {BOE, BI, BDPA}}, | |
6836 | -{"bcla", B(16,1,1), B_MASK, COM, {BO, BI, BDA}}, | |
6837 | - | |
6838 | -{"svc", SC(17,0,0), SC_MASK, POWER, {SVC_LEV, FL1, FL2}}, | |
6839 | -{"svcl", SC(17,0,1), SC_MASK, POWER, {SVC_LEV, FL1, FL2}}, | |
6840 | -{"sc", SC(17,1,0), SC_MASK, PPC, {LEV}}, | |
6841 | -{"svca", SC(17,1,0), SC_MASK, PWRCOM, {SV}}, | |
6842 | -{"svcla", SC(17,1,1), SC_MASK, POWER, {SV}}, | |
6843 | - | |
6844 | -{"b", B(18,0,0), B_MASK, COM, {LI}}, | |
6845 | -{"bl", B(18,0,1), B_MASK, COM, {LI}}, | |
6846 | -{"ba", B(18,1,0), B_MASK, COM, {LIA}}, | |
6847 | -{"bla", B(18,1,1), B_MASK, COM, {LIA}}, | |
6848 | - | |
6849 | -{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}}, | |
6850 | - | |
6851 | -{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}}, | |
6852 | -{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, | |
6853 | -{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}}, | |
6854 | -{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, | |
6855 | -{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, | |
6856 | -{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, | |
6857 | -{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, {0}}, | |
6858 | -{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, | |
6859 | -{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, {0}}, | |
6860 | -{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, | |
6861 | -{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, {0}}, | |
6862 | -{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, {0}}, | |
6863 | -{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, {0}}, | |
6864 | -{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, {0}}, | |
6865 | -{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, {0}}, | |
6866 | -{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, {0}}, | |
6867 | -{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, {0}}, | |
6868 | -{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, {0}}, | |
6869 | -{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, {0}}, | |
6870 | -{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, {0}}, | |
6871 | -{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, {0}}, | |
6872 | -{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, {0}}, | |
6873 | -{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, {0}}, | |
6874 | -{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, {0}}, | |
6875 | - | |
6876 | -{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6877 | -{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6878 | -{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6879 | -{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6880 | -{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6881 | -{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6882 | -{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6883 | -{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6884 | -{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6885 | -{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6886 | -{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6887 | -{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6888 | -{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6889 | -{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6890 | -{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6891 | -{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6892 | -{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6893 | -{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6894 | -{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6895 | -{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6896 | -{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6897 | -{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6898 | -{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6899 | -{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6900 | -{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6901 | -{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6902 | -{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6903 | -{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6904 | -{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6905 | -{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6906 | -{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6907 | -{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6908 | -{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6909 | -{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6910 | -{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6911 | -{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6912 | -{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6913 | -{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6914 | -{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6915 | -{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6916 | -{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6917 | -{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6918 | -{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6919 | -{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6920 | -{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6921 | -{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6922 | -{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6923 | -{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6924 | -{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6925 | -{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6926 | -{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6927 | -{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6928 | -{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6929 | -{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6930 | -{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6931 | -{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6932 | -{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6933 | -{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6934 | -{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6935 | -{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6936 | -{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6937 | -{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6938 | -{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6939 | -{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6940 | -{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6941 | -{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6942 | -{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6943 | -{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6944 | -{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6945 | -{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6946 | -{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6947 | -{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6948 | -{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6949 | -{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6950 | -{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6951 | -{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6952 | -{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6953 | -{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6954 | -{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6955 | -{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6956 | -{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6957 | -{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6958 | -{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6959 | -{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6960 | -{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6961 | -{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6962 | -{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6963 | -{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6964 | -{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6965 | -{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6966 | -{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6967 | -{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6968 | -{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6969 | -{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6970 | -{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6971 | -{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6972 | -{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6973 | -{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6974 | -{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6975 | -{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6976 | -{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6977 | -{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6978 | -{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6979 | -{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6980 | -{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6981 | -{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6982 | -{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6983 | -{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, {CR}}, | |
6984 | -{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
6985 | -{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6986 | -{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6987 | -{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6988 | -{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6989 | -{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6990 | -{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6991 | -{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6992 | -{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6993 | -{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6994 | -{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6995 | -{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
6996 | -{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6997 | -{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
6998 | -{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
6999 | -{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7000 | -{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7001 | -{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7002 | -{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7003 | -{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7004 | -{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7005 | -{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7006 | -{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7007 | -{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7008 | -{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7009 | -{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7010 | -{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7011 | -{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7012 | -{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7013 | -{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7014 | -{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7015 | -{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7016 | - | |
7017 | -{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, {BI}}, | |
7018 | -{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7019 | -{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, {BI}}, | |
7020 | -{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7021 | -{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7022 | -{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7023 | -{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, {BI}}, | |
7024 | -{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7025 | -{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, {BI}}, | |
7026 | -{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7027 | -{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7028 | -{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7029 | -{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, {BI}}, | |
7030 | -{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7031 | -{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, {BI}}, | |
7032 | -{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, {BI}}, | |
7033 | -{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7034 | -{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, {BI}}, | |
7035 | -{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7036 | -{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7037 | -{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, {BI}}, | |
7038 | -{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, {BI}}, | |
7039 | -{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, {BI}}, | |
7040 | -{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, {BI}}, | |
7041 | -{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, {BI}}, | |
7042 | -{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7043 | -{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, {BI}}, | |
7044 | -{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7045 | -{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7046 | -{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7047 | -{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, {BI}}, | |
7048 | -{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7049 | -{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, {BI}}, | |
7050 | -{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7051 | -{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7052 | -{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7053 | -{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, {BI}}, | |
7054 | -{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7055 | -{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, {BI}}, | |
7056 | -{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, {BI}}, | |
7057 | -{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7058 | -{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, {BI}}, | |
7059 | -{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7060 | -{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7061 | -{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, {BI}}, | |
7062 | -{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, {BI}}, | |
7063 | -{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, {BI}}, | |
7064 | -{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, {BI}}, | |
7065 | - | |
7066 | -{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, | |
7067 | -{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, | |
7068 | -{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, | |
7069 | -{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, | |
7070 | -{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, {BO, BI, BH}}, | |
7071 | -{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, {BO, BI}}, | |
7072 | -{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, {BO, BI, BH}}, | |
7073 | -{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, {BO, BI}}, | |
7074 | - | |
7075 | -{"bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, {BO, BI}}, | |
7076 | -{"bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, {BO, BI}}, | |
7077 | - | |
7078 | -{"rfid", XL(19,18), 0xffffffff, PPC64, {0}}, | |
7079 | - | |
7080 | -{"crnot", XL(19,33), XL_MASK, PPCCOM, {BT, BA, BBA}}, | |
7081 | -{"crnor", XL(19,33), XL_MASK, COM, {BT, BA, BB}}, | |
7082 | -{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, {0}}, | |
7083 | - | |
7084 | -{"rfdi", XL(19,39), 0xffffffff, E500MC, {0}}, | |
7085 | -{"rfi", XL(19,50), 0xffffffff, COM, {0}}, | |
7086 | -{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, {0}}, | |
7087 | - | |
7088 | -{"rfsvc", XL(19,82), 0xffffffff, POWER, {0}}, | |
7089 | - | |
7090 | -{"rfgi", XL(19,102), 0xffffffff, E500MC, {0}}, | |
7091 | - | |
7092 | -{"crandc", XL(19,129), XL_MASK, COM, {BT, BA, BB}}, | |
7093 | - | |
7094 | -{"isync", XL(19,150), 0xffffffff, PPCCOM, {0}}, | |
7095 | -{"ics", XL(19,150), 0xffffffff, PWRCOM, {0}}, | |
7096 | - | |
7097 | -{"crclr", XL(19,193), XL_MASK, PPCCOM, {BT, BAT, BBA}}, | |
7098 | -{"crxor", XL(19,193), XL_MASK, COM, {BT, BA, BB}}, | |
7099 | - | |
7100 | -{"dnh", X(19,198), X_MASK, E500MC, {DUI, DUIS}}, | |
7101 | - | |
7102 | -{"crnand", XL(19,225), XL_MASK, COM, {BT, BA, BB}}, | |
7103 | - | |
7104 | -{"crand", XL(19,257), XL_MASK, COM, {BT, BA, BB}}, | |
7105 | - | |
7106 | -{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, {0}}, | |
7107 | - | |
7108 | -{"crset", XL(19,289), XL_MASK, PPCCOM, {BT, BAT, BBA}}, | |
7109 | -{"creqv", XL(19,289), XL_MASK, COM, {BT, BA, BB}}, | |
7110 | - | |
7111 | -{"doze", XL(19,402), 0xffffffff, POWER6, {0}}, | |
7112 | - | |
7113 | -{"crorc", XL(19,417), XL_MASK, COM, {BT, BA, BB}}, | |
7114 | - | |
7115 | -{"nap", XL(19,434), 0xffffffff, POWER6, {0}}, | |
7116 | - | |
7117 | -{"crmove", XL(19,449), XL_MASK, PPCCOM, {BT, BA, BBA}}, | |
7118 | -{"cror", XL(19,449), XL_MASK, COM, {BT, BA, BB}}, | |
7119 | - | |
7120 | -{"sleep", XL(19,466), 0xffffffff, POWER6, {0}}, | |
7121 | -{"rvwinkle", XL(19,498), 0xffffffff, POWER6, {0}}, | |
7122 | - | |
7123 | -{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, {0}}, | |
7124 | -{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, {0}}, | |
7125 | - | |
7126 | -{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7127 | -{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7128 | -{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7129 | -{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7130 | -{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7131 | -{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7132 | -{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7133 | -{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7134 | -{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7135 | -{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7136 | -{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7137 | -{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7138 | -{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7139 | -{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7140 | -{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7141 | -{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7142 | -{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7143 | -{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7144 | -{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7145 | -{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7146 | -{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7147 | -{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7148 | -{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7149 | -{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7150 | -{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7151 | -{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7152 | -{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7153 | -{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7154 | -{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7155 | -{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7156 | -{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7157 | -{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7158 | -{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7159 | -{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7160 | -{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7161 | -{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7162 | -{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7163 | -{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7164 | -{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7165 | -{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7166 | -{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7167 | -{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7168 | -{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7169 | -{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7170 | -{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7171 | -{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7172 | -{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7173 | -{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7174 | -{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7175 | -{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7176 | -{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7177 | -{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7178 | -{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7179 | -{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7180 | -{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7181 | -{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7182 | -{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7183 | -{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7184 | -{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7185 | -{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7186 | -{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7187 | -{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7188 | -{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7189 | -{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7190 | -{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7191 | -{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7192 | -{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7193 | -{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7194 | -{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7195 | -{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7196 | -{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7197 | -{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7198 | -{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7199 | -{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7200 | -{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7201 | -{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7202 | -{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7203 | -{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7204 | -{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7205 | -{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7206 | -{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7207 | -{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7208 | -{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7209 | -{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7210 | -{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7211 | -{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7212 | -{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7213 | -{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7214 | -{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, {CR}}, | |
7215 | -{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7216 | -{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7217 | -{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7218 | -{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7219 | -{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7220 | -{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7221 | -{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7222 | -{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7223 | -{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7224 | -{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7225 | -{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, {CR}}, | |
7226 | -{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7227 | -{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7228 | -{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7229 | -{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7230 | -{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7231 | -{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7232 | -{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7233 | -{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7234 | -{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7235 | -{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7236 | -{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7237 | -{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7238 | -{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7239 | -{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7240 | -{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7241 | -{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7242 | -{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7243 | -{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, {CR}}, | |
7244 | -{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7245 | -{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, {CR}}, | |
7246 | - | |
7247 | -{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, {BI}}, | |
7248 | -{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7249 | -{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, {BI}}, | |
7250 | -{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7251 | -{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7252 | -{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7253 | -{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, {BI}}, | |
7254 | -{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, {BI}}, | |
7255 | -{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, {BI}}, | |
7256 | -{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, {BI}}, | |
7257 | -{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, {BI}}, | |
7258 | -{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7259 | -{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, {BI}}, | |
7260 | -{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7261 | -{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7262 | -{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, {BI}}, | |
7263 | -{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, {BI}}, | |
7264 | -{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, {BI}}, | |
7265 | -{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, {BI}}, | |
7266 | -{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, {BI}}, | |
7267 | - | |
7268 | -{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, | |
7269 | -{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, | |
7270 | -{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, {BOE, BI}}, | |
7271 | -{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, {BOE, BI}}, | |
7272 | -{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, {BO, BI, BH}}, | |
7273 | -{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, {BO, BI}}, | |
7274 | -{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, {BO, BI, BH}}, | |
7275 | -{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, {BO, BI}}, | |
7276 | - | |
7277 | -{"bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, {BO, BI}}, | |
7278 | -{"bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, {BO, BI}}, | |
7279 | - | |
7280 | -{"rlwimi", M(20,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, | |
7281 | -{"rlimi", M(20,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, | |
7282 | - | |
7283 | -{"rlwimi.", M(20,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, | |
7284 | -{"rlimi.", M(20,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, | |
7285 | - | |
7286 | -{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, {RA, RS, SH}}, | |
7287 | -{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, {RA, RS, MB}}, | |
7288 | -{"rlwinm", M(21,0), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, | |
7289 | -{"rlinm", M(21,0), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, | |
7290 | -{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, {RA, RS, SH}}, | |
7291 | -{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, {RA, RS, MB}}, | |
7292 | -{"rlwinm.", M(21,1), M_MASK, PPCCOM, {RA, RS, SH, MBE, ME}}, | |
7293 | -{"rlinm.", M(21,1), M_MASK, PWRCOM, {RA, RS, SH, MBE, ME}}, | |
7294 | - | |
7295 | -{"rlmi", M(22,0), M_MASK, M601, {RA, RS, RB, MBE, ME}}, | |
7296 | -{"be", B(22,0,0), B_MASK, BOOKE64, {LI}}, | |
7297 | -{"bel", B(22,0,1), B_MASK, BOOKE64, {LI}}, | |
7298 | -{"rlmi.", M(22,1), M_MASK, M601, {RA, RS, RB, MBE, ME}}, | |
7299 | -{"bea", B(22,1,0), B_MASK, BOOKE64, {LIA}}, | |
7300 | -{"bela", B(22,1,1), B_MASK, BOOKE64, {LIA}}, | |
7301 | - | |
7302 | -{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, {RA, RS, RB}}, | |
7303 | -{"rlwnm", M(23,0), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}}, | |
7304 | -{"rlnm", M(23,0), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}}, | |
7305 | -{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, {RA, RS, RB}}, | |
7306 | -{"rlwnm.", M(23,1), M_MASK, PPCCOM, {RA, RS, RB, MBE, ME}}, | |
7307 | -{"rlnm.", M(23,1), M_MASK, PWRCOM, {RA, RS, RB, MBE, ME}}, | |
7308 | - | |
7309 | -{"nop", OP(24), 0xffffffff, PPCCOM, {0}}, | |
7310 | -{"ori", OP(24), OP_MASK, PPCCOM, {RA, RS, UI}}, | |
7311 | -{"oril", OP(24), OP_MASK, PWRCOM, {RA, RS, UI}}, | |
7312 | - | |
7313 | -{"oris", OP(25), OP_MASK, PPCCOM, {RA, RS, UI}}, | |
7314 | -{"oriu", OP(25), OP_MASK, PWRCOM, {RA, RS, UI}}, | |
7315 | - | |
7316 | -{"xori", OP(26), OP_MASK, PPCCOM, {RA, RS, UI}}, | |
7317 | -{"xoril", OP(26), OP_MASK, PWRCOM, {RA, RS, UI}}, | |
7318 | - | |
7319 | -{"xoris", OP(27), OP_MASK, PPCCOM, {RA, RS, UI}}, | |
7320 | -{"xoriu", OP(27), OP_MASK, PWRCOM, {RA, RS, UI}}, | |
7321 | - | |
7322 | -{"andi.", OP(28), OP_MASK, PPCCOM, {RA, RS, UI}}, | |
7323 | -{"andil.", OP(28), OP_MASK, PWRCOM, {RA, RS, UI}}, | |
7324 | - | |
7325 | -{"andis.", OP(29), OP_MASK, PPCCOM, {RA, RS, UI}}, | |
7326 | -{"andiu.", OP(29), OP_MASK, PWRCOM, {RA, RS, UI}}, | |
7327 | - | |
7328 | -{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, {RA, RS, SH6}}, | |
7329 | -{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, {RA, RS, MB6}}, | |
7330 | -{"rldicl", MD(30,0,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, | |
7331 | -{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, {RA, RS, SH6}}, | |
7332 | -{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, {RA, RS, MB6}}, | |
7333 | -{"rldicl.", MD(30,0,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, | |
7334 | - | |
7335 | -{"rldicr", MD(30,1,0), MD_MASK, PPC64, {RA, RS, SH6, ME6}}, | |
7336 | -{"rldicr.", MD(30,1,1), MD_MASK, PPC64, {RA, RS, SH6, ME6}}, | |
7337 | - | |
7338 | -{"rldic", MD(30,2,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, | |
7339 | -{"rldic.", MD(30,2,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, | |
7340 | - | |
7341 | -{"rldimi", MD(30,3,0), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, | |
7342 | -{"rldimi.", MD(30,3,1), MD_MASK, PPC64, {RA, RS, SH6, MB6}}, | |
7343 | - | |
7344 | -{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, {RA, RS, RB}}, | |
7345 | -{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, {RA, RS, RB, MB6}}, | |
7346 | -{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, {RA, RS, RB}}, | |
7347 | -{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, {RA, RS, RB, MB6}}, | |
7348 | - | |
7349 | -{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, {RA, RS, RB, ME6}}, | |
7350 | -{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, {RA, RS, RB, ME6}}, | |
7351 | - | |
7352 | -{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}}, | |
7353 | -{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, {OBF, RA, RB}}, | |
7354 | -{"cmp", X(31,0), XCMP_MASK, PPC, {BF, L, RA, RB}}, | |
7355 | -{"cmp", X(31,0), XCMPL_MASK, PWRCOM, {BF, RA, RB}}, | |
7356 | - | |
7357 | -{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, {RA, RB}}, | |
7358 | -{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, {RA, RB}}, | |
7359 | -{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, {RA, RB}}, | |
7360 | -{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, {RA, RB}}, | |
7361 | -{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, {RA, RB}}, | |
7362 | -{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, {RA, RB}}, | |
7363 | -{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, {RA, RB}}, | |
7364 | -{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, {RA, RB}}, | |
7365 | -{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, {RA, RB}}, | |
7366 | -{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, {RA, RB}}, | |
7367 | -{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, {RA, RB}}, | |
7368 | -{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, {RA, RB}}, | |
7369 | -{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, {RA, RB}}, | |
7370 | -{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, {RA, RB}}, | |
7371 | -{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, {RA, RB}}, | |
7372 | -{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, {RA, RB}}, | |
7373 | -{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, {RA, RB}}, | |
7374 | -{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, {RA, RB}}, | |
7375 | -{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, {RA, RB}}, | |
7376 | -{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, {RA, RB}}, | |
7377 | -{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, {RA, RB}}, | |
7378 | -{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, {RA, RB}}, | |
7379 | -{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, {RA, RB}}, | |
7380 | -{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, {RA, RB}}, | |
7381 | -{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, {RA, RB}}, | |
7382 | -{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, {RA, RB}}, | |
7383 | -{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, {RA, RB}}, | |
7384 | -{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, {RA, RB}}, | |
7385 | -{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, {0}}, | |
7386 | -{"tw", X(31,4), X_MASK, PPCCOM, {TO, RA, RB}}, | |
7387 | -{"t", X(31,4), X_MASK, PWRCOM, {TO, RA, RB}}, | |
7388 | - | |
7389 | -{"lvsl", X(31,6), X_MASK, PPCVEC, {VD, RA, RB}}, | |
7390 | -{"lvebx", X(31,7), X_MASK, PPCVEC, {VD, RA, RB}}, | |
7391 | -{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
7392 | - | |
7393 | -{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7394 | -{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7395 | -{"subc", XO(31,8,0,0), XO_MASK, PPC, {RT, RB, RA}}, | |
7396 | -{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7397 | -{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7398 | -{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, {RT, RB, RA}}, | |
7399 | - | |
7400 | -{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, {RT, RA, RB}}, | |
7401 | -{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, {RT, RA, RB}}, | |
7402 | - | |
7403 | -{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7404 | -{"a", XO(31,10,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7405 | -{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7406 | -{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7407 | - | |
7408 | -{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, {RT, RA, RB}}, | |
7409 | -{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, {RT, RA, RB}}, | |
7410 | - | |
7411 | -{"isellt", X(31,15), X_MASK, PPCISEL, {RT, RA, RB}}, | |
7412 | - | |
7413 | -{"mfcr", XFXM(31,19,0,0), XRARB_MASK, NOPOWER4|COM, {RT}}, | |
7414 | -{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, {RT, FXM4}}, | |
7415 | -{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, {RT, FXM}}, | |
7416 | - | |
7417 | -{"lwarx", X(31,20), XEH_MASK, PPC, {RT, RA0, RB, EH}}, | |
7418 | - | |
7419 | -{"ldx", X(31,21), X_MASK, PPC64, {RT, RA0, RB}}, | |
7420 | - | |
7421 | -{"icbt", X(31,22), X_MASK, BOOKE|PPCE300, {CT, RA, RB}}, | |
7422 | - | |
7423 | -{"lwzx", X(31,23), X_MASK, PPCCOM, {RT, RA0, RB}}, | |
7424 | -{"lx", X(31,23), X_MASK, PWRCOM, {RT, RA, RB}}, | |
7425 | - | |
7426 | -{"slw", XRC(31,24,0), X_MASK, PPCCOM, {RA, RS, RB}}, | |
7427 | -{"sl", XRC(31,24,0), X_MASK, PWRCOM, {RA, RS, RB}}, | |
7428 | -{"slw.", XRC(31,24,1), X_MASK, PPCCOM, {RA, RS, RB}}, | |
7429 | -{"sl.", XRC(31,24,1), X_MASK, PWRCOM, {RA, RS, RB}}, | |
7430 | - | |
7431 | -{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, {RA, RS}}, | |
7432 | -{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, {RA, RS}}, | |
7433 | -{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, {RA, RS}}, | |
7434 | -{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, {RA, RS}}, | |
7435 | - | |
7436 | -{"sld", XRC(31,27,0), X_MASK, PPC64, {RA, RS, RB}}, | |
7437 | -{"sld.", XRC(31,27,1), X_MASK, PPC64, {RA, RS, RB}}, | |
7438 | - | |
7439 | -{"and", XRC(31,28,0), X_MASK, COM, {RA, RS, RB}}, | |
7440 | -{"and.", XRC(31,28,1), X_MASK, COM, {RA, RS, RB}}, | |
7441 | - | |
7442 | -{"maskg", XRC(31,29,0), X_MASK, M601, {RA, RS, RB}}, | |
7443 | -{"maskg.", XRC(31,29,1), X_MASK, M601, {RA, RS, RB}}, | |
7444 | - | |
7445 | -{"ldepx", X(31,29), X_MASK, E500MC, {RT, RA, RB}}, | |
7446 | - | |
7447 | -{"icbte", X(31,30), X_MASK, BOOKE64, {CT, RA, RB}}, | |
7448 | - | |
7449 | -{"lwzxe", X(31,31), X_MASK, BOOKE64, {RT, RA0, RB}}, | |
7450 | -{"lwepx", X(31,31), X_MASK, E500MC, {RT, RA, RB}}, | |
7451 | - | |
7452 | -{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, {OBF, RA, RB}}, | |
7453 | -{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, {OBF, RA, RB}}, | |
7454 | -{"cmpl", X(31,32), XCMP_MASK, PPC, {BF, L, RA, RB}}, | |
7455 | -{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, {BF, RA, RB}}, | |
7456 | - | |
7457 | -{"lvsr", X(31,38), X_MASK, PPCVEC, {VD, RA, RB}}, | |
7458 | -{"lvehx", X(31,39), X_MASK, PPCVEC, {VD, RA, RB}}, | |
7459 | -{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
7460 | - | |
7461 | -{"iselgt", X(31,47), X_MASK, PPCISEL, {RT, RA, RB}}, | |
7462 | - | |
7463 | -{"lvewx", X(31,71), X_MASK, PPCVEC, {VD, RA, RB}}, | |
7464 | - | |
7465 | -{"iseleq", X(31,79), X_MASK, PPCISEL, {RT, RA, RB}}, | |
7466 | - | |
7467 | -{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, {RT, RA, RB, CRB}}, | |
7468 | - | |
7469 | -{"subf", XO(31,40,0,0), XO_MASK, PPC, {RT, RA, RB}}, | |
7470 | -{"sub", XO(31,40,0,0), XO_MASK, PPC, {RT, RB, RA}}, | |
7471 | -{"subf.", XO(31,40,0,1), XO_MASK, PPC, {RT, RA, RB}}, | |
7472 | -{"sub.", XO(31,40,0,1), XO_MASK, PPC, {RT, RB, RA}}, | |
7473 | - | |
7474 | -{"ldux", X(31,53), X_MASK, PPC64, {RT, RAL, RB}}, | |
7475 | - | |
7476 | -{"dcbst", X(31,54), XRT_MASK, PPC, {RA, RB}}, | |
7477 | - | |
7478 | -{"lwzux", X(31,55), X_MASK, PPCCOM, {RT, RAL, RB}}, | |
7479 | -{"lux", X(31,55), X_MASK, PWRCOM, {RT, RA, RB}}, | |
7480 | - | |
7481 | -{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, {RA, RS}}, | |
7482 | -{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, {RA, RS}}, | |
7483 | - | |
7484 | -{"andc", XRC(31,60,0), X_MASK, COM, {RA, RS, RB}}, | |
7485 | -{"andc.", XRC(31,60,1), X_MASK, COM, {RA, RS, RB}}, | |
7486 | - | |
7487 | -{"dcbste", X(31,62), XRT_MASK, BOOKE64, {RA, RB}}, | |
7488 | - | |
7489 | -{"wait", X(31,62), 0xffffffff, E500MC, {0}}, | |
7490 | - | |
7491 | -{"lwzuxe", X(31,63), X_MASK, BOOKE64, {RT, RAL, RB}}, | |
7492 | - | |
7493 | -{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, {RA, RB}}, | |
7494 | - | |
7495 | -{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, {RA, RB}}, | |
7496 | -{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, {RA, RB}}, | |
7497 | -{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, {RA, RB}}, | |
7498 | -{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, {RA, RB}}, | |
7499 | -{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, {RA, RB}}, | |
7500 | -{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, {RA, RB}}, | |
7501 | -{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, {RA, RB}}, | |
7502 | -{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, {RA, RB}}, | |
7503 | -{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, {RA, RB}}, | |
7504 | -{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, {RA, RB}}, | |
7505 | -{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, {RA, RB}}, | |
7506 | -{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, {RA, RB}}, | |
7507 | -{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, {RA, RB}}, | |
7508 | -{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, {RA, RB}}, | |
7509 | -{"td", X(31,68), X_MASK, PPC64, {TO, RA, RB}}, | |
7510 | - | |
7511 | -{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
7512 | -{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, {RT, RA, RB}}, | |
7513 | -{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, {RT, RA, RB}}, | |
7514 | - | |
7515 | -{"mulhw", XO(31,75,0,0), XO_MASK, PPC, {RT, RA, RB}}, | |
7516 | -{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, {RT, RA, RB}}, | |
7517 | - | |
7518 | -{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, {RA, RS, RB}}, | |
7519 | -{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, {RA, RS, RB}}, | |
7520 | - | |
7521 | -{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, {SR, RS}}, | |
7522 | - | |
7523 | -{"mfmsr", X(31,83), XRARB_MASK, COM, {RT}}, | |
7524 | - | |
7525 | -{"ldarx", X(31,84), XEH_MASK, PPC64, {RT, RA0, RB, EH}}, | |
7526 | - | |
7527 | -{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, {RA, RB}}, | |
7528 | -{"dcbf", X(31,86), XLRT_MASK, PPC, {RA, RB, L}}, | |
7529 | - | |
7530 | -{"lbzx", X(31,87), X_MASK, COM, {RT, RA0, RB}}, | |
7531 | - | |
7532 | -{"dcbfe", X(31,94), XRT_MASK, BOOKE64, {RA, RB}}, | |
7533 | - | |
7534 | -{"lbzxe", X(31,95), X_MASK, BOOKE64, {RT, RA0, RB}}, | |
7535 | -{"lbepx", X(31,95), X_MASK, E500MC, {RT, RA, RB}}, | |
7536 | - | |
7537 | -{"lvx", X(31,103), X_MASK, PPCVEC, {VD, RA, RB}}, | |
7538 | -{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
7539 | - | |
7540 | -{"neg", XO(31,104,0,0), XORB_MASK, COM, {RT, RA}}, | |
7541 | -{"neg.", XO(31,104,0,1), XORB_MASK, COM, {RT, RA}}, | |
7542 | - | |
7543 | -{"mul", XO(31,107,0,0), XO_MASK, M601, {RT, RA, RB}}, | |
7544 | -{"mul.", XO(31,107,0,1), XO_MASK, M601, {RT, RA, RB}}, | |
7545 | - | |
7546 | -{"mtsrdin", X(31,114), XRA_MASK, PPC64, {RS, RB}}, | |
7547 | - | |
7548 | -{"clf", X(31,118), XTO_MASK, POWER, {RA, RB}}, | |
7549 | - | |
7550 | -{"lbzux", X(31,119), X_MASK, COM, {RT, RAL, RB}}, | |
7551 | - | |
7552 | -{"popcntb", X(31,122), XRB_MASK, POWER5, {RA, RS}}, | |
7553 | - | |
7554 | -{"not", XRC(31,124,0), X_MASK, COM, {RA, RS, RBS}}, | |
7555 | -{"nor", XRC(31,124,0), X_MASK, COM, {RA, RS, RB}}, | |
7556 | -{"not.", XRC(31,124,1), X_MASK, COM, {RA, RS, RBS}}, | |
7557 | -{"nor.", XRC(31,124,1), X_MASK, COM, {RA, RS, RB}}, | |
7558 | - | |
7559 | -{"lwarxe", X(31,126), X_MASK, BOOKE64, {RT, RA0, RB}}, | |
7560 | - | |
7561 | -{"lbzuxe", X(31,127), X_MASK, BOOKE64, {RT, RAL, RB}}, | |
7562 | - | |
7563 | -{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, {RA, RB}}, | |
7564 | - | |
7565 | -{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, {RS}}, | |
7566 | - | |
7567 | -{"dcbtstls", X(31,134), X_MASK, PPCCHLK, {CT, RA, RB}}, | |
7568 | - | |
7569 | -{"stvebx", X(31,135), X_MASK, PPCVEC, {VS, RA, RB}}, | |
7570 | -{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
7571 | - | |
7572 | -{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7573 | -{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7574 | -{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7575 | -{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7576 | - | |
7577 | -{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7578 | -{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7579 | -{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7580 | -{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7581 | - | |
7582 | -{"dcbtstlse", X(31,142), X_MASK, PPCCHLK64, {CT, RA, RB}}, | |
7583 | - | |
7584 | -{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, {RS}}, | |
7585 | -{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, {FXM, RS}}, | |
7586 | -{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, {FXM, RS}}, | |
7587 | - | |
7588 | -{"mtmsr", X(31,146), XRLARB_MASK, COM, {RS, A_L}}, | |
7589 | - | |
7590 | -{"stdx", X(31,149), X_MASK, PPC64, {RS, RA0, RB}}, | |
7591 | - | |
7592 | -{"stwcx.", XRC(31,150,1), X_MASK, PPC, {RS, RA0, RB}}, | |
7593 | - | |
7594 | -{"stwx", X(31,151), X_MASK, PPCCOM, {RS, RA0, RB}}, | |
7595 | -{"stx", X(31,151), X_MASK, PWRCOM, {RS, RA, RB}}, | |
7596 | - | |
7597 | -{"slq", XRC(31,152,0), X_MASK, M601, {RA, RS, RB}}, | |
7598 | -{"slq.", XRC(31,152,1), X_MASK, M601, {RA, RS, RB}}, | |
7599 | - | |
7600 | -{"sle", XRC(31,153,0), X_MASK, M601, {RA, RS, RB}}, | |
7601 | -{"sle.", XRC(31,153,1), X_MASK, M601, {RA, RS, RB}}, | |
7602 | - | |
7603 | -{"prtyw", X(31,154), XRB_MASK, POWER6, {RA, RS}}, | |
7604 | - | |
7605 | -{"stdepx", X(31,157), X_MASK, E500MC, {RS, RA, RB}}, | |
7606 | - | |
7607 | -{"stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, {RS, RA0, RB}}, | |
7608 | - | |
7609 | -{"stwxe", X(31,159), X_MASK, BOOKE64, {RS, RA0, RB}}, | |
7610 | -{"stwepx", X(31,159), X_MASK, E500MC, {RS, RA, RB}}, | |
7611 | - | |
7612 | -{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, {E}}, | |
7613 | - | |
7614 | -{"dcbtls", X(31,166), X_MASK, PPCCHLK, {CT, RA, RB}}, | |
7615 | - | |
7616 | -{"stvehx", X(31,167), X_MASK, PPCVEC, {VS, RA, RB}}, | |
7617 | -{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
7618 | - | |
7619 | -{"dcbtlse", X(31,174), X_MASK, PPCCHLK64, {CT, RA, RB}}, | |
7620 | - | |
7621 | -{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, {RS, A_L}}, | |
7622 | - | |
7623 | -{"stdux", X(31,181), X_MASK, PPC64, {RS, RAS, RB}}, | |
7624 | - | |
7625 | -{"stwux", X(31,183), X_MASK, PPCCOM, {RS, RAS, RB}}, | |
7626 | -{"stux", X(31,183), X_MASK, PWRCOM, {RS, RA0, RB}}, | |
7627 | - | |
7628 | -{"sliq", XRC(31,184,0), X_MASK, M601, {RA, RS, SH}}, | |
7629 | -{"sliq.", XRC(31,184,1), X_MASK, M601, {RA, RS, SH}}, | |
7630 | - | |
7631 | -{"prtyd", X(31,186), XRB_MASK, POWER6, {RA, RS}}, | |
7632 | - | |
7633 | -{"stwuxe", X(31,191), X_MASK, BOOKE64, {RS, RAS, RB}}, | |
7634 | - | |
7635 | -{"stvewx", X(31,199), X_MASK, PPCVEC, {VS, RA, RB}}, | |
7636 | -{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
7637 | - | |
7638 | -{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, {RT, RA}}, | |
7639 | -{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, {RT, RA}}, | |
7640 | -{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, {RT, RA}}, | |
7641 | -{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, {RT, RA}}, | |
7642 | - | |
7643 | -{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, {RT, RA}}, | |
7644 | -{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, {RT, RA}}, | |
7645 | -{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, {RT, RA}}, | |
7646 | -{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, {RT, RA}}, | |
7647 | - | |
7648 | -{"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, {RB}}, | |
7649 | - | |
7650 | -{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, {SR, RS}}, | |
7651 | - | |
7652 | -{"stdcx.", XRC(31,214,1), X_MASK, PPC64, {RS, RA0, RB}}, | |
7653 | - | |
7654 | -{"stbx", X(31,215), X_MASK, COM, {RS, RA0, RB}}, | |
7655 | - | |
7656 | -{"sllq", XRC(31,216,0), X_MASK, M601, {RA, RS, RB}}, | |
7657 | -{"sllq.", XRC(31,216,1), X_MASK, M601, {RA, RS, RB}}, | |
7658 | - | |
7659 | -{"sleq", XRC(31,217,0), X_MASK, M601, {RA, RS, RB}}, | |
7660 | -{"sleq.", XRC(31,217,1), X_MASK, M601, {RA, RS, RB}}, | |
7661 | - | |
7662 | -{"stbxe", X(31,223), X_MASK, BOOKE64, {RS, RA0, RB}}, | |
7663 | -{"stbepx", X(31,223), X_MASK, E500MC, {RS, RA, RB}}, | |
7664 | - | |
7665 | -{"icblc", X(31,230), X_MASK, PPCCHLK, {CT, RA, RB}}, | |
7666 | - | |
7667 | -{"stvx", X(31,231), X_MASK, PPCVEC, {VS, RA, RB}}, | |
7668 | -{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
7669 | - | |
7670 | -{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, {RT, RA}}, | |
7671 | -{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, {RT, RA}}, | |
7672 | -{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, {RT, RA}}, | |
7673 | -{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, {RT, RA}}, | |
7674 | - | |
7675 | -{"mulld", XO(31,233,0,0), XO_MASK, PPC64, {RT, RA, RB}}, | |
7676 | -{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, {RT, RA, RB}}, | |
7677 | - | |
7678 | -{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, {RT, RA}}, | |
7679 | -{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, {RT, RA}}, | |
7680 | -{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, {RT, RA}}, | |
7681 | -{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, {RT, RA}}, | |
7682 | - | |
7683 | -{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7684 | -{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7685 | -{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7686 | -{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7687 | - | |
7688 | -{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, {RB}}, | |
7689 | -{"icblce", X(31,238), X_MASK, PPCCHLK64, {CT, RA, RB}}, | |
7690 | -{"mtsrin", X(31,242), XRA_MASK, PPC32, {RS, RB}}, | |
7691 | -{"mtsri", X(31,242), XRA_MASK, POWER32, {RS, RB}}, | |
7692 | - | |
7693 | -{"dcbtst", X(31,246), X_MASK, PPC, {CT, RA, RB}}, | |
7694 | - | |
7695 | -{"stbux", X(31,247), X_MASK, COM, {RS, RAS, RB}}, | |
7696 | - | |
7697 | -{"slliq", XRC(31,248,0), X_MASK, M601, {RA, RS, SH}}, | |
7698 | -{"slliq.", XRC(31,248,1), X_MASK, M601, {RA, RS, SH}}, | |
7699 | - | |
7700 | -{"dcbtste", X(31,253), X_MASK, BOOKE64, {CT, RA, RB}}, | |
7701 | - | |
7702 | -{"stbuxe", X(31,255), X_MASK, BOOKE64, {RS, RAS, RB}}, | |
7703 | - | |
7704 | -{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, {RT, RA, RB}}, | |
7705 | - | |
7706 | -{"mfdcrx", X(31,259), X_MASK, BOOKE, {RS, RA}}, | |
7707 | - | |
7708 | -{"icbt", X(31,262), XRT_MASK, PPC403, {RA, RB}}, | |
7709 | - | |
7710 | -{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
7711 | -{"doz", XO(31,264,0,0), XO_MASK, M601, {RT, RA, RB}}, | |
7712 | -{"doz.", XO(31,264,0,1), XO_MASK, M601, {RT, RA, RB}}, | |
7713 | - | |
7714 | -{"add", XO(31,266,0,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7715 | -{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7716 | -{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
7717 | -{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
7718 | - | |
7719 | -{"ehpriv", X(31,270), 0xffffffff, E500MC, {0}}, | |
7720 | - | |
7721 | -{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, {RB, L}}, | |
7722 | - | |
7723 | -{"mfapidi", X(31,275), X_MASK, BOOKE, {RT, RA}}, | |
7724 | - | |
7725 | -{"lscbx", XRC(31,277,0), X_MASK, M601, {RT, RA, RB}}, | |
7726 | -{"lscbx.", XRC(31,277,1), X_MASK, M601, {RT, RA, RB}}, | |
7727 | - | |
7728 | -{"dcbt", X(31,278), X_MASK, PPC, {CT, RA, RB}}, | |
7729 | - | |
7730 | -{"lhzx", X(31,279), X_MASK, COM, {RT, RA0, RB}}, | |
7731 | - | |
7732 | -{"eqv", XRC(31,284,0), X_MASK, COM, {RA, RS, RB}}, | |
7733 | -{"eqv.", XRC(31,284,1), X_MASK, COM, {RA, RS, RB}}, | |
7734 | - | |
7735 | -{"dcbte", X(31,286), X_MASK, BOOKE64, {CT, RA, RB}}, | |
7736 | - | |
7737 | -{"lhzxe", X(31,287), X_MASK, BOOKE64, {RT, RA0, RB}}, | |
7738 | -{"lhepx", X(31,287), X_MASK, E500MC, {RT, RA, RB}}, | |
7739 | - | |
7740 | -{"mfdcrux", X(31,291), X_MASK, PPC464, {RS, RA}}, | |
7741 | - | |
7742 | -{"tlbie", X(31,306), XRTLRA_MASK, PPC, {RB, L}}, | |
7743 | -{"tlbi", X(31,306), XRT_MASK, POWER, {RA0, RB}}, | |
7744 | - | |
7745 | -{"eciwx", X(31,310), X_MASK, PPC, {RT, RA, RB}}, | |
7746 | - | |
7747 | -{"lhzux", X(31,311), X_MASK, COM, {RT, RAL, RB}}, | |
7748 | - | |
7749 | -{"xor", XRC(31,316,0), X_MASK, COM, {RA, RS, RB}}, | |
7750 | -{"xor.", XRC(31,316,1), X_MASK, COM, {RA, RS, RB}}, | |
7751 | - | |
7752 | -{"lhzuxe", X(31,319), X_MASK, BOOKE64, {RT, RAL, RB}}, | |
7753 | - | |
7754 | -{"dcbtep", XRT(31,319,0), X_MASK, E500MC, {RT, RA, RB}}, | |
7755 | - | |
7756 | -{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, {RT}}, | |
7757 | -{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, {RT}}, | |
7758 | -{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, {RT}}, | |
7759 | -{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, {RT}}, | |
7760 | -{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, {RT}}, | |
7761 | -{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, {RT}}, | |
7762 | -{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, {RT}}, | |
7763 | -{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, {RT}}, | |
7764 | -{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, {RT}}, | |
7765 | -{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, {RT}}, | |
7766 | -{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, {RT}}, | |
7767 | -{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, {RT}}, | |
7768 | -{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, {RT}}, | |
7769 | -{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, {RT}}, | |
7770 | -{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, {RT}}, | |
7771 | -{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, {RT}}, | |
7772 | -{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, {RT}}, | |
7773 | -{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, {RT}}, | |
7774 | -{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, {RT}}, | |
7775 | -{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, {RT}}, | |
7776 | -{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, {RT}}, | |
7777 | -{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, {RT}}, | |
7778 | -{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, {RT}}, | |
7779 | -{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, {RT}}, | |
7780 | -{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, {RT}}, | |
7781 | -{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, {RT}}, | |
7782 | -{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, {RT}}, | |
7783 | -{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, {RT}}, | |
7784 | -{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, {RT}}, | |
7785 | -{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, {RT}}, | |
7786 | -{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, {RT}}, | |
7787 | -{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, {RT}}, | |
7788 | -{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, {RT}}, | |
7789 | -{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, {RT}}, | |
7790 | -{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, {RT, SPR}}, | |
7791 | - | |
7792 | -{"div", XO(31,331,0,0), XO_MASK, M601, {RT, RA, RB}}, | |
7793 | -{"div.", XO(31,331,0,1), XO_MASK, M601, {RT, RA, RB}}, | |
7794 | - | |
7795 | -{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, {RT, PMR}}, | |
7796 | - | |
7797 | -{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, {RT}}, | |
7798 | -{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, {RT}}, | |
7799 | -{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, {RT}}, | |
7800 | -{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, {RT}}, | |
7801 | -{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, {RT}}, | |
7802 | -{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, {RT}}, | |
7803 | -{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, {RT}}, | |
7804 | -{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, {RT}}, | |
7805 | -{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, {RT}}, | |
7806 | -{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, {RT}}, | |
7807 | -{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, {RT}}, | |
7808 | -{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, {RT}}, | |
7809 | -{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, {RT}}, | |
7810 | -{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, {RT}}, | |
7811 | -{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, {RT}}, | |
7812 | -{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, {RT}}, | |
7813 | -{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, {RT}}, | |
7814 | -{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, {RT}}, | |
7815 | -{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, {RT}}, | |
7816 | -{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, {RT}}, | |
7817 | -{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, {RT}}, | |
7818 | -{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, {RT}}, | |
7819 | -{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, {RT}}, | |
7820 | -{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, {RT}}, | |
7821 | -{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, {RT}}, | |
7822 | -{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, {RT}}, | |
7823 | -{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, {RT}}, | |
7824 | -{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, {RT}}, | |
7825 | -{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, {RT}}, | |
7826 | -{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, {RT}}, | |
7827 | -{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, {RT}}, | |
7828 | -{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, {RT}}, | |
7829 | -{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, {RT}}, | |
7830 | -{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, {RT}}, | |
7831 | -{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, {RT}}, | |
7832 | -{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, {RT}}, | |
7833 | -{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, {RT}}, | |
7834 | -{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, {RT}}, | |
7835 | -{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, {RT}}, | |
7836 | -{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, {RT}}, | |
7837 | -{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, {RT, SPRG}}, | |
7838 | -{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, {RT}}, | |
7839 | -{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, {RT}}, | |
7840 | -{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, {RT}}, | |
7841 | -{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, {RT}}, | |
7842 | -{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}}, | |
7843 | -{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, {RT}}, | |
7844 | -{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, {RT}}, | |
7845 | -{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, {RT}}, | |
7846 | -{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, {RT}}, | |
7847 | -{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, {RT}}, | |
7848 | -{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, {RT}}, | |
7849 | -{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, {RT}}, | |
7850 | -{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, {RT}}, | |
7851 | -{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, {RT}}, | |
7852 | -{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, {RT}}, | |
7853 | -{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, {RT}}, | |
7854 | -{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, {RT}}, | |
7855 | -{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, {RT}}, | |
7856 | -{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, {RT}}, | |
7857 | -{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, {RT}}, | |
7858 | -{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, {RT}}, | |
7859 | -{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, {RT}}, | |
7860 | -{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, {RT}}, | |
7861 | -{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, {RT}}, | |
7862 | -{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, {RT}}, | |
7863 | -{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, {RT}}, | |
7864 | -{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, {RT}}, | |
7865 | -{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, {RT}}, | |
7866 | -{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, {RT}}, | |
7867 | -{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, {RT}}, | |
7868 | -{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, {RT}}, | |
7869 | -{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, {RT}}, | |
7870 | -{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, {RT}}, | |
7871 | -{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, {RT}}, | |
7872 | -{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, {RT}}, | |
7873 | -{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, {RT}}, | |
7874 | -{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, {RT}}, | |
7875 | -{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, {RT}}, | |
7876 | -{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, {RT}}, | |
7877 | -{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, {RT}}, | |
7878 | -{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, {RT}}, | |
7879 | -{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, {RT}}, | |
7880 | -{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, {RT}}, | |
7881 | -{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, {RT}}, | |
7882 | -{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, {RT}}, | |
7883 | -{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, {RT}}, | |
7884 | -{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, {RT}}, | |
7885 | -{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, {RT}}, | |
7886 | -{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, {RT}}, | |
7887 | -{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, | |
7888 | -{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, {RT}}, | |
7889 | -{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, | |
7890 | -{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, {RT}}, | |
7891 | -{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, {RT}}, | |
7892 | -{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, | |
7893 | -{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, {RT, SPRBAT}}, | |
7894 | -{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, {RT}}, | |
7895 | -{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, {RT}}, | |
7896 | -{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, {RT}}, | |
7897 | -{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, {RT}}, | |
7898 | -{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, {RT}}, | |
7899 | -{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, {RT}}, | |
7900 | -{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, {RT}}, | |
7901 | -{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, {RT}}, | |
7902 | -{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, {RT}}, | |
7903 | -{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, {RT}}, | |
7904 | -{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, {RT}}, | |
7905 | -{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, {RT}}, | |
7906 | -{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, {RT}}, | |
7907 | -{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, {RT}}, | |
7908 | -{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, {RT}}, | |
7909 | -{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, {RT}}, | |
7910 | -{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, {RT}}, | |
7911 | -{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, {RT}}, | |
7912 | -{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, {RT}}, | |
7913 | -{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, {RT}}, | |
7914 | -{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, {RT}}, | |
7915 | -{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, {RT}}, | |
7916 | -{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, {RT}}, | |
7917 | -{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, {RT}}, | |
7918 | -{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, {RT}}, | |
7919 | -{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, {RT}}, | |
7920 | -{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, {RT}}, | |
7921 | -{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, {RT}}, | |
7922 | -{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, {RT}}, | |
7923 | -{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, {RT}}, | |
7924 | -{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, {RT}}, | |
7925 | -{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, {RT}}, | |
7926 | -{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, {RT}}, | |
7927 | -{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, {RT}}, | |
7928 | -{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, {RT}}, | |
7929 | -{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, {RT}}, | |
7930 | -{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, {RT}}, | |
7931 | -{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, {RT}}, | |
7932 | -{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, {RT}}, | |
7933 | -{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, {RT}}, | |
7934 | -{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, {RT}}, | |
7935 | -{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, {RT}}, | |
7936 | -{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, {RT}}, | |
7937 | -{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, {RT}}, | |
7938 | -{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, {RT}}, | |
7939 | -{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, {RT}}, | |
7940 | -{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, {RT}}, | |
7941 | -{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, {RT}}, | |
7942 | -{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, {RT}}, | |
7943 | -{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, {RT}}, | |
7944 | -{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, {RT}}, | |
7945 | -{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, {RT}}, | |
7946 | -{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, {RT}}, | |
7947 | -{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, {RT}}, | |
7948 | -{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, {RT}}, | |
7949 | -{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, {RT}}, | |
7950 | -{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, {RT}}, | |
7951 | -{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, {RT}}, | |
7952 | -{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, {RT}}, | |
7953 | -{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, {RT}}, | |
7954 | -{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, {RT}}, | |
7955 | -{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, {RT}}, | |
7956 | -{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, {RT}}, | |
7957 | -{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, {RT}}, | |
7958 | -{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, {RT}}, | |
7959 | -{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, {RT}}, | |
7960 | -{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, {RT}}, | |
7961 | -{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, {RT}}, | |
7962 | -{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, {RT}}, | |
7963 | -{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, {RT}}, | |
7964 | -{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, {RT}}, | |
7965 | -{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, {RT}}, | |
7966 | -{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, {RT}}, | |
7967 | -{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, {RT}}, | |
7968 | -{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, {RT}}, | |
7969 | -{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, {RT}}, | |
7970 | -{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, {RT}}, | |
7971 | -{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, {RT}}, | |
7972 | -{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, {RT}}, | |
7973 | -{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, {RT}}, | |
7974 | -{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, {RT}}, | |
7975 | -{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, {RT}}, | |
7976 | -{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, {RT}}, | |
7977 | -{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, {RT}}, | |
7978 | -{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, {RT}}, | |
7979 | -{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, {RT}}, | |
7980 | -{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, {RT}}, | |
7981 | -{"mfspr", X(31,339), X_MASK, COM, {RT, SPR}}, | |
7982 | - | |
7983 | -{"lwax", X(31,341), X_MASK, PPC64, {RT, RA0, RB}}, | |
7984 | - | |
7985 | -{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, | |
7986 | - | |
7987 | -{"lhax", X(31,343), X_MASK, COM, {RT, RA0, RB}}, | |
7988 | - | |
7989 | -{"lhaxe", X(31,351), X_MASK, BOOKE64, {RT, RA0, RB}}, | |
7990 | - | |
7991 | -{"lvxl", X(31,359), X_MASK, PPCVEC, {VD, RA, RB}}, | |
7992 | - | |
7993 | -{"abs", XO(31,360,0,0), XORB_MASK, M601, {RT, RA}}, | |
7994 | -{"abs.", XO(31,360,0,1), XORB_MASK, M601, {RT, RA}}, | |
7995 | - | |
7996 | -{"divs", XO(31,363,0,0), XO_MASK, M601, {RT, RA, RB}}, | |
7997 | -{"divs.", XO(31,363,0,1), XO_MASK, M601, {RT, RA, RB}}, | |
7998 | - | |
7999 | -{"tlbia", X(31,370), 0xffffffff, PPC, {0}}, | |
8000 | - | |
8001 | -{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, {RT}}, | |
8002 | -{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, {RT}}, | |
8003 | -{"mftb", X(31,371), X_MASK, CLASSIC, {RT, TBR}}, | |
8004 | - | |
8005 | -{"lwaux", X(31,373), X_MASK, PPC64, {RT, RAL, RB}}, | |
8006 | - | |
8007 | -{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, | |
8008 | - | |
8009 | -{"lhaux", X(31,375), X_MASK, COM, {RT, RAL, RB}}, | |
8010 | - | |
8011 | -{"lhauxe", X(31,383), X_MASK, BOOKE64, {RT, RAL, RB}}, | |
8012 | - | |
8013 | -{"mtdcrx", X(31,387), X_MASK, BOOKE, {RA, RS}}, | |
8014 | - | |
8015 | -{"dcblc", X(31,390), X_MASK, PPCCHLK, {CT, RA, RB}}, | |
8016 | -{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8017 | - | |
8018 | -{"subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, {RT, RA, RB}}, | |
8019 | - | |
8020 | -{"adde64", XO(31,394,0,0), XO_MASK, BOOKE64, {RT, RA, RB}}, | |
8021 | - | |
8022 | -{"dcblce", X(31,398), X_MASK, PPCCHLK64, {CT, RA, RB}}, | |
8023 | - | |
8024 | -{"slbmte", X(31,402), XRA_MASK, PPC64, {RS, RB}}, | |
8025 | - | |
8026 | -{"sthx", X(31,407), X_MASK, COM, {RS, RA0, RB}}, | |
8027 | - | |
8028 | -{"orc", XRC(31,412,0), X_MASK, COM, {RA, RS, RB}}, | |
8029 | -{"orc.", XRC(31,412,1), X_MASK, COM, {RA, RS, RB}}, | |
8030 | - | |
8031 | -{"sthxe", X(31,415), X_MASK, BOOKE64, {RS, RA0, RB}}, | |
8032 | -{"sthepx", X(31,415), X_MASK, E500MC, {RS, RA, RB}}, | |
8033 | - | |
8034 | -{"mtdcrux", X(31,419), X_MASK, PPC464, {RA, RS}}, | |
8035 | - | |
8036 | -{"slbie", X(31,434), XRTRA_MASK, PPC64, {RB}}, | |
8037 | - | |
8038 | -{"ecowx", X(31,438), X_MASK, PPC, {RT, RA, RB}}, | |
8039 | - | |
8040 | -{"sthux", X(31,439), X_MASK, COM, {RS, RAS, RB}}, | |
8041 | - | |
8042 | -{"mdors", 0x7f9ce378, 0xffffffff, E500MC, {0}}, | |
8043 | - | |
8044 | -{"mr", XRC(31,444,0), X_MASK, COM, {RA, RS, RBS}}, | |
8045 | -{"or", XRC(31,444,0), X_MASK, COM, {RA, RS, RB}}, | |
8046 | -{"mr.", XRC(31,444,1), X_MASK, COM, {RA, RS, RBS}}, | |
8047 | -{"or.", XRC(31,444,1), X_MASK, COM, {RA, RS, RB}}, | |
8048 | - | |
8049 | -{"sthuxe", X(31,447), X_MASK, BOOKE64, {RS, RAS, RB}}, | |
8050 | - | |
8051 | -{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, {RS}}, | |
8052 | -{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, {RS}}, | |
8053 | -{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, {RS}}, | |
8054 | -{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, {RS}}, | |
8055 | -{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, {RS}}, | |
8056 | -{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, {RS}}, | |
8057 | -{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, {RS}}, | |
8058 | -{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, {RS}}, | |
8059 | -{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, {RS}}, | |
8060 | -{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, {RS}}, | |
8061 | -{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, {RS}}, | |
8062 | -{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, {RS}}, | |
8063 | -{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, {RS}}, | |
8064 | -{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, {RS}}, | |
8065 | -{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, {RS}}, | |
8066 | -{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, {RS}}, | |
8067 | -{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, {RS}}, | |
8068 | -{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, {RS}}, | |
8069 | -{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, {RS}}, | |
8070 | -{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, {RS}}, | |
8071 | -{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, {RS}}, | |
8072 | -{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, {RS}}, | |
8073 | -{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, {RS}}, | |
8074 | -{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, {RS}}, | |
8075 | -{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, {RS}}, | |
8076 | -{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, {RS}}, | |
8077 | -{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, {RS}}, | |
8078 | -{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, {RS}}, | |
8079 | -{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, {RS}}, | |
8080 | -{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, {RS}}, | |
8081 | -{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, {RS}}, | |
8082 | -{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, {RS}}, | |
8083 | -{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, {RS}}, | |
8084 | -{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, {RS}}, | |
8085 | -{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, {SPR, RS}}, | |
8086 | - | |
8087 | -{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, {RA, RB}}, | |
8088 | - | |
8089 | -{"subfze64", XO(31,456,0,0), XORB_MASK, BOOKE64, {RT, RA}}, | |
8090 | - | |
8091 | -{"divdu", XO(31,457,0,0), XO_MASK, PPC64, {RT, RA, RB}}, | |
8092 | -{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, {RT, RA, RB}}, | |
8093 | - | |
8094 | -{"addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, {RT, RA}}, | |
8095 | - | |
8096 | -{"divwu", XO(31,459,0,0), XO_MASK, PPC, {RT, RA, RB}}, | |
8097 | -{"divwu.", XO(31,459,0,1), XO_MASK, PPC, {RT, RA, RB}}, | |
8098 | - | |
8099 | -{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, {PMR, RS}}, | |
8100 | - | |
8101 | -{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, {RS}}, | |
8102 | -{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, {RS}}, | |
8103 | -{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, {RS}}, | |
8104 | -{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, {RS}}, | |
8105 | -{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, {RS}}, | |
8106 | -{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, {RS}}, | |
8107 | -{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, {RS}}, | |
8108 | -{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, {RS}}, | |
8109 | -{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, {RS}}, | |
8110 | -{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, {RS}}, | |
8111 | -{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, {RS}}, | |
8112 | -{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, {RS}}, | |
8113 | -{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, {RS}}, | |
8114 | -{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, {RS}}, | |
8115 | -{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, {RS}}, | |
8116 | -{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, {RS}}, | |
8117 | -{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, {RS}}, | |
8118 | -{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, {RS}}, | |
8119 | -{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, {RS}}, | |
8120 | -{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, {RS}}, | |
8121 | -{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, {RS}}, | |
8122 | -{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, {RS}}, | |
8123 | -{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, {RS}}, | |
8124 | -{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, {RS}}, | |
8125 | -{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, {RS}}, | |
8126 | -{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, {RS}}, | |
8127 | -{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, {RS}}, | |
8128 | -{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, {RS}}, | |
8129 | -{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, {RS}}, | |
8130 | -{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, {RS}}, | |
8131 | -{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, {RS}}, | |
8132 | -{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, {RS}}, | |
8133 | -{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, {RS}}, | |
8134 | -{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, {RS}}, | |
8135 | -{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, {RS}}, | |
8136 | -{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, {RS}}, | |
8137 | -{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, {RS}}, | |
8138 | -{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, {RS}}, | |
8139 | -{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, {RS}}, | |
8140 | -{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, {RS}}, | |
8141 | -{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, {SPRG, RS}}, | |
8142 | -{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, {RS}}, | |
8143 | -{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, {RS}}, | |
8144 | -{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, {RS}}, | |
8145 | -{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, {RS}}, | |
8146 | -{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, {RS}}, | |
8147 | -{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, {RS}}, | |
8148 | -{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, {RS}}, | |
8149 | -{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, {RS}}, | |
8150 | -{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, {RS}}, | |
8151 | -{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, {RS}}, | |
8152 | -{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, {RS}}, | |
8153 | -{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, {RS}}, | |
8154 | -{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, {RS}}, | |
8155 | -{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, {RS}}, | |
8156 | -{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, {RS}}, | |
8157 | -{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, {RS}}, | |
8158 | -{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, {RS}}, | |
8159 | -{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, {RS}}, | |
8160 | -{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, {RS}}, | |
8161 | -{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, {RS}}, | |
8162 | -{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, {RS}}, | |
8163 | -{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, {RS}}, | |
8164 | -{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, {RS}}, | |
8165 | -{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, {RS}}, | |
8166 | -{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, {RS}}, | |
8167 | -{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, {RS}}, | |
8168 | -{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, {RS}}, | |
8169 | -{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, {RS}}, | |
8170 | -{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, {RS}}, | |
8171 | -{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, {RS}}, | |
8172 | -{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, {RS}}, | |
8173 | -{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, {RS}}, | |
8174 | -{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, {RS}}, | |
8175 | -{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, {RS}}, | |
8176 | -{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, {RS}}, | |
8177 | -{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, {RS}}, | |
8178 | -{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, {RS}}, | |
8179 | -{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, {RS}}, | |
8180 | -{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, {RS}}, | |
8181 | -{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, {RS}}, | |
8182 | -{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, {RS}}, | |
8183 | -{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, {RS}}, | |
8184 | -{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, {RS}}, | |
8185 | -{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, {RS}}, | |
8186 | -{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, {RS}}, | |
8187 | -{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, {RS}}, | |
8188 | -{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, | |
8189 | -{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, {RS}}, | |
8190 | -{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, | |
8191 | -{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, {RS}}, | |
8192 | -{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, {RS}}, | |
8193 | -{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, | |
8194 | -{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, {SPRBAT, RS}}, | |
8195 | -{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, {RS}}, | |
8196 | -{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, {RS}}, | |
8197 | -{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, {RS}}, | |
8198 | -{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, {RS}}, | |
8199 | -{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, {RS}}, | |
8200 | -{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, {RS}}, | |
8201 | -{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, {RS}}, | |
8202 | -{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, {RS}}, | |
8203 | -{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, {RS}}, | |
8204 | -{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, {RS}}, | |
8205 | -{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, {RS}}, | |
8206 | -{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, {RS}}, | |
8207 | -{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, {RS}}, | |
8208 | -{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, {RS}}, | |
8209 | -{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, {RS}}, | |
8210 | -{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, {RS}}, | |
8211 | -{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, {RS}}, | |
8212 | -{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, {RS}}, | |
8213 | -{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, {RS}}, | |
8214 | -{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, {RS}}, | |
8215 | -{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, {RS}}, | |
8216 | -{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, {RS}}, | |
8217 | -{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, {RS}}, | |
8218 | -{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, {RS}}, | |
8219 | -{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, {RS}}, | |
8220 | -{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, {RS}}, | |
8221 | -{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, {RS}}, | |
8222 | -{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, {RS}}, | |
8223 | -{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, {RS}}, | |
8224 | -{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, {RS}}, | |
8225 | -{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, {RS}}, | |
8226 | -{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, {RS}}, | |
8227 | -{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, {RS}}, | |
8228 | -{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, {RS}}, | |
8229 | -{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, {RS}}, | |
8230 | -{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, {RS}}, | |
8231 | -{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, {RS}}, | |
8232 | -{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, {RS}}, | |
8233 | -{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, {RS}}, | |
8234 | -{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, {RS}}, | |
8235 | -{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, {RS}}, | |
8236 | -{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, {RS}}, | |
8237 | -{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, {RS}}, | |
8238 | -{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, {RS}}, | |
8239 | -{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, {RS}}, | |
8240 | -{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, {RS}}, | |
8241 | -{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, {RS}}, | |
8242 | -{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, {RS}}, | |
8243 | -{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, {RS}}, | |
8244 | -{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, {RS}}, | |
8245 | -{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, {RS}}, | |
8246 | -{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, {RS}}, | |
8247 | -{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, {RS}}, | |
8248 | -{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, {RS}}, | |
8249 | -{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, {RS}}, | |
8250 | -{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, {RS}}, | |
8251 | -{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, {RS}}, | |
8252 | -{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, {RS}}, | |
8253 | -{"mtspr", X(31,467), X_MASK, COM, {SPR, RS}}, | |
8254 | - | |
8255 | -{"dcbi", X(31,470), XRT_MASK, PPC, {RA, RB}}, | |
8256 | - | |
8257 | -{"nand", XRC(31,476,0), X_MASK, COM, {RA, RS, RB}}, | |
8258 | -{"nand.", XRC(31,476,1), X_MASK, COM, {RA, RS, RB}}, | |
8259 | - | |
8260 | -{"dcbie", X(31,478), XRT_MASK, BOOKE64, {RA, RB}}, | |
8261 | - | |
8262 | -{"dsn", X(31,483), XRT_MASK, E500MC, {RA, RB}}, | |
8263 | - | |
8264 | -{"dcread", X(31,486), X_MASK, PPC403|PPC440, {RT, RA, RB}}, | |
8265 | - | |
8266 | -{"icbtls", X(31,486), X_MASK, PPCCHLK, {CT, RA, RB}}, | |
8267 | - | |
8268 | -{"stvxl", X(31,487), X_MASK, PPCVEC, {VS, RA, RB}}, | |
8269 | - | |
8270 | -{"nabs", XO(31,488,0,0), XORB_MASK, M601, {RT, RA}}, | |
8271 | -{"subfme64", XO(31,488,0,0), XORB_MASK, BOOKE64, {RT, RA}}, | |
8272 | -{"nabs.", XO(31,488,0,1), XORB_MASK, M601, {RT, RA}}, | |
8273 | - | |
8274 | -{"divd", XO(31,489,0,0), XO_MASK, PPC64, {RT, RA, RB}}, | |
8275 | -{"divd.", XO(31,489,0,1), XO_MASK, PPC64, {RT, RA, RB}}, | |
8276 | - | |
8277 | -{"addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, {RT, RA}}, | |
8278 | - | |
8279 | -{"divw", XO(31,491,0,0), XO_MASK, PPC, {RT, RA, RB}}, | |
8280 | -{"divw.", XO(31,491,0,1), XO_MASK, PPC, {RT, RA, RB}}, | |
8281 | - | |
8282 | -{"icbtlse", X(31,494), X_MASK, PPCCHLK64, {CT, RA, RB}}, | |
8283 | - | |
8284 | -{"slbia", X(31,498), 0xffffffff, PPC64, {0}}, | |
8285 | - | |
8286 | -{"cli", X(31,502), XRB_MASK, POWER, {RT, RA}}, | |
8287 | - | |
8288 | -{"cmpb", X(31,508), X_MASK, POWER6, {RA, RS, RB}}, | |
8289 | - | |
8290 | -{"stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, {RS, RA, RB}}, | |
8291 | - | |
8292 | -{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, {BF}}, | |
8293 | - | |
8294 | -{"lbdx", X(31,515), X_MASK, E500MC, {RT, RA, RB}}, | |
8295 | - | |
8296 | -{"bblels", X(31,518), X_MASK, PPCBRLK, {0}}, | |
8297 | - | |
8298 | -{"lvlx", X(31,519), X_MASK, CELL, {VD, RA0, RB}}, | |
8299 | -{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8300 | - | |
8301 | -{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8302 | -{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8303 | -{"subco", XO(31,8,1,0), XO_MASK, PPC, {RT, RB, RA}}, | |
8304 | -{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8305 | -{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8306 | -{"subco.", XO(31,8,1,1), XO_MASK, PPC, {RT, RB, RA}}, | |
8307 | - | |
8308 | -{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8309 | -{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8310 | -{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8311 | -{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8312 | - | |
8313 | -{"clcs", X(31,531), XRB_MASK, M601, {RT, RA}}, | |
8314 | - | |
8315 | -{"ldbrx", X(31,532), X_MASK, CELL, {RT, RA0, RB}}, | |
8316 | - | |
8317 | -{"lswx", X(31,533), X_MASK, PPCCOM, {RT, RA0, RB}}, | |
8318 | -{"lsx", X(31,533), X_MASK, PWRCOM, {RT, RA, RB}}, | |
8319 | - | |
8320 | -{"lwbrx", X(31,534), X_MASK, PPCCOM, {RT, RA0, RB}}, | |
8321 | -{"lbrx", X(31,534), X_MASK, PWRCOM, {RT, RA, RB}}, | |
8322 | - | |
8323 | -{"lfsx", X(31,535), X_MASK, COM, {FRT, RA0, RB}}, | |
8324 | - | |
8325 | -{"srw", XRC(31,536,0), X_MASK, PPCCOM, {RA, RS, RB}}, | |
8326 | -{"sr", XRC(31,536,0), X_MASK, PWRCOM, {RA, RS, RB}}, | |
8327 | -{"srw.", XRC(31,536,1), X_MASK, PPCCOM, {RA, RS, RB}}, | |
8328 | -{"sr.", XRC(31,536,1), X_MASK, PWRCOM, {RA, RS, RB}}, | |
8329 | - | |
8330 | -{"rrib", XRC(31,537,0), X_MASK, M601, {RA, RS, RB}}, | |
8331 | -{"rrib.", XRC(31,537,1), X_MASK, M601, {RA, RS, RB}}, | |
8332 | - | |
8333 | -{"srd", XRC(31,539,0), X_MASK, PPC64, {RA, RS, RB}}, | |
8334 | -{"srd.", XRC(31,539,1), X_MASK, PPC64, {RA, RS, RB}}, | |
8335 | - | |
8336 | -{"maskir", XRC(31,541,0), X_MASK, M601, {RA, RS, RB}}, | |
8337 | -{"maskir.", XRC(31,541,1), X_MASK, M601, {RA, RS, RB}}, | |
8338 | - | |
8339 | -{"lwbrxe", X(31,542), X_MASK, BOOKE64, {RT, RA0, RB}}, | |
8340 | - | |
8341 | -{"lfsxe", X(31,543), X_MASK, BOOKE64, {FRT, RA0, RB}}, | |
8342 | - | |
8343 | -{"mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, {BF}}, | |
8344 | - | |
8345 | -{"lhdx", X(31,547), X_MASK, E500MC, {RT, RA, RB}}, | |
8346 | - | |
8347 | -{"bbelr", X(31,550), X_MASK, PPCBRLK, {0}}, | |
8348 | - | |
8349 | -{"lvrx", X(31,551), X_MASK, CELL, {VD, RA0, RB}}, | |
8350 | -{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8351 | - | |
8352 | -{"subfo", XO(31,40,1,0), XO_MASK, PPC, {RT, RA, RB}}, | |
8353 | -{"subo", XO(31,40,1,0), XO_MASK, PPC, {RT, RB, RA}}, | |
8354 | -{"subfo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RA, RB}}, | |
8355 | -{"subo.", XO(31,40,1,1), XO_MASK, PPC, {RT, RB, RA}}, | |
8356 | - | |
8357 | -{"tlbsync", X(31,566), 0xffffffff, PPC, {0}}, | |
8358 | - | |
8359 | -{"lfsux", X(31,567), X_MASK, COM, {FRT, RAS, RB}}, | |
8360 | - | |
8361 | -{"lfsuxe", X(31,575), X_MASK, BOOKE64, {FRT, RAS, RB}}, | |
8362 | - | |
8363 | -{"lwdx", X(31,579), X_MASK, E500MC, {RT, RA, RB}}, | |
8364 | - | |
8365 | -{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8366 | - | |
8367 | -{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, {RT, SR}}, | |
8368 | - | |
8369 | -{"lswi", X(31,597), X_MASK, PPCCOM, {RT, RA0, NB}}, | |
8370 | -{"lsi", X(31,597), X_MASK, PWRCOM, {RT, RA0, NB}}, | |
8371 | - | |
8372 | -{"msync", X(31,598), 0xffffffff, BOOKE, {0}}, | |
8373 | -{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, {0}}, | |
8374 | -{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, {0}}, | |
8375 | -{"sync", X(31,598), XSYNC_MASK, PPCCOM, {LS}}, | |
8376 | -{"dcs", X(31,598), 0xffffffff, PWRCOM, {0}}, | |
8377 | - | |
8378 | -{"lfdx", X(31,599), X_MASK, COM, {FRT, RA0, RB}}, | |
8379 | - | |
8380 | -{"lfdxe", X(31,607), X_MASK, BOOKE64, {FRT, RA0, RB}}, | |
8381 | -{"lfdepx", X(31,607), X_MASK, E500MC, {RT, RA, RB}}, | |
8382 | -{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, {FRT, RB}}, | |
8383 | - | |
8384 | -{"lddx", X(31,611), X_MASK, E500MC, {RT, RA, RB}}, | |
8385 | - | |
8386 | -{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8387 | - | |
8388 | -{"nego", XO(31,104,1,0), XORB_MASK, COM, {RT, RA}}, | |
8389 | -{"nego.", XO(31,104,1,1), XORB_MASK, COM, {RT, RA}}, | |
8390 | - | |
8391 | -{"mulo", XO(31,107,1,0), XO_MASK, M601, {RT, RA, RB}}, | |
8392 | -{"mulo.", XO(31,107,1,1), XO_MASK, M601, {RT, RA, RB}}, | |
8393 | - | |
8394 | -{"mfsri", X(31,627), X_MASK, PWRCOM, {RT, RA, RB}}, | |
8395 | - | |
8396 | -{"dclst", X(31,630), XRB_MASK, PWRCOM, {RS, RA}}, | |
8397 | - | |
8398 | -{"lfdux", X(31,631), X_MASK, COM, {FRT, RAS, RB}}, | |
8399 | - | |
8400 | -{"lfduxe", X(31,639), X_MASK, BOOKE64, {FRT, RAS, RB}}, | |
8401 | - | |
8402 | -{"stbdx", X(31,643), X_MASK, E500MC, {RS, RA, RB}}, | |
8403 | - | |
8404 | -{"stvlx", X(31,647), X_MASK, CELL, {VS, RA0, RB}}, | |
8405 | -{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8406 | - | |
8407 | -{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8408 | -{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8409 | -{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8410 | -{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8411 | - | |
8412 | -{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8413 | -{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8414 | -{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8415 | -{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8416 | - | |
8417 | -{"mfsrin", X(31,659), XRA_MASK, PPC32, {RT, RB}}, | |
8418 | - | |
8419 | -{"stdbrx", X(31,660), X_MASK, CELL, {RS, RA0, RB}}, | |
8420 | - | |
8421 | -{"stswx", X(31,661), X_MASK, PPCCOM, {RS, RA0, RB}}, | |
8422 | -{"stsx", X(31,661), X_MASK, PWRCOM, {RS, RA0, RB}}, | |
8423 | - | |
8424 | -{"stwbrx", X(31,662), X_MASK, PPCCOM, {RS, RA0, RB}}, | |
8425 | -{"stbrx", X(31,662), X_MASK, PWRCOM, {RS, RA0, RB}}, | |
8426 | - | |
8427 | -{"stfsx", X(31,663), X_MASK, COM, {FRS, RA0, RB}}, | |
8428 | - | |
8429 | -{"srq", XRC(31,664,0), X_MASK, M601, {RA, RS, RB}}, | |
8430 | -{"srq.", XRC(31,664,1), X_MASK, M601, {RA, RS, RB}}, | |
8431 | - | |
8432 | -{"sre", XRC(31,665,0), X_MASK, M601, {RA, RS, RB}}, | |
8433 | -{"sre.", XRC(31,665,1), X_MASK, M601, {RA, RS, RB}}, | |
8434 | - | |
8435 | -{"stwbrxe", X(31,670), X_MASK, BOOKE64, {RS, RA0, RB}}, | |
8436 | - | |
8437 | -{"stfsxe", X(31,671), X_MASK, BOOKE64, {FRS, RA0, RB}}, | |
8438 | - | |
8439 | -{"sthdx", X(31,675), X_MASK, E500MC, {RS, RA, RB}}, | |
8440 | - | |
8441 | -{"stvrx", X(31,679), X_MASK, CELL, {VS, RA0, RB}}, | |
8442 | -{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8443 | - | |
8444 | -{"stfsux", X(31,695), X_MASK, COM, {FRS, RAS, RB}}, | |
8445 | - | |
8446 | -{"sriq", XRC(31,696,0), X_MASK, M601, {RA, RS, SH}}, | |
8447 | -{"sriq.", XRC(31,696,1), X_MASK, M601, {RA, RS, SH}}, | |
8448 | - | |
8449 | -{"stfsuxe", X(31,703), X_MASK, BOOKE64, {FRS, RAS, RB}}, | |
8450 | - | |
8451 | -{"stwdx", X(31,707), X_MASK, E500MC, {RS, RA, RB}}, | |
8452 | - | |
8453 | -{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8454 | - | |
8455 | -{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, {RT, RA}}, | |
8456 | -{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, {RT, RA}}, | |
8457 | -{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, {RT, RA}}, | |
8458 | -{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, {RT, RA}}, | |
8459 | - | |
8460 | -{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, {RT, RA}}, | |
8461 | -{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, {RT, RA}}, | |
8462 | -{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, {RT, RA}}, | |
8463 | -{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, {RT, RA}}, | |
8464 | - | |
8465 | -{"stswi", X(31,725), X_MASK, PPCCOM, {RS, RA0, NB}}, | |
8466 | -{"stsi", X(31,725), X_MASK, PWRCOM, {RS, RA0, NB}}, | |
8467 | - | |
8468 | -{"stfdx", X(31,727), X_MASK, COM, {FRS, RA0, RB}}, | |
8469 | - | |
8470 | -{"srlq", XRC(31,728,0), X_MASK, M601, {RA, RS, RB}}, | |
8471 | -{"srlq.", XRC(31,728,1), X_MASK, M601, {RA, RS, RB}}, | |
8472 | - | |
8473 | -{"sreq", XRC(31,729,0), X_MASK, M601, {RA, RS, RB}}, | |
8474 | -{"sreq.", XRC(31,729,1), X_MASK, M601, {RA, RS, RB}}, | |
8475 | - | |
8476 | -{"stfdxe", X(31,735), X_MASK, BOOKE64, {FRS, RA0, RB}}, | |
8477 | -{"stfdepx", X(31,735), X_MASK, E500MC, {RS, RA, RB}}, | |
8478 | -{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, {RT, FRB}}, | |
8479 | - | |
8480 | -{"stddx", X(31,739), X_MASK, E500MC, {RS, RA, RB}}, | |
8481 | - | |
8482 | -{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8483 | - | |
8484 | -{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, {RT, RA}}, | |
8485 | -{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, {RT, RA}}, | |
8486 | -{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, {RT, RA}}, | |
8487 | -{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, {RT, RA}}, | |
8488 | - | |
8489 | -{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, {RT, RA, RB}}, | |
8490 | -{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, {RT, RA, RB}}, | |
8491 | - | |
8492 | -{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, {RT, RA}}, | |
8493 | -{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, {RT, RA}}, | |
8494 | -{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, {RT, RA}}, | |
8495 | -{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, {RT, RA}}, | |
8496 | - | |
8497 | -{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8498 | -{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8499 | -{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8500 | -{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8501 | - | |
8502 | -{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, {RA, RB}}, | |
8503 | -{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, {RA, RB}}, | |
8504 | - | |
8505 | -{"stfdux", X(31,759), X_MASK, COM, {FRS, RAS, RB}}, | |
8506 | - | |
8507 | -{"srliq", XRC(31,760,0), X_MASK, M601, {RA, RS, SH}}, | |
8508 | -{"srliq.", XRC(31,760,1), X_MASK, M601, {RA, RS, SH}}, | |
8509 | - | |
8510 | -{"dcbae", X(31,766), XRT_MASK, BOOKE64, {RA, RB}}, | |
8511 | - | |
8512 | -{"stfduxe", X(31,767), X_MASK, BOOKE64, {FRS, RAS, RB}}, | |
8513 | - | |
8514 | -{"lvlxl", X(31,775), X_MASK, CELL, {VD, RA0, RB}}, | |
8515 | -{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8516 | - | |
8517 | -{"dozo", XO(31,264,1,0), XO_MASK, M601, {RT, RA, RB}}, | |
8518 | -{"dozo.", XO(31,264,1,1), XO_MASK, M601, {RT, RA, RB}}, | |
8519 | - | |
8520 | -{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8521 | -{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8522 | -{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, {RT, RA, RB}}, | |
8523 | -{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, {RT, RA, RB}}, | |
8524 | - | |
8525 | -{"tlbivax", X(31,786), XRT_MASK, BOOKE, {RA, RB}}, | |
8526 | -{"tlbivaxe", X(31,787), XRT_MASK, BOOKE64, {RA, RB}}, | |
8527 | -{"tlbilx", X(31,787), X_MASK, E500MC, {T, RA0, RB}}, | |
8528 | -{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, {0}}, | |
8529 | -{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, {0}}, | |
8530 | -{"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, {RA0, RB}}, | |
8531 | - | |
8532 | -{"lwzcix", X(31,789), X_MASK, POWER6, {RT, RA0, RB}}, | |
8533 | - | |
8534 | -{"lhbrx", X(31,790), X_MASK, COM, {RT, RA0, RB}}, | |
8535 | - | |
8536 | -{"lfqx", X(31,791), X_MASK, POWER2, {FRT, RA, RB}}, | |
8537 | -{"lfdpx", X(31,791), X_MASK, POWER6, {FRT, RA, RB}}, | |
8538 | - | |
8539 | -{"sraw", XRC(31,792,0), X_MASK, PPCCOM, {RA, RS, RB}}, | |
8540 | -{"sra", XRC(31,792,0), X_MASK, PWRCOM, {RA, RS, RB}}, | |
8541 | -{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, {RA, RS, RB}}, | |
8542 | -{"sra.", XRC(31,792,1), X_MASK, PWRCOM, {RA, RS, RB}}, | |
8543 | - | |
8544 | -{"srad", XRC(31,794,0), X_MASK, PPC64, {RA, RS, RB}}, | |
8545 | -{"srad.", XRC(31,794,1), X_MASK, PPC64, {RA, RS, RB}}, | |
8546 | - | |
8547 | -{"lhbrxe", X(31,798), X_MASK, BOOKE64, {RT, RA0, RB}}, | |
8548 | - | |
8549 | -{"ldxe", X(31,799), X_MASK, BOOKE64, {RT, RA0, RB}}, | |
8550 | - | |
8551 | -{"lfddx", X(31,803), X_MASK, E500MC, {FRT, RA, RB}}, | |
8552 | - | |
8553 | -{"lvrxl", X(31,807), X_MASK, CELL, {VD, RA0, RB}}, | |
8554 | - | |
8555 | -{"rac", X(31,818), X_MASK, PWRCOM, {RT, RA, RB}}, | |
8556 | - | |
8557 | -{"lhzcix", X(31,821), X_MASK, POWER6, {RT, RA0, RB}}, | |
8558 | - | |
8559 | -{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, {STRM}}, | |
8560 | - | |
8561 | -{"lfqux", X(31,823), X_MASK, POWER2, {FRT, RA, RB}}, | |
8562 | - | |
8563 | -{"srawi", XRC(31,824,0), X_MASK, PPCCOM, {RA, RS, SH}}, | |
8564 | -{"srai", XRC(31,824,0), X_MASK, PWRCOM, {RA, RS, SH}}, | |
8565 | -{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, {RA, RS, SH}}, | |
8566 | -{"srai.", XRC(31,824,1), X_MASK, PWRCOM, {RA, RS, SH}}, | |
8567 | - | |
8568 | -{"sradi", XS(31,413,0), XS_MASK, PPC64, {RA, RS, SH6}}, | |
8569 | -{"sradi.", XS(31,413,1), XS_MASK, PPC64, {RA, RS, SH6}}, | |
8570 | - | |
8571 | -{"divo", XO(31,331,1,0), XO_MASK, M601, {RT, RA, RB}}, | |
8572 | -{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}}, | |
8573 | -{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}}, | |
8574 | - | |
8575 | -{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}}, | |
8576 | - | |
8577 | -{"slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}}, | |
8578 | - | |
8579 | -{"lbzcix", X(31,853), X_MASK, POWER6, {RT, RA0, RB}}, | |
8580 | - | |
8581 | -{"mbar", X(31,854), X_MASK, BOOKE, {MO}}, | |
8582 | -{"eieio", X(31,854), 0xffffffff, PPC, {0}}, | |
8583 | - | |
8584 | -{"lfiwax", X(31,855), X_MASK, POWER6, {FRT, RA0, RB}}, | |
8585 | - | |
8586 | -{"abso", XO(31,360,1,0), XORB_MASK, M601, {RT, RA}}, | |
8587 | -{"abso.", XO(31,360,1,1), XORB_MASK, M601, {RT, RA}}, | |
8588 | - | |
8589 | -{"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}}, | |
8590 | -{"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}}, | |
8591 | - | |
8592 | -{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, {XT6, RA, RB}}, | |
8593 | - | |
8594 | -{"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}}, | |
8595 | - | |
8596 | -{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}}, | |
8597 | -{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, {FCRT, RA, RB}}, | |
8598 | - | |
8599 | -{"subfe64o", XO(31,392,1,0), XO_MASK, BOOKE64, {RT, RA, RB}}, | |
8600 | - | |
8601 | -{"adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, {RT, RA, RB}}, | |
8602 | - | |
8603 | -{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, {RTO, RA, RB}}, | |
8604 | -{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, {RTO, RA, RB}}, | |
8605 | - | |
8606 | -{"tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, {RTO, RA, RB}}, | |
8607 | -{"tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, {RTO, RA, RB}}, | |
8608 | -{"slbmfee", X(31,915), XRA_MASK, PPC64, {RT, RB}}, | |
8609 | - | |
8610 | -{"stwcix", X(31,917), X_MASK, POWER6, {RS, RA0, RB}}, | |
8611 | - | |
8612 | -{"sthbrx", X(31,918), X_MASK, COM, {RS, RA0, RB}}, | |
8613 | - | |
8614 | -{"stfqx", X(31,919), X_MASK, POWER2, {FRS, RA, RB}}, | |
8615 | -{"stfdpx", X(31,919), X_MASK, POWER6, {FRS, RA, RB}}, | |
8616 | - | |
8617 | -{"sraq", XRC(31,920,0), X_MASK, M601, {RA, RS, RB}}, | |
8618 | -{"sraq.", XRC(31,920,1), X_MASK, M601, {RA, RS, RB}}, | |
8619 | - | |
8620 | -{"srea", XRC(31,921,0), X_MASK, M601, {RA, RS, RB}}, | |
8621 | -{"srea.", XRC(31,921,1), X_MASK, M601, {RA, RS, RB}}, | |
8622 | - | |
8623 | -{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, {RA, RS}}, | |
8624 | -{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, {RA, RS}}, | |
8625 | -{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, {RA, RS}}, | |
8626 | -{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, {RA, RS}}, | |
8627 | - | |
8628 | -{"sthbrxe", X(31,926), X_MASK, BOOKE64, {RS, RA0, RB}}, | |
8629 | - | |
8630 | -{"stdxe", X(31,927), X_MASK, BOOKE64, {RS, RA0, RB}}, | |
8631 | - | |
8632 | -{"stfddx", X(31,931), X_MASK, E500MC, {FRS, RA, RB}}, | |
8633 | - | |
8634 | -{"stvrxl", X(31,935), X_MASK, CELL, {VS, RA0, RB}}, | |
8635 | - | |
8636 | -{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, {RT, RA}}, | |
8637 | -{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, {RT, RA}}, | |
8638 | -{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}}, | |
8639 | - | |
8640 | -{"sthcix", X(31,949), X_MASK, POWER6, {RS, RA0, RB}}, | |
8641 | - | |
8642 | -{"stfqux", X(31,951), X_MASK, POWER2, {FRS, RA, RB}}, | |
8643 | - | |
8644 | -{"sraiq", XRC(31,952,0), X_MASK, M601, {RA, RS, SH}}, | |
8645 | -{"sraiq.", XRC(31,952,1), X_MASK, M601, {RA, RS, SH}}, | |
8646 | - | |
8647 | -{"extsb", XRC(31,954,0), XRB_MASK, PPC, {RA, RS}}, | |
8648 | -{"extsb.", XRC(31,954,1), XRB_MASK, PPC, {RA, RS}}, | |
8649 | - | |
8650 | -{"stduxe", X(31,959), X_MASK, BOOKE64, {RS, RAS, RB}}, | |
8651 | - | |
8652 | -{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, {RA, RB}}, | |
8653 | - | |
8654 | -{"subfze64o", XO(31,456,1,0), XORB_MASK, BOOKE64, {RT, RA}}, | |
8655 | - | |
8656 | -{"divduo", XO(31,457,1,0), XO_MASK, PPC64, {RT, RA, RB}}, | |
8657 | -{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, {RT, RA, RB}}, | |
8658 | - | |
8659 | -{"addze64o", XO(31,458,1,0), XORB_MASK, BOOKE64, {RT, RA}}, | |
8660 | - | |
8661 | -{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}}, | |
8662 | -{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}}, | |
8663 | - | |
8664 | -{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, {XS6, RA, RB}}, | |
8665 | - | |
8666 | -{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}}, | |
8667 | -{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}}, | |
8668 | -{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}}, | |
8669 | -{"tlbld", X(31,978), XRTRA_MASK, PPC, {RB}}, | |
8670 | - | |
8671 | -{"stbcix", X(31,981), X_MASK, POWER6, {RS, RA0, RB}}, | |
8672 | - | |
8673 | -{"icbi", X(31,982), XRT_MASK, PPC, {RA, RB}}, | |
8674 | - | |
8675 | -{"stfiwx", X(31,983), X_MASK, PPC, {FRS, RA0, RB}}, | |
8676 | - | |
8677 | -{"extsw", XRC(31,986,0), XRB_MASK, PPC64|BOOKE64, {RA, RS}}, | |
8678 | -{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, {RA, RS}}, | |
8679 | - | |
8680 | -{"icbie", X(31,990), XRT_MASK, BOOKE64, {RA, RB}}, | |
8681 | -{"stfiwxe", X(31,991), X_MASK, BOOKE64, {FRS, RA0, RB}}, | |
8682 | - | |
8683 | -{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, {RA, RB}}, | |
8684 | - | |
8685 | -{"icread", X(31,998), XRT_MASK, PPC403|PPC440, {RA, RB}}, | |
8686 | - | |
8687 | -{"nabso", XO(31,488,1,0), XORB_MASK, M601, {RT, RA}}, | |
8688 | -{"subfme64o", XO(31,488,1,0), XORB_MASK, BOOKE64, {RT, RA}}, | |
8689 | -{"nabso.", XO(31,488,1,1), XORB_MASK, M601, {RT, RA}}, | |
8690 | - | |
8691 | -{"divdo", XO(31,489,1,0), XO_MASK, PPC64, {RT, RA, RB}}, | |
8692 | -{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, {RT, RA, RB}}, | |
8693 | - | |
8694 | -{"addme64o", XO(31,490,1,0), XORB_MASK, BOOKE64, {RT, RA}}, | |
8695 | - | |
8696 | -{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}}, | |
8697 | -{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}}, | |
8698 | - | |
8699 | -{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, {XS6, RA, RB}}, | |
8700 | - | |
8701 | -{"tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}}, | |
8702 | - | |
8703 | -{"stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}}, | |
8704 | - | |
8705 | -{"dcbz", X(31,1014), XRT_MASK, PPC, {RA, RB}}, | |
8706 | -{"dclz", X(31,1014), XRT_MASK, PPC, {RA, RB}}, | |
8707 | - | |
8708 | -{"dcbze", X(31,1022), XRT_MASK, BOOKE64, {RA, RB}}, | |
8709 | -{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, {RA, RB}}, | |
8710 | - | |
8711 | -{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, {RA, RB}}, | |
8712 | -{"dcbzl", XOPL(31,1014,1), XRT_MASK, NOPOWER4|E500MC,{RA, RB}}, | |
8713 | - | |
8714 | -{"cctpl", 0x7c210b78, 0xffffffff, CELL, {0}}, | |
8715 | -{"cctpm", 0x7c421378, 0xffffffff, CELL, {0}}, | |
8716 | -{"cctph", 0x7c631b78, 0xffffffff, CELL, {0}}, | |
8717 | - | |
8718 | -{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, | |
8719 | -{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, {RA, RB, STRM}}, | |
8720 | -{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, {0}}, | |
8721 | - | |
8722 | -{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, {0}}, | |
8723 | -{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, {0}}, | |
8724 | -{"db12cyc", 0x7fdef378, 0xffffffff, CELL, {0}}, | |
8725 | -{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, {0}}, | |
8726 | - | |
8727 | -{"lwz", OP(32), OP_MASK, PPCCOM, {RT, D, RA0}}, | |
8728 | -{"l", OP(32), OP_MASK, PWRCOM, {RT, D, RA0}}, | |
8729 | - | |
8730 | -{"lwzu", OP(33), OP_MASK, PPCCOM, {RT, D, RAL}}, | |
8731 | -{"lu", OP(33), OP_MASK, PWRCOM, {RT, D, RA0}}, | |
8732 | - | |
8733 | -{"lbz", OP(34), OP_MASK, COM, {RT, D, RA0}}, | |
8734 | - | |
8735 | -{"lbzu", OP(35), OP_MASK, COM, {RT, D, RAL}}, | |
8736 | - | |
8737 | -{"stw", OP(36), OP_MASK, PPCCOM, {RS, D, RA0}}, | |
8738 | -{"st", OP(36), OP_MASK, PWRCOM, {RS, D, RA0}}, | |
8739 | - | |
8740 | -{"stwu", OP(37), OP_MASK, PPCCOM, {RS, D, RAS}}, | |
8741 | -{"stu", OP(37), OP_MASK, PWRCOM, {RS, D, RA0}}, | |
8742 | - | |
8743 | -{"stb", OP(38), OP_MASK, COM, {RS, D, RA0}}, | |
8744 | - | |
8745 | -{"stbu", OP(39), OP_MASK, COM, {RS, D, RAS}}, | |
8746 | - | |
8747 | -{"lhz", OP(40), OP_MASK, COM, {RT, D, RA0}}, | |
8748 | - | |
8749 | -{"lhzu", OP(41), OP_MASK, COM, {RT, D, RAL}}, | |
8750 | - | |
8751 | -{"lha", OP(42), OP_MASK, COM, {RT, D, RA0}}, | |
8752 | - | |
8753 | -{"lhau", OP(43), OP_MASK, COM, {RT, D, RAL}}, | |
8754 | - | |
8755 | -{"sth", OP(44), OP_MASK, COM, {RS, D, RA0}}, | |
8756 | - | |
8757 | -{"sthu", OP(45), OP_MASK, COM, {RS, D, RAS}}, | |
8758 | - | |
8759 | -{"lmw", OP(46), OP_MASK, PPCCOM, {RT, D, RAM}}, | |
8760 | -{"lm", OP(46), OP_MASK, PWRCOM, {RT, D, RA0}}, | |
8761 | - | |
8762 | -{"stmw", OP(47), OP_MASK, PPCCOM, {RS, D, RA0}}, | |
8763 | -{"stm", OP(47), OP_MASK, PWRCOM, {RS, D, RA0}}, | |
8764 | - | |
8765 | -{"lfs", OP(48), OP_MASK, COM, {FRT, D, RA0}}, | |
8766 | - | |
8767 | -{"lfsu", OP(49), OP_MASK, COM, {FRT, D, RAS}}, | |
8768 | - | |
8769 | -{"lfd", OP(50), OP_MASK, COM, {FRT, D, RA0}}, | |
8770 | - | |
8771 | -{"lfdu", OP(51), OP_MASK, COM, {FRT, D, RAS}}, | |
8772 | - | |
8773 | -{"stfs", OP(52), OP_MASK, COM, {FRS, D, RA0}}, | |
8774 | - | |
8775 | -{"stfsu", OP(53), OP_MASK, COM, {FRS, D, RAS}}, | |
8776 | - | |
8777 | -{"stfd", OP(54), OP_MASK, COM, {FRS, D, RA0}}, | |
8778 | - | |
8779 | -{"stfdu", OP(55), OP_MASK, COM, {FRS, D, RAS}}, | |
8780 | - | |
8781 | -{"lq", OP(56), OP_MASK, POWER4, {RTQ, DQ, RAQ}}, | |
8782 | - | |
8783 | -{"lfq", OP(56), OP_MASK, POWER2, {FRT, D, RA0}}, | |
8784 | - | |
8785 | -{"psq_l", OP(56), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}}, | |
8786 | - | |
8787 | -{"lfqu", OP(57), OP_MASK, POWER2, {FRT, D, RA0}}, | |
8788 | - | |
8789 | -{"psq_lu", OP(57), OP_MASK, PPCPS, {FRT,PSD,RA,PSW,PSQ}}, | |
8790 | - | |
8791 | -{"lfdp", OP(57), OP_MASK, POWER6, {FRT, D, RA0}}, | |
8792 | - | |
8793 | -{"lbze", DEO(58,0), DE_MASK, BOOKE64, {RT, DE, RA0}}, | |
8794 | -{"lbzue", DEO(58,1), DE_MASK, BOOKE64, {RT, DE, RAL}}, | |
8795 | -{"lhze", DEO(58,2), DE_MASK, BOOKE64, {RT, DE, RA0}}, | |
8796 | -{"lhzue", DEO(58,3), DE_MASK, BOOKE64, {RT, DE, RAL}}, | |
8797 | -{"lhae", DEO(58,4), DE_MASK, BOOKE64, {RT, DE, RA0}}, | |
8798 | -{"lhaue", DEO(58,5), DE_MASK, BOOKE64, {RT, DE, RAL}}, | |
8799 | -{"lwze", DEO(58,6), DE_MASK, BOOKE64, {RT, DE, RA0}}, | |
8800 | -{"lwzue", DEO(58,7), DE_MASK, BOOKE64, {RT, DE, RAL}}, | |
8801 | -{"stbe", DEO(58,8), DE_MASK, BOOKE64, {RS, DE, RA0}}, | |
8802 | -{"stbue", DEO(58,9), DE_MASK, BOOKE64, {RS, DE, RAS}}, | |
8803 | -{"sthe", DEO(58,10), DE_MASK, BOOKE64, {RS, DE, RA0}}, | |
8804 | -{"sthue", DEO(58,11), DE_MASK, BOOKE64, {RS, DE, RAS}}, | |
8805 | -{"stwe", DEO(58,14), DE_MASK, BOOKE64, {RS, DE, RA0}}, | |
8806 | -{"stwue", DEO(58,15), DE_MASK, BOOKE64, {RS, DE, RAS}}, | |
8807 | - | |
8808 | -{"ld", DSO(58,0), DS_MASK, PPC64, {RT, DS, RA0}}, | |
8809 | -{"ldu", DSO(58,1), DS_MASK, PPC64, {RT, DS, RAL}}, | |
8810 | -{"lwa", DSO(58,2), DS_MASK, PPC64, {RT, DS, RA0}}, | |
8811 | - | |
8812 | -{"dadd", XRC(59,2,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8813 | -{"dadd.", XRC(59,2,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8814 | - | |
8815 | -{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}}, | |
8816 | -{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, {FRT,FRA,FRB,RMC}}, | |
8817 | - | |
8818 | -{"fdivs", A(59,18,0), AFRC_MASK, PPC, {FRT, FRA, FRB}}, | |
8819 | -{"fdivs.", A(59,18,1), AFRC_MASK, PPC, {FRT, FRA, FRB}}, | |
8820 | - | |
8821 | -{"fsubs", A(59,20,0), AFRC_MASK, PPC, {FRT, FRA, FRB}}, | |
8822 | -{"fsubs.", A(59,20,1), AFRC_MASK, PPC, {FRT, FRA, FRB}}, | |
8823 | - | |
8824 | -{"fadds", A(59,21,0), AFRC_MASK, PPC, {FRT, FRA, FRB}}, | |
8825 | -{"fadds.", A(59,21,1), AFRC_MASK, PPC, {FRT, FRA, FRB}}, | |
8826 | - | |
8827 | -{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, {FRT, FRB}}, | |
8828 | -{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, {FRT, FRB}}, | |
8829 | - | |
8830 | -{"fres", A(59,24,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, | |
8831 | -{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, | |
8832 | - | |
8833 | -{"fmuls", A(59,25,0), AFRB_MASK, PPC, {FRT, FRA, FRC}}, | |
8834 | -{"fmuls.", A(59,25,1), AFRB_MASK, PPC, {FRT, FRA, FRC}}, | |
8835 | - | |
8836 | -{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, | |
8837 | -{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, | |
8838 | - | |
8839 | -{"fmsubs", A(59,28,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8840 | -{"fmsubs.", A(59,28,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8841 | - | |
8842 | -{"fmadds", A(59,29,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8843 | -{"fmadds.", A(59,29,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8844 | - | |
8845 | -{"fnmsubs", A(59,30,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8846 | -{"fnmsubs.", A(59,30,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8847 | - | |
8848 | -{"fnmadds", A(59,31,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8849 | -{"fnmadds.", A(59,31,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8850 | - | |
8851 | -{"dmul", XRC(59,34,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8852 | -{"dmul.", XRC(59,34,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8853 | - | |
8854 | -{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, | |
8855 | -{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, | |
8856 | - | |
8857 | -{"dscli", ZRC(59,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, | |
8858 | -{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, | |
8859 | - | |
8860 | -{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}}, | |
8861 | -{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, {TE, FRT,FRB,RMC}}, | |
8862 | - | |
8863 | -{"dscri", ZRC(59,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, | |
8864 | -{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, | |
8865 | - | |
8866 | -{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, | |
8867 | -{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, | |
8868 | - | |
8869 | -{"dcmpo", X(59,130), X_MASK, POWER6, {BF, FRA, FRB}}, | |
8870 | - | |
8871 | -{"dtstex", X(59,162), X_MASK, POWER6, {BF, FRA, FRB}}, | |
8872 | -{"dtstdc", Z(59,194), Z_MASK, POWER6, {BF, FRA, DCM}}, | |
8873 | -{"dtstdg", Z(59,226), Z_MASK, POWER6, {BF, FRA, DGM}}, | |
8874 | - | |
8875 | -{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, | |
8876 | -{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, | |
8877 | - | |
8878 | -{"dctdp", XRC(59,258,0), X_MASK, POWER6, {FRT, FRB}}, | |
8879 | -{"dctdp.", XRC(59,258,1), X_MASK, POWER6, {FRT, FRB}}, | |
8880 | - | |
8881 | -{"dctfix", XRC(59,290,0), X_MASK, POWER6, {FRT, FRB}}, | |
8882 | -{"dctfix.", XRC(59,290,1), X_MASK, POWER6, {FRT, FRB}}, | |
8883 | - | |
8884 | -{"ddedpd", XRC(59,322,0), X_MASK, POWER6, {SP, FRT, FRB}}, | |
8885 | -{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, {SP, FRT, FRB}}, | |
8886 | - | |
8887 | -{"dxex", XRC(59,354,0), X_MASK, POWER6, {FRT, FRB}}, | |
8888 | -{"dxex.", XRC(59,354,1), X_MASK, POWER6, {FRT, FRB}}, | |
8889 | - | |
8890 | -{"dsub", XRC(59,514,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8891 | -{"dsub.", XRC(59,514,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8892 | - | |
8893 | -{"ddiv", XRC(59,546,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8894 | -{"ddiv.", XRC(59,546,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8895 | - | |
8896 | -{"dcmpu", X(59,642), X_MASK, POWER6, {BF, FRA, FRB}}, | |
8897 | - | |
8898 | -{"dtstsf", X(59,674), X_MASK, POWER6, {BF, FRA, FRB}}, | |
8899 | - | |
8900 | -{"drsp", XRC(59,770,0), X_MASK, POWER6, {FRT, FRB}}, | |
8901 | -{"drsp.", XRC(59,770,1), X_MASK, POWER6, {FRT, FRB}}, | |
8902 | - | |
8903 | -{"denbcd", XRC(59,834,0), X_MASK, POWER6, {S, FRT, FRB}}, | |
8904 | -{"denbcd.", XRC(59,834,1), X_MASK, POWER6, {S, FRT, FRB}}, | |
8905 | - | |
8906 | -{"diex", XRC(59,866,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8907 | -{"diex.", XRC(59,866,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8908 | - | |
8909 | -{"stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}}, | |
8910 | - | |
8911 | -{"psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}}, | |
8912 | - | |
8913 | -{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, | |
8914 | -{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, | |
8915 | -{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, {XT6, XA6, XB6, DM}}, | |
8916 | -{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6S}}, | |
8917 | -{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, | |
8918 | - | |
8919 | -{"psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}}, | |
8920 | - | |
8921 | -{"stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}}, | |
8922 | - | |
8923 | -{"stfdp", OP(61), OP_MASK, POWER6, {FRT, D, RA0}}, | |
8924 | - | |
8925 | -{"lde", DEO(62,0), DE_MASK, BOOKE64, {RT, DES, RA0}}, | |
8926 | -{"ldue", DEO(62,1), DE_MASK, BOOKE64, {RT, DES, RA0}}, | |
8927 | -{"lfse", DEO(62,4), DE_MASK, BOOKE64, {FRT, DES, RA0}}, | |
8928 | -{"lfsue", DEO(62,5), DE_MASK, BOOKE64, {FRT, DES, RAS}}, | |
8929 | -{"lfde", DEO(62,6), DE_MASK, BOOKE64, {FRT, DES, RA0}}, | |
8930 | -{"lfdue", DEO(62,7), DE_MASK, BOOKE64, {FRT, DES, RAS}}, | |
8931 | -{"stde", DEO(62,8), DE_MASK, BOOKE64, {RS, DES, RA0}}, | |
8932 | -{"stdue", DEO(62,9), DE_MASK, BOOKE64, {RS, DES, RAS}}, | |
8933 | -{"stfse", DEO(62,12), DE_MASK, BOOKE64, {FRS, DES, RA0}}, | |
8934 | -{"stfsue", DEO(62,13), DE_MASK, BOOKE64, {FRS, DES, RAS}}, | |
8935 | -{"stfde", DEO(62,14), DE_MASK, BOOKE64, {FRS, DES, RA0}}, | |
8936 | -{"stfdue", DEO(62,15), DE_MASK, BOOKE64, {FRS, DES, RAS}}, | |
8937 | - | |
8938 | -{"std", DSO(62,0), DS_MASK, PPC64, {RS, DS, RA0}}, | |
8939 | -{"stdu", DSO(62,1), DS_MASK, PPC64, {RS, DS, RAS}}, | |
8940 | -{"stq", DSO(62,2), DS_MASK, POWER4, {RSQ, DS, RA0}}, | |
8941 | - | |
8942 | -{"fcmpu", X(63,0), X_MASK|(3<<21), COM, {BF, FRA, FRB}}, | |
8943 | - | |
8944 | -{"daddq", XRC(63,2,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8945 | -{"daddq.", XRC(63,2,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8946 | - | |
8947 | -{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, | |
8948 | -{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, | |
8949 | - | |
8950 | -{"fcpsgn", XRC(63,8,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8951 | -{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
8952 | - | |
8953 | -{"frsp", XRC(63,12,0), XRA_MASK, COM, {FRT, FRB}}, | |
8954 | -{"frsp.", XRC(63,12,1), XRA_MASK, COM, {FRT, FRB}}, | |
8955 | - | |
8956 | -{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, {FRT, FRB}}, | |
8957 | -{"fcir", XRC(63,14,0), XRA_MASK, POWER2, {FRT, FRB}}, | |
8958 | -{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, {FRT, FRB}}, | |
8959 | -{"fcir.", XRC(63,14,1), XRA_MASK, POWER2, {FRT, FRB}}, | |
8960 | - | |
8961 | -{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, {FRT, FRB}}, | |
8962 | -{"fcirz", XRC(63,15,0), XRA_MASK, POWER2, {FRT, FRB}}, | |
8963 | -{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, {FRT, FRB}}, | |
8964 | -{"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, {FRT, FRB}}, | |
8965 | - | |
8966 | -{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, | |
8967 | -{"fd", A(63,18,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, | |
8968 | -{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, | |
8969 | -{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, | |
8970 | - | |
8971 | -{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, | |
8972 | -{"fs", A(63,20,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, | |
8973 | -{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, | |
8974 | -{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, | |
8975 | - | |
8976 | -{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, | |
8977 | -{"fa", A(63,21,0), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, | |
8978 | -{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, {FRT, FRA, FRB}}, | |
8979 | -{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, {FRT, FRA, FRB}}, | |
8980 | - | |
8981 | -{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}}, | |
8982 | -{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, {FRT, FRB}}, | |
8983 | - | |
8984 | -{"fsel", A(63,23,0), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8985 | -{"fsel.", A(63,23,1), A_MASK, PPC, {FRT, FRA, FRC, FRB}}, | |
8986 | - | |
8987 | -{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, | |
8988 | -{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, {FRT, FRB, A_L}}, | |
8989 | - | |
8990 | -{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}}, | |
8991 | -{"fm", A(63,25,0), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}}, | |
8992 | -{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, {FRT, FRA, FRC}}, | |
8993 | -{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, {FRT, FRA, FRC}}, | |
8994 | - | |
8995 | -{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, | |
8996 | -{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, {FRT, FRB, A_L}}, | |
8997 | - | |
8998 | -{"fmsub", A(63,28,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, | |
8999 | -{"fms", A(63,28,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, | |
9000 | -{"fmsub.", A(63,28,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, | |
9001 | -{"fms.", A(63,28,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, | |
9002 | - | |
9003 | -{"fmadd", A(63,29,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, | |
9004 | -{"fma", A(63,29,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, | |
9005 | -{"fmadd.", A(63,29,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, | |
9006 | -{"fma.", A(63,29,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, | |
9007 | - | |
9008 | -{"fnmsub", A(63,30,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, | |
9009 | -{"fnms", A(63,30,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, | |
9010 | -{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, | |
9011 | -{"fnms.", A(63,30,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, | |
9012 | - | |
9013 | -{"fnmadd", A(63,31,0), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, | |
9014 | -{"fnma", A(63,31,0), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, | |
9015 | -{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, {FRT, FRA, FRC, FRB}}, | |
9016 | -{"fnma.", A(63,31,1), A_MASK, PWRCOM, {FRT, FRA, FRC, FRB}}, | |
9017 | - | |
9018 | -{"fcmpo", X(63,32), X_MASK|(3<<21), COM, {BF, FRA, FRB}}, | |
9019 | - | |
9020 | -{"dmulq", XRC(63,34,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
9021 | -{"dmulq.", XRC(63,34,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
9022 | - | |
9023 | -{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, | |
9024 | -{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, {FRT, FRA, FRB, RMC}}, | |
9025 | - | |
9026 | -{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, {BT}}, | |
9027 | -{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, {BT}}, | |
9028 | - | |
9029 | -{"fneg", XRC(63,40,0), XRA_MASK, COM, {FRT, FRB}}, | |
9030 | -{"fneg.", XRC(63,40,1), XRA_MASK, COM, {FRT, FRB}}, | |
9031 | - | |
9032 | -{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, {BF, BFA}}, | |
9033 | - | |
9034 | -{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, | |
9035 | -{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, | |
9036 | - | |
9037 | -{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}}, | |
9038 | -{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, {TE, FRT, FRB, RMC}}, | |
9039 | - | |
9040 | -{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, {BT}}, | |
9041 | -{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, {BT}}, | |
9042 | - | |
9043 | -{"fmr", XRC(63,72,0), XRA_MASK, COM, {FRT, FRB}}, | |
9044 | -{"fmr.", XRC(63,72,1), XRA_MASK, COM, {FRT, FRB}}, | |
9045 | - | |
9046 | -{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, {FRT, FRA, SH16}}, | |
9047 | -{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, {FRT, FRA, SH16}}, | |
9048 | - | |
9049 | -{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, | |
9050 | -{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, | |
9051 | - | |
9052 | -{"dcmpoq", X(63,130), X_MASK, POWER6, {BF, FRA, FRB}}, | |
9053 | - | |
9054 | -{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}}, | |
9055 | -{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, {BFF, U, W}}, | |
9056 | - | |
9057 | -{"fnabs", XRC(63,136,0), XRA_MASK, COM, {FRT, FRB}}, | |
9058 | -{"fnabs.", XRC(63,136,1), XRA_MASK, COM, {FRT, FRB}}, | |
9059 | - | |
9060 | -{"dtstexq", X(63,162), X_MASK, POWER6, {BF, FRA, FRB}}, | |
9061 | -{"dtstdcq", Z(63,194), Z_MASK, POWER6, {BF, FRA, DCM}}, | |
9062 | -{"dtstdgq", Z(63,226), Z_MASK, POWER6, {BF, FRA, DGM}}, | |
9063 | - | |
9064 | -{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, | |
9065 | -{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, {R, FRT, FRB, RMC}}, | |
9066 | - | |
9067 | -{"dctqpq", XRC(63,258,0), X_MASK, POWER6, {FRT, FRB}}, | |
9068 | -{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, {FRT, FRB}}, | |
9069 | - | |
9070 | -{"fabs", XRC(63,264,0), XRA_MASK, COM, {FRT, FRB}}, | |
9071 | -{"fabs.", XRC(63,264,1), XRA_MASK, COM, {FRT, FRB}}, | |
9072 | - | |
9073 | -{"dctfixq", XRC(63,290,0), X_MASK, POWER6, {FRT, FRB}}, | |
9074 | -{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, {FRT, FRB}}, | |
9075 | - | |
9076 | -{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, {SP, FRT, FRB}}, | |
9077 | -{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, {SP, FRT, FRB}}, | |
9078 | - | |
9079 | -{"dxexq", XRC(63,354,0), X_MASK, POWER6, {FRT, FRB}}, | |
9080 | -{"dxexq.", XRC(63,354,1), X_MASK, POWER6, {FRT, FRB}}, | |
9081 | - | |
9082 | -{"frin", XRC(63,392,0), XRA_MASK, POWER5, {FRT, FRB}}, | |
9083 | -{"frin.", XRC(63,392,1), XRA_MASK, POWER5, {FRT, FRB}}, | |
9084 | -{"friz", XRC(63,424,0), XRA_MASK, POWER5, {FRT, FRB}}, | |
9085 | -{"friz.", XRC(63,424,1), XRA_MASK, POWER5, {FRT, FRB}}, | |
9086 | -{"frip", XRC(63,456,0), XRA_MASK, POWER5, {FRT, FRB}}, | |
9087 | -{"frip.", XRC(63,456,1), XRA_MASK, POWER5, {FRT, FRB}}, | |
9088 | -{"frim", XRC(63,488,0), XRA_MASK, POWER5, {FRT, FRB}}, | |
9089 | -{"frim.", XRC(63,488,1), XRA_MASK, POWER5, {FRT, FRB}}, | |
9090 | - | |
9091 | -{"dsubq", XRC(63,514,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
9092 | -{"dsubq.", XRC(63,514,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
9093 | - | |
9094 | -{"ddivq", XRC(63,546,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
9095 | -{"ddivq.", XRC(63,546,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
9096 | - | |
9097 | -{"mffs", XRC(63,583,0), XRARB_MASK, COM, {FRT}}, | |
9098 | -{"mffs.", XRC(63,583,1), XRARB_MASK, COM, {FRT}}, | |
9099 | - | |
9100 | -{"dcmpuq", X(63,642), X_MASK, POWER6, {BF, FRA, FRB}}, | |
9101 | - | |
9102 | -{"dtstsfq", X(63,674), X_MASK, POWER6, {BF, FRA, FRB}}, | |
9103 | - | |
9104 | -{"mtfsf", XFL(63,711,0), XFL_MASK, COM, {FLM, FRB, XFL_L, W}}, | |
9105 | -{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, {FLM, FRB, XFL_L, W}}, | |
9106 | - | |
9107 | -{"drdpq", XRC(63,770,0), X_MASK, POWER6, {FRT, FRB}}, | |
9108 | -{"drdpq.", XRC(63,770,1), X_MASK, POWER6, {FRT, FRB}}, | |
9109 | - | |
9110 | -{"dcffixq", XRC(63,802,0), X_MASK, POWER6, {FRT, FRB}}, | |
9111 | -{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, {FRT, FRB}}, | |
9112 | - | |
9113 | -{"fctid", XRC(63,814,0), XRA_MASK, PPC64, {FRT, FRB}}, | |
9114 | -{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, {FRT, FRB}}, | |
9115 | - | |
9116 | -{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, {FRT, FRB}}, | |
9117 | -{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, {FRT, FRB}}, | |
9118 | - | |
9119 | -{"denbcdq", XRC(63,834,0), X_MASK, POWER6, {S, FRT, FRB}}, | |
9120 | -{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, {S, FRT, FRB}}, | |
9121 | +{"attn", X(0,256), X_MASK, POWER4, PPCNONE, {0}}, | |
9122 | +{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9123 | +{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9124 | +{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9125 | +{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9126 | +{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9127 | +{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9128 | +{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9129 | +{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9130 | +{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9131 | +{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9132 | +{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9133 | +{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9134 | +{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9135 | +{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, | |
9136 | +{"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}}, | |
9137 | + | |
9138 | +{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9139 | +{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9140 | +{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9141 | +{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9142 | +{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9143 | +{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9144 | +{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9145 | +{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9146 | +{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9147 | +{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9148 | +{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9149 | +{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9150 | +{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9151 | +{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9152 | +{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9153 | +{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9154 | +{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9155 | +{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9156 | +{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9157 | +{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9158 | +{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9159 | +{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9160 | +{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9161 | +{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9162 | +{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9163 | +{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9164 | +{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, | |
9165 | +{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, | |
9166 | +{"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}}, | |
9167 | +{"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}}, | |
9168 | + | |
9169 | +{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, | |
9170 | +{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9171 | +{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9172 | +{"vrlb", VX (4, 4), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9173 | +{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9174 | +{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9175 | +{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9176 | +{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, | |
9177 | +{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9178 | +{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, | |
9179 | +{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9180 | +{"mulhhwu", XRC(4, 8,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9181 | +{"mulhhwu.", XRC(4, 8,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9182 | +{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9183 | +{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9184 | +{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9185 | +{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9186 | +{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
9187 | +{"machhwu", XO (4, 12,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9188 | +{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
9189 | +{"machhwu.", XO (4, 12,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9190 | +{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
9191 | +{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
9192 | +{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9193 | +{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9194 | +{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9195 | +{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9196 | +{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9197 | +{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9198 | +{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9199 | +{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9200 | +{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9201 | +{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9202 | +{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9203 | +{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9204 | +{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9205 | +{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9206 | +{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9207 | +{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9208 | +{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9209 | +{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9210 | +{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9211 | +{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9212 | +{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, | |
9213 | +{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, SHB}}, | |
9214 | +{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9215 | +{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}}, | |
9216 | +{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9217 | +{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}}, | |
9218 | +{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9219 | +{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9220 | +{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
9221 | +{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, | |
9222 | +{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9223 | +{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9224 | +{"ps_msub", A (4, 28,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9225 | +{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9226 | +{"ps_madd", A (4, 29,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9227 | +{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9228 | +{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9229 | +{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9230 | +{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9231 | +{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
9232 | +{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, | |
9233 | +{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9234 | +{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9235 | +{"vrlh", VX (4, 68), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9236 | +{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9237 | +{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9238 | +{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9239 | +{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, | |
9240 | +{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9241 | +{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, | |
9242 | +{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9243 | +{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9244 | +{"mulhhw", XRC(4, 40,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9245 | +{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9246 | +{"mulhhw.", XRC(4, 40,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9247 | +{"machhw", XO (4, 44,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9248 | +{"machhw.", XO (4, 44,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9249 | +{"nmachhw", XO (4, 46,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9250 | +{"nmachhw.", XO (4, 46,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9251 | +{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, | |
9252 | +{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9253 | +{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9254 | +{"vrlw", VX (4, 132), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9255 | +{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9256 | +{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9257 | +{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9258 | +{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9259 | +{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9260 | +{"machhwsu", XO (4, 76,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9261 | +{"machhwsu.", XO (4, 76,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9262 | +{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, | |
9263 | +{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9264 | +{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9265 | +{"machhws", XO (4, 108,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9266 | +{"machhws.", XO (4, 108,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9267 | +{"nmachhws", XO (4, 110,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9268 | +{"nmachhws.", XO (4, 110,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9269 | +{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9270 | +{"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9271 | +{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9272 | +{"vrefp", VX (4, 266), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9273 | +{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9274 | +{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9275 | +{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9276 | +{"mulchwu", XRC(4, 136,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9277 | +{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9278 | +{"mulchwu.", XRC(4, 136,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9279 | +{"macchwu", XO (4, 140,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9280 | +{"macchwu.", XO (4, 140,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9281 | +{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9282 | +{"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9283 | +{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9284 | +{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9285 | +{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9286 | +{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9287 | +{"mulchw", XRC(4, 168,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9288 | +{"mulchw.", XRC(4, 168,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9289 | +{"macchw", XO (4, 172,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9290 | +{"macchw.", XO (4, 172,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9291 | +{"nmacchw", XO (4, 174,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9292 | +{"nmacchw.", XO (4, 174,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9293 | +{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9294 | +{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9295 | +{"vslw", VX (4, 388), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9296 | +{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9297 | +{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9298 | +{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9299 | +{"macchwsu", XO (4, 204,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9300 | +{"macchwsu.", XO (4, 204,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9301 | +{"vsl", VX (4, 452), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9302 | +{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9303 | +{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9304 | +{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9305 | +{"macchws", XO (4, 236,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9306 | +{"macchws.", XO (4, 236,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9307 | +{"nmacchws", XO (4, 238,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9308 | +{"nmacchws.", XO (4, 238,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9309 | +{"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9310 | +{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9311 | +{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}}, | |
9312 | +{"vminub", VX (4, 514), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9313 | +{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9314 | +{"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}}, | |
9315 | +{"vsrb", VX (4, 516), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9316 | +{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, UIMM, RB}}, | |
9317 | +{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}}, | |
9318 | +{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9319 | +{"evabs", VX (4, 520), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9320 | +{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9321 | +{"evneg", VX (4, 521), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9322 | +{"evextsb", VX (4, 522), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9323 | +{"vrfin", VX (4, 522), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9324 | +{"evextsh", VX (4, 523), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9325 | +{"evrndw", VX (4, 524), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9326 | +{"vspltb", VX (4, 524), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, | |
9327 | +{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9328 | +{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9329 | +{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9330 | +{"brinc", VX (4, 527), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9331 | +{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9332 | +{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, | |
9333 | +{"evand", VX (4, 529), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9334 | +{"evandc", VX (4, 530), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9335 | +{"evxor", VX (4, 534), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9336 | +{"evmr", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}}, | |
9337 | +{"evor", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9338 | +{"evnor", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9339 | +{"evnot", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}}, | |
9340 | +{"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, | |
9341 | +{"eveqv", VX (4, 537), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9342 | +{"evorc", VX (4, 539), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9343 | +{"evnand", VX (4, 542), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9344 | +{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9345 | +{"evsrws", VX (4, 545), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9346 | +{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, | |
9347 | +{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, | |
9348 | +{"evslw", VX (4, 548), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9349 | +{"evslwi", VX (4, 550), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, | |
9350 | +{"evrlw", VX (4, 552), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9351 | +{"evsplati", VX (4, 553), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}}, | |
9352 | +{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, | |
9353 | +{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}}, | |
9354 | +{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9355 | +{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9356 | +{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9357 | +{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9358 | +{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9359 | +{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9360 | +{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9361 | +{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9362 | +{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9363 | +{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, | |
9364 | +{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9365 | +{"vminuh", VX (4, 578), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9366 | +{"vsrh", VX (4, 580), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9367 | +{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9368 | +{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9369 | +{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9370 | +{"vsplth", VX (4, 588), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, | |
9371 | +{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9372 | +{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, | |
9373 | +{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, PPCNONE, {RS, RA, RB, CRFS}}, | |
9374 | +{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, | |
9375 | +{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9376 | +{"vadduws", VX (4, 640), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9377 | +{"evfssub", VX (4, 641), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9378 | +{"vminuw", VX (4, 642), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9379 | +{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9380 | +{"vsrw", VX (4, 644), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9381 | +{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9382 | +{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9383 | +{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9384 | +{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9385 | +{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9386 | +{"vrfip", VX (4, 650), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9387 | +{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9388 | +{"vspltw", VX (4, 652), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, | |
9389 | +{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9390 | +{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9391 | +{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9392 | +{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9393 | +{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9394 | +{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9395 | +{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9396 | +{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9397 | +{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9398 | +{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9399 | +{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9400 | +{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9401 | +{"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, | |
9402 | +{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, | |
9403 | +{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9404 | +{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9405 | +{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, | |
9406 | +{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, | |
9407 | +{"efsadd", VX (4, 704), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, | |
9408 | +{"efssub", VX (4, 705), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, | |
9409 | +{"efsabs", VX (4, 708), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, | |
9410 | +{"vsr", VX (4, 708), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9411 | +{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, | |
9412 | +{"efsneg", VX (4, 710), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, | |
9413 | +{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9414 | +{"efsmul", VX (4, 712), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, | |
9415 | +{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, | |
9416 | +{"vrfim", VX (4, 714), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9417 | +{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9418 | +{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9419 | +{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9420 | +{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9421 | +{"efscfd", VX (4, 719), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9422 | +{"efscfui", VX (4, 720), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9423 | +{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9424 | +{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9425 | +{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9426 | +{"efsctui", VX (4, 724), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9427 | +{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9428 | +{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9429 | +{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9430 | +{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9431 | +{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, | |
9432 | +{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9433 | +{"efststgt", VX (4, 732), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9434 | +{"efststlt", VX (4, 733), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9435 | +{"efststeq", VX (4, 734), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9436 | +{"efdadd", VX (4, 736), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, | |
9437 | +{"efdsub", VX (4, 737), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, | |
9438 | +{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9439 | +{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9440 | +{"efdabs", VX (4, 740), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, | |
9441 | +{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, | |
9442 | +{"efdneg", VX (4, 742), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, | |
9443 | +{"efdmul", VX (4, 744), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, | |
9444 | +{"efddiv", VX (4, 745), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, | |
9445 | +{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9446 | +{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9447 | +{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9448 | +{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9449 | +{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9450 | +{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9451 | +{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9452 | +{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9453 | +{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9454 | +{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9455 | +{"efdctui", VX (4, 756), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9456 | +{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9457 | +{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9458 | +{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9459 | +{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9460 | +{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, | |
9461 | +{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, | |
9462 | +{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9463 | +{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9464 | +{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, | |
9465 | +{"evlddx", VX (4, 768), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9466 | +{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9467 | +{"evldd", VX (4, 769), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
9468 | +{"evldwx", VX (4, 770), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9469 | +{"vminsb", VX (4, 770), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9470 | +{"evldw", VX (4, 771), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
9471 | +{"evldhx", VX (4, 772), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9472 | +{"vsrab", VX (4, 772), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9473 | +{"evldh", VX (4, 773), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
9474 | +{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9475 | +{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9476 | +{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9477 | +{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, | |
9478 | +{"vcfux", VX (4, 778), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, | |
9479 | +{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9480 | +{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, | |
9481 | +{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, | |
9482 | +{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9483 | +{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9484 | +{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, | |
9485 | +{"mullhwu", XRC(4, 392,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9486 | +{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9487 | +{"mullhwu.", XRC(4, 392,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9488 | +{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
9489 | +{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9490 | +{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
9491 | +{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9492 | +{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
9493 | +{"maclhwu", XO (4, 396,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9494 | +{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9495 | +{"maclhwu.", XO (4, 396,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9496 | +{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
9497 | +{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9498 | +{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
9499 | +{"evstddx", VX (4, 800), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9500 | +{"evstdd", VX (4, 801), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
9501 | +{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9502 | +{"evstdw", VX (4, 803), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
9503 | +{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9504 | +{"evstdh", VX (4, 805), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, | |
9505 | +{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9506 | +{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
9507 | +{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9508 | +{"evstwho", VX (4, 821), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
9509 | +{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9510 | +{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
9511 | +{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9512 | +{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, | |
9513 | +{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9514 | +{"vminsh", VX (4, 834), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9515 | +{"vsrah", VX (4, 836), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9516 | +{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9517 | +{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9518 | +{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, | |
9519 | +{"vspltish", VX (4, 844), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, | |
9520 | +{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9521 | +{"mullhw", XRC(4, 424,0), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9522 | +{"mullhw.", XRC(4, 424,1), X_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9523 | +{"maclhw", XO (4, 428,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9524 | +{"maclhw.", XO (4, 428,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9525 | +{"nmaclhw", XO (4, 430,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9526 | +{"nmaclhw.", XO (4, 430,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9527 | +{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9528 | +{"vminsw", VX (4, 898), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9529 | +{"vsraw", VX (4, 900), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9530 | +{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9531 | +{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, | |
9532 | +{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, | |
9533 | +{"maclhwsu", XO (4, 460,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9534 | +{"maclhwsu.", XO (4, 460,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9535 | +{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9536 | +{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, | |
9537 | +{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, | |
9538 | +{"maclhws", XO (4, 492,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9539 | +{"maclhws.", XO (4, 492,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9540 | +{"nmaclhws", XO (4, 494,0,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9541 | +{"nmaclhws.", XO (4, 494,0,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9542 | +{"vsububm", VX (4,1024), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9543 | +{"vavgub", VX (4,1026), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9544 | +{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9545 | +{"vand", VX (4,1028), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9546 | +{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9547 | +{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9548 | +{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9549 | +{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9550 | +{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9551 | +{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9552 | +{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9553 | +{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9554 | +{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9555 | +{"vslo", VX (4,1036), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9556 | +{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9557 | +{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9558 | +{"machhwuo", XO (4, 12,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9559 | +{"machhwuo.", XO (4, 12,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9560 | +{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9561 | +{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9562 | +{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9563 | +{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9564 | +{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9565 | +{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9566 | +{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9567 | +{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9568 | +{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9569 | +{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9570 | +{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9571 | +{"vavguh", VX (4,1090), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9572 | +{"vandc", VX (4,1092), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9573 | +{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9574 | +{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9575 | +{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9576 | +{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9577 | +{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9578 | +{"vminfp", VX (4,1098), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9579 | +{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9580 | +{"vsro", VX (4,1100), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9581 | +{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9582 | +{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9583 | +{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9584 | +{"machhwo", XO (4, 44,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9585 | +{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9586 | +{"machhwo.", XO (4, 44,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9587 | +{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9588 | +{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9589 | +{"nmachhwo", XO (4, 46,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9590 | +{"nmachhwo.", XO (4, 46,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9591 | +{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9592 | +{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9593 | +{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9594 | +{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9595 | +{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9596 | +{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9597 | +{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9598 | +{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9599 | +{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9600 | +{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9601 | +{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9602 | +{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9603 | +{"vavguw", VX (4,1154), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9604 | +{"vor", VX (4,1156), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9605 | +{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9606 | +{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9607 | +{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9608 | +{"machhwsuo", XO (4, 76,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9609 | +{"machhwsuo.", XO (4, 76,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9610 | +{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9611 | +{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9612 | +{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9613 | +{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9614 | +{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9615 | +{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9616 | +{"evmra", VX (4,1220), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9617 | +{"vxor", VX (4,1220), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9618 | +{"evdivws", VX (4,1222), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9619 | +{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9620 | +{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9621 | +{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9622 | +{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9623 | +{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9624 | +{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9625 | +{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9626 | +{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, | |
9627 | +{"machhwso", XO (4, 108,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9628 | +{"machhwso.", XO (4, 108,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9629 | +{"nmachhwso", XO (4, 110,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9630 | +{"nmachhwso.", XO (4, 110,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9631 | +{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9632 | +{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, | |
9633 | +{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9634 | +{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9635 | +{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9636 | +{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9637 | +{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9638 | +{"vnor", VX (4,1284), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9639 | +{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9640 | +{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9641 | +{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9642 | +{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9643 | +{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9644 | +{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9645 | +{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9646 | +{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9647 | +{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9648 | +{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9649 | +{"macchwuo", XO (4, 140,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9650 | +{"macchwuo.", XO (4, 140,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9651 | +{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9652 | +{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9653 | +{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9654 | +{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9655 | +{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9656 | +{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9657 | +{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9658 | +{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9659 | +{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9660 | +{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9661 | +{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9662 | +{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9663 | +{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9664 | +{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9665 | +{"macchwo", XO (4, 172,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9666 | +{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9667 | +{"macchwo.", XO (4, 172,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9668 | +{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9669 | +{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9670 | +{"nmacchwo", XO (4, 174,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9671 | +{"nmacchwo.", XO (4, 174,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9672 | +{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9673 | +{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9674 | +{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9675 | +{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9676 | +{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9677 | +{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9678 | +{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9679 | +{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9680 | +{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9681 | +{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9682 | +{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9683 | +{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9684 | +{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9685 | +{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9686 | +{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9687 | +{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9688 | +{"macchwsuo", XO (4, 204,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9689 | +{"macchwsuo.", XO (4, 204,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9690 | +{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9691 | +{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9692 | +{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9693 | +{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9694 | +{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9695 | +{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9696 | +{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9697 | +{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9698 | +{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9699 | +{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9700 | +{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPCNONE, {URT, URA, URB}}, | |
9701 | +{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9702 | +{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9703 | +{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9704 | +{"macchwso", XO (4, 236,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9705 | +{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9706 | +{"macchwso.", XO (4, 236,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9707 | +{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9708 | +{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, | |
9709 | +{"nmacchwso", XO (4, 238,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9710 | +{"nmacchwso.", XO (4, 238,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9711 | +{"vsububs", VX (4,1536), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9712 | +{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, PPCNONE, {VD}}, | |
9713 | +{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9714 | +{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9715 | +{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9716 | +{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9717 | +{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9718 | +{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, PPCNONE, {VB}}, | |
9719 | +{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9720 | +{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9721 | +{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9722 | +{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9723 | +{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9724 | +{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9725 | +{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9726 | +{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9727 | +{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9728 | +{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9729 | +{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9730 | +{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9731 | +{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9732 | +{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9733 | +{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9734 | +{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9735 | +{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9736 | +{"maclhwuo", XO (4, 396,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9737 | +{"maclhwuo.", XO (4, 396,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9738 | +{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9739 | +{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9740 | +{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9741 | +{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9742 | +{"maclhwo", XO (4, 428,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9743 | +{"maclhwo.", XO (4, 428,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9744 | +{"nmaclhwo", XO (4, 430,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9745 | +{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9746 | +{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9747 | +{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9748 | +{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9749 | +{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9750 | +{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9751 | +{"maclhwsuo", XO (4, 460,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9752 | +{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9753 | +{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, | |
9754 | +{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9755 | +{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPCNONE, {URT, URA, URB}}, | |
9756 | +{"maclhwso", XO (4, 492,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9757 | +{"maclhwso.", XO (4, 492,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9758 | +{"nmaclhwso", XO (4, 494,1,0),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9759 | +{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, PPC405|PPC440, PPCNONE, {RT, RA, RB}}, | |
9760 | +{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}}, | |
9761 | + | |
9762 | +{"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, | |
9763 | +{"muli", OP(7), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, | |
9764 | + | |
9765 | +{"subfic", OP(8), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, | |
9766 | +{"sfi", OP(8), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, | |
9767 | + | |
9768 | +{"dozi", OP(9), OP_MASK, M601, PPCNONE, {RT, RA, SI}}, | |
9769 | + | |
9770 | +{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, UI}}, | |
9771 | +{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, UI}}, | |
9772 | +{"cmpli", OP(10), OP_MASK, PPC, PPCNONE, {BF, L, RA, UI}}, | |
9773 | +{"cmpli", OP(10), OP_MASK, PWRCOM, PPCNONE, {BF, RA, UI}}, | |
9774 | + | |
9775 | +{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCNONE, {OBF, RA, SI}}, | |
9776 | +{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCNONE, {OBF, RA, SI}}, | |
9777 | +{"cmpi", OP(11), OP_MASK, PPC, PPCNONE, {BF, L, RA, SI}}, | |
9778 | +{"cmpi", OP(11), OP_MASK, PWRCOM, PPCNONE, {BF, RA, SI}}, | |
9779 | + | |
9780 | +{"addic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, | |
9781 | +{"ai", OP(12), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, | |
9782 | +{"subic", OP(12), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}}, | |
9783 | + | |
9784 | +{"addic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, | |
9785 | +{"ai.", OP(13), OP_MASK, PWRCOM, PPCNONE, {RT, RA, SI}}, | |
9786 | +{"subic.", OP(13), OP_MASK, PPCCOM, PPCNONE, {RT, RA, NSI}}, | |
9787 | + | |
9788 | +{"li", OP(14), DRA_MASK, PPCCOM, PPCNONE, {RT, SI}}, | |
9789 | +{"lil", OP(14), DRA_MASK, PWRCOM, PPCNONE, {RT, SI}}, | |
9790 | +{"addi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SI}}, | |
9791 | +{"cal", OP(14), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, | |
9792 | +{"subi", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}}, | |
9793 | +{"la", OP(14), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}}, | |
9794 | + | |
9795 | +{"lis", OP(15), DRA_MASK, PPCCOM, PPCNONE, {RT, SISIGNOPT}}, | |
9796 | +{"liu", OP(15), DRA_MASK, PWRCOM, PPCNONE, {RT, SISIGNOPT}}, | |
9797 | +{"addis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, | |
9798 | +{"cau", OP(15), OP_MASK, PWRCOM, PPCNONE, {RT, RA0, SISIGNOPT}}, | |
9799 | +{"subis", OP(15), OP_MASK, PPCCOM, PPCNONE, {RT, RA0, NSI}}, | |
9800 | + | |
9801 | +{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, | |
9802 | +{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, | |
9803 | +{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}}, | |
9804 | +{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}}, | |
9805 | +{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, | |
9806 | +{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, | |
9807 | +{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BD}}, | |
9808 | +{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BD}}, | |
9809 | +{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, | |
9810 | +{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, | |
9811 | +{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}}, | |
9812 | +{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}}, | |
9813 | +{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, | |
9814 | +{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, | |
9815 | +{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDA}}, | |
9816 | +{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCNONE, {BDA}}, | |
9817 | +{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, | |
9818 | +{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, | |
9819 | +{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCNONE, {BD}}, | |
9820 | +{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDM}}, | |
9821 | +{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDP}}, | |
9822 | +{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCNONE, {BD}}, | |
9823 | +{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, | |
9824 | +{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, | |
9825 | +{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCNONE, {BDA}}, | |
9826 | +{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDMA}}, | |
9827 | +{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCNONE, {BDPA}}, | |
9828 | +{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCNONE, {BDA}}, | |
9829 | + | |
9830 | +{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9831 | +{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9832 | +{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9833 | +{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9834 | +{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9835 | +{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9836 | +{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9837 | +{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9838 | +{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9839 | +{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9840 | +{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9841 | +{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9842 | +{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9843 | +{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9844 | +{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9845 | +{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9846 | +{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9847 | +{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9848 | +{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9849 | +{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9850 | +{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9851 | +{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9852 | +{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9853 | +{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9854 | +{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9855 | +{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9856 | +{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9857 | +{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9858 | +{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9859 | +{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9860 | +{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9861 | +{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9862 | +{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9863 | +{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9864 | +{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9865 | +{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9866 | +{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9867 | +{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9868 | +{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9869 | +{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9870 | +{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9871 | +{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9872 | +{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9873 | +{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9874 | +{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9875 | +{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9876 | +{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9877 | +{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9878 | +{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9879 | +{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9880 | +{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9881 | +{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9882 | +{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9883 | +{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9884 | +{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9885 | +{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9886 | +{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9887 | +{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9888 | +{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9889 | +{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9890 | +{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9891 | +{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9892 | +{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9893 | +{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9894 | +{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9895 | +{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, | |
9896 | +{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9897 | +{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9898 | +{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9899 | +{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9900 | +{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9901 | +{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, | |
9902 | +{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9903 | +{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9904 | +{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9905 | +{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9906 | +{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9907 | +{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, | |
9908 | +{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9909 | +{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9910 | +{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9911 | +{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9912 | +{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9913 | +{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, | |
9914 | + | |
9915 | +{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9916 | +{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9917 | +{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9918 | +{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9919 | +{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9920 | +{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9921 | +{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9922 | +{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9923 | +{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9924 | +{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9925 | +{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9926 | +{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9927 | +{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9928 | +{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9929 | +{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9930 | +{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9931 | +{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9932 | +{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9933 | +{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9934 | +{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9935 | +{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9936 | +{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9937 | +{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9938 | +{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9939 | +{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9940 | +{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9941 | +{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9942 | +{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9943 | +{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9944 | +{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9945 | +{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9946 | +{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9947 | +{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9948 | +{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9949 | +{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9950 | +{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9951 | +{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9952 | +{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9953 | +{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9954 | +{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9955 | +{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9956 | +{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, | |
9957 | +{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9958 | +{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9959 | +{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCNONE, {CR, BD}}, | |
9960 | +{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDM}}, | |
9961 | +{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDP}}, | |
9962 | +{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BD}}, | |
9963 | +{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9964 | +{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9965 | +{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9966 | +{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9967 | +{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9968 | +{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, | |
9969 | +{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9970 | +{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9971 | +{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCNONE, {CR, BDA}}, | |
9972 | +{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDMA}}, | |
9973 | +{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDPA}}, | |
9974 | +{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCNONE, {CR, BDA}}, | |
9975 | + | |
9976 | +{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, | |
9977 | +{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, | |
9978 | +{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
9979 | +{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, | |
9980 | +{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, | |
9981 | +{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
9982 | +{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, | |
9983 | +{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, | |
9984 | +{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
9985 | +{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, | |
9986 | +{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, | |
9987 | +{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
9988 | +{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, | |
9989 | +{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, | |
9990 | +{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
9991 | +{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, | |
9992 | +{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, | |
9993 | +{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
9994 | +{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, | |
9995 | +{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, | |
9996 | +{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
9997 | +{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, | |
9998 | +{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, | |
9999 | +{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
10000 | + | |
10001 | +{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, | |
10002 | +{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, | |
10003 | +{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
10004 | +{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, | |
10005 | +{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, | |
10006 | +{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, | |
10007 | +{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
10008 | +{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, | |
10009 | +{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, | |
10010 | +{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, | |
10011 | +{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
10012 | +{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, | |
10013 | +{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, | |
10014 | +{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, | |
10015 | +{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
10016 | +{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, | |
10017 | + | |
10018 | +{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, | |
10019 | +{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, | |
10020 | +{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
10021 | +{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, | |
10022 | +{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, | |
10023 | +{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
10024 | +{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, | |
10025 | +{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, | |
10026 | +{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
10027 | +{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, | |
10028 | +{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, | |
10029 | +{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
10030 | +{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, | |
10031 | +{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, | |
10032 | +{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
10033 | +{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDM}}, | |
10034 | +{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDP}}, | |
10035 | +{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
10036 | +{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, | |
10037 | +{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, | |
10038 | +{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
10039 | +{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDMA}}, | |
10040 | +{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, POWER4, {BI, BDPA}}, | |
10041 | +{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
10042 | + | |
10043 | +{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, | |
10044 | +{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, | |
10045 | +{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
10046 | +{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, | |
10047 | +{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDM}}, | |
10048 | +{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDP}}, | |
10049 | +{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BD}}, | |
10050 | +{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BD}}, | |
10051 | +{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, | |
10052 | +{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, | |
10053 | +{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
10054 | +{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, | |
10055 | +{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDMA}}, | |
10056 | +{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDPA}}, | |
10057 | +{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCNONE, {BI, BDA}}, | |
10058 | +{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCNONE, {BI, BDA}}, | |
10059 | + | |
10060 | +{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}}, | |
10061 | +{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}}, | |
10062 | +{"bc", B(16,0,0), B_MASK, COM, PPCNONE, {BO, BI, BD}}, | |
10063 | +{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDM}}, | |
10064 | +{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDP}}, | |
10065 | +{"bcl", B(16,0,1), B_MASK, COM, PPCNONE, {BO, BI, BD}}, | |
10066 | +{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}}, | |
10067 | +{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}}, | |
10068 | +{"bca", B(16,1,0), B_MASK, COM, PPCNONE, {BO, BI, BDA}}, | |
10069 | +{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDMA}}, | |
10070 | +{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCNONE, {BOE, BI, BDPA}}, | |
10071 | +{"bcla", B(16,1,1), B_MASK, COM, PPCNONE, {BO, BI, BDA}}, | |
10072 | + | |
10073 | +{"svc", SC(17,0,0), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}}, | |
10074 | +{"svcl", SC(17,0,1), SC_MASK, POWER, PPCNONE, {SVC_LEV, FL1, FL2}}, | |
10075 | +{"sc", SC(17,1,0), SC_MASK, PPC, PPCNONE, {LEV}}, | |
10076 | +{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCNONE, {SV}}, | |
10077 | +{"svcla", SC(17,1,1), SC_MASK, POWER, PPCNONE, {SV}}, | |
10078 | + | |
10079 | +{"b", B(18,0,0), B_MASK, COM, PPCNONE, {LI}}, | |
10080 | +{"bl", B(18,0,1), B_MASK, COM, PPCNONE, {LI}}, | |
10081 | +{"ba", B(18,1,0), B_MASK, COM, PPCNONE, {LIA}}, | |
10082 | +{"bla", B(18,1,1), B_MASK, COM, PPCNONE, {LIA}}, | |
10083 | + | |
10084 | +{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, | |
10085 | + | |
10086 | +{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, | |
10087 | +{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, | |
10088 | +{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, | |
10089 | +{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, | |
10090 | +{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, | |
10091 | +{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, | |
10092 | +{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, | |
10093 | +{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, | |
10094 | +{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, | |
10095 | +{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, | |
10096 | +{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, | |
10097 | +{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, POWER4, {0}}, | |
10098 | +{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, | |
10099 | +{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}}, | |
10100 | +{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, | |
10101 | +{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCNONE, {0}}, | |
10102 | +{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, | |
10103 | +{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, | |
10104 | +{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, | |
10105 | +{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, | |
10106 | +{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, | |
10107 | +{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, | |
10108 | +{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, | |
10109 | +{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, PPCNONE, {0}}, | |
10110 | + | |
10111 | +{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10112 | +{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10113 | +{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10114 | +{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10115 | +{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10116 | +{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10117 | +{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10118 | +{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10119 | +{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10120 | +{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10121 | +{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10122 | +{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10123 | +{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10124 | +{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10125 | +{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10126 | +{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10127 | +{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10128 | +{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10129 | +{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10130 | +{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10131 | +{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10132 | +{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10133 | +{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10134 | +{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10135 | +{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10136 | +{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10137 | +{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10138 | +{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10139 | +{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10140 | +{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10141 | +{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10142 | +{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10143 | +{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10144 | +{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10145 | +{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10146 | +{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10147 | +{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10148 | +{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10149 | +{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10150 | +{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10151 | +{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10152 | +{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10153 | +{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10154 | +{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10155 | +{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10156 | +{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10157 | +{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10158 | +{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10159 | +{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10160 | +{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10161 | +{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10162 | +{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10163 | +{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10164 | +{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10165 | +{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10166 | +{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10167 | +{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10168 | +{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10169 | +{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10170 | +{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10171 | +{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10172 | +{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10173 | +{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10174 | +{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10175 | +{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10176 | +{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10177 | +{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10178 | +{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10179 | +{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10180 | +{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10181 | +{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10182 | +{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10183 | +{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10184 | +{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10185 | +{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10186 | +{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10187 | +{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10188 | +{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10189 | +{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10190 | +{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10191 | +{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10192 | +{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10193 | +{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10194 | +{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10195 | +{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10196 | +{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10197 | +{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10198 | +{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10199 | +{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10200 | +{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10201 | +{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10202 | +{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10203 | +{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10204 | +{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10205 | +{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10206 | +{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10207 | +{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10208 | +{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10209 | +{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10210 | +{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10211 | +{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10212 | +{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10213 | +{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10214 | +{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10215 | +{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10216 | +{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10217 | +{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10218 | +{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCNONE, {CR}}, | |
10219 | +{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10220 | +{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10221 | +{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10222 | +{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10223 | +{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10224 | +{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10225 | +{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10226 | +{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10227 | +{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10228 | +{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10229 | +{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10230 | +{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10231 | +{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10232 | +{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10233 | +{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10234 | +{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10235 | +{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10236 | +{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10237 | +{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10238 | +{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10239 | +{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10240 | +{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10241 | +{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10242 | +{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10243 | +{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10244 | +{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10245 | +{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10246 | +{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10247 | +{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10248 | +{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10249 | +{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10250 | +{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10251 | + | |
10252 | +{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10253 | +{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10254 | +{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10255 | +{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10256 | +{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10257 | +{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10258 | +{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10259 | +{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10260 | +{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10261 | +{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10262 | +{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10263 | +{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10264 | +{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10265 | +{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10266 | +{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, | |
10267 | +{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10268 | +{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10269 | +{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, | |
10270 | +{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10271 | +{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10272 | +{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10273 | +{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10274 | +{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10275 | +{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10276 | +{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10277 | +{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10278 | +{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10279 | +{"bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10280 | +{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10281 | +{"bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10282 | +{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10283 | +{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10284 | +{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10285 | +{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10286 | +{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10287 | +{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10288 | +{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10289 | +{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10290 | +{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, | |
10291 | +{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10292 | +{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10293 | +{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCNONE, {BI}}, | |
10294 | +{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10295 | +{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10296 | +{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10297 | +{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10298 | +{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10299 | +{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10300 | + | |
10301 | +{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
10302 | +{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
10303 | +{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
10304 | +{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
10305 | +{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, | |
10306 | +{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, | |
10307 | +{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, | |
10308 | +{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, | |
10309 | + | |
10310 | +{"rfid", XL(19,18), 0xffffffff, PPC64, PPCNONE, {0}}, | |
10311 | + | |
10312 | +{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}}, | |
10313 | +{"crnor", XL(19,33), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
10314 | +{"rfmci", X(19,38), 0xffffffff, PPCRFMCI, PPCNONE, {0}}, | |
10315 | + | |
10316 | +{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCNONE, {0}}, | |
10317 | +{"rfi", XL(19,50), 0xffffffff, COM, PPCNONE, {0}}, | |
10318 | +{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300, PPCNONE, {0}}, | |
10319 | + | |
10320 | +{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCNONE, {0}}, | |
10321 | + | |
10322 | +{"rfgi", XL(19,102), 0xffffffff, E500MC, PPCNONE, {0}}, | |
10323 | + | |
10324 | +{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
10325 | + | |
10326 | +{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}}, | |
10327 | +{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}}, | |
10328 | + | |
10329 | +{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}}, | |
10330 | +{"crxor", XL(19,193), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
10331 | + | |
10332 | +{"dnh", X(19,198), X_MASK, E500MC, PPCNONE, {DUI, DUIS}}, | |
10333 | + | |
10334 | +{"crnand", XL(19,225), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
10335 | + | |
10336 | +{"crand", XL(19,257), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
10337 | + | |
10338 | +{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPCNONE, {0}}, | |
10339 | + | |
10340 | +{"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}}, | |
10341 | +{"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
10342 | + | |
10343 | +{"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}}, | |
10344 | + | |
10345 | +{"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
10346 | + | |
10347 | +{"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}}, | |
10348 | + | |
10349 | +{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}}, | |
10350 | +{"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, | |
10351 | + | |
10352 | +{"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}}, | |
10353 | +{"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}}, | |
10354 | + | |
10355 | +{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}}, | |
10356 | +{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}}, | |
10357 | + | |
10358 | +{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10359 | +{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10360 | +{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10361 | +{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10362 | +{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10363 | +{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10364 | +{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10365 | +{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10366 | +{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10367 | +{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10368 | +{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10369 | +{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10370 | +{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10371 | +{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10372 | +{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10373 | +{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10374 | +{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10375 | +{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10376 | +{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10377 | +{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10378 | +{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10379 | +{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10380 | +{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10381 | +{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10382 | +{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10383 | +{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10384 | +{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10385 | +{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10386 | +{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10387 | +{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10388 | +{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10389 | +{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10390 | +{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10391 | +{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10392 | +{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10393 | +{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10394 | +{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10395 | +{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10396 | +{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10397 | +{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10398 | +{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10399 | +{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10400 | +{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10401 | +{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10402 | +{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10403 | +{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10404 | +{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10405 | +{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10406 | +{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10407 | +{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10408 | +{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10409 | +{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10410 | +{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10411 | +{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10412 | +{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10413 | +{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10414 | +{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10415 | +{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10416 | +{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10417 | +{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10418 | +{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10419 | +{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10420 | +{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10421 | +{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10422 | +{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10423 | +{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10424 | +{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10425 | +{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10426 | +{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10427 | +{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10428 | +{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10429 | +{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10430 | +{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10431 | +{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10432 | +{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10433 | +{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10434 | +{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10435 | +{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10436 | +{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10437 | +{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10438 | +{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10439 | +{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10440 | +{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10441 | +{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10442 | +{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10443 | +{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10444 | +{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10445 | +{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10446 | +{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCNONE, {CR}}, | |
10447 | +{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10448 | +{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10449 | +{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10450 | +{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10451 | +{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10452 | +{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10453 | +{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10454 | +{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10455 | +{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10456 | +{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10457 | +{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, POWER4, {CR}}, | |
10458 | +{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10459 | +{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10460 | +{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10461 | +{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10462 | +{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10463 | +{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10464 | +{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10465 | +{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10466 | +{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10467 | +{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10468 | +{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10469 | +{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10470 | +{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10471 | +{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10472 | +{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10473 | +{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10474 | +{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10475 | +{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10476 | +{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10477 | +{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, PPCNONE, {CR}}, | |
10478 | + | |
10479 | +{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10480 | +{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10481 | +{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10482 | +{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10483 | +{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10484 | +{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10485 | +{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10486 | +{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10487 | +{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10488 | +{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10489 | +{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10490 | +{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10491 | +{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCNONE, {BI}}, | |
10492 | +{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10493 | +{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10494 | +{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, POWER4, {BI}}, | |
10495 | +{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10496 | +{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10497 | +{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10498 | +{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, PPCNONE, {BI}}, | |
10499 | + | |
10500 | +{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
10501 | +{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
10502 | +{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
10503 | +{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCNONE, {BOE, BI}}, | |
10504 | +{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, | |
10505 | +{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, | |
10506 | +{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}}, | |
10507 | +{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}}, | |
10508 | + | |
10509 | +{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
10510 | +{"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
10511 | + | |
10512 | +{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
10513 | +{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
10514 | + | |
10515 | +{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, | |
10516 | +{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, | |
10517 | +{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
10518 | +{"rlinm", M(21,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
10519 | +{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, | |
10520 | +{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCNONE, {RA, RS, MB}}, | |
10521 | +{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
10522 | +{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}}, | |
10523 | + | |
10524 | +{"rlmi", M(22,0), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
10525 | +{"rlmi.", M(22,1), M_MASK, M601, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
10526 | + | |
10527 | +{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
10528 | +{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
10529 | +{"rlnm", M(23,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
10530 | +{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
10531 | +{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
10532 | +{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCNONE, {RA, RS, RB, MBE, ME}}, | |
10533 | + | |
10534 | +{"nop", OP(24), 0xffffffff, PPCCOM, PPCNONE, {0}}, | |
10535 | +{"ori", OP(24), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
10536 | +{"oril", OP(24), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
10537 | + | |
10538 | +{"oris", OP(25), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
10539 | +{"oriu", OP(25), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
10540 | + | |
10541 | +{"xori", OP(26), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
10542 | +{"xoril", OP(26), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
10543 | + | |
10544 | +{"xoris", OP(27), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
10545 | +{"xoriu", OP(27), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
10546 | + | |
10547 | +{"andi.", OP(28), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
10548 | +{"andil.", OP(28), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
10549 | + | |
10550 | +{"andis.", OP(29), OP_MASK, PPCCOM, PPCNONE, {RA, RS, UI}}, | |
10551 | +{"andiu.", OP(29), OP_MASK, PWRCOM, PPCNONE, {RA, RS, UI}}, | |
10552 | + | |
10553 | +{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, | |
10554 | +{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}}, | |
10555 | +{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
10556 | +{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, | |
10557 | +{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCNONE, {RA, RS, MB6}}, | |
10558 | +{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
10559 | + | |
10560 | +{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}}, | |
10561 | +{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, ME6}}, | |
10562 | + | |
10563 | +{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
10564 | +{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
10565 | + | |
10566 | +{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
10567 | +{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCNONE, {RA, RS, SH6, MB6}}, | |
10568 | + | |
10569 | +{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
10570 | +{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}}, | |
10571 | +{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
10572 | +{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, MB6}}, | |
10573 | + | |
10574 | +{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}}, | |
10575 | +{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCNONE, {RA, RS, RB, ME6}}, | |
10576 | + | |
10577 | +{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, | |
10578 | +{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, | |
10579 | +{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, | |
10580 | +{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}}, | |
10581 | + | |
10582 | +{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10583 | +{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10584 | +{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10585 | +{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10586 | +{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10587 | +{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10588 | +{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10589 | +{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10590 | +{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10591 | +{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10592 | +{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10593 | +{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10594 | +{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10595 | +{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10596 | +{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10597 | +{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10598 | +{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10599 | +{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10600 | +{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10601 | +{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10602 | +{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10603 | +{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10604 | +{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10605 | +{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10606 | +{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10607 | +{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10608 | +{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, | |
10609 | +{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, | |
10610 | +{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}}, | |
10611 | +{"tw", X(31,4), X_MASK, PPCCOM, PPCNONE, {TO, RA, RB}}, | |
10612 | +{"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}}, | |
10613 | + | |
10614 | +{"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, | |
10615 | +{"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, | |
10616 | +{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
10617 | + | |
10618 | +{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10619 | +{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10620 | +{"subc", XO(31,8,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, | |
10621 | +{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10622 | +{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10623 | +{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, | |
10624 | + | |
10625 | +{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
10626 | +{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
10627 | + | |
10628 | +{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10629 | +{"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10630 | +{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10631 | +{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10632 | + | |
10633 | +{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
10634 | +{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
10635 | + | |
10636 | +{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, | |
10637 | + | |
10638 | +{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}}, | |
10639 | +{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}}, | |
10640 | +{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}}, | |
10641 | + | |
10642 | +{"lwarx", X(31,20), XEH_MASK, PPC, PPCNONE, {RT, RA0, RB, EH}}, | |
10643 | + | |
10644 | +{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}}, | |
10645 | + | |
10646 | +{"icbt", X(31,22), X_MASK, BOOKE|PPCE300, PPCNONE, {CT, RA, RB}}, | |
10647 | + | |
10648 | +{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, | |
10649 | +{"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10650 | + | |
10651 | +{"slw", XRC(31,24,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
10652 | +{"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, | |
10653 | +{"slw.", XRC(31,24,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
10654 | +{"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, | |
10655 | + | |
10656 | +{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, | |
10657 | +{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, | |
10658 | +{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, | |
10659 | +{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, | |
10660 | + | |
10661 | +{"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
10662 | +{"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
10663 | + | |
10664 | +{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10665 | +{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10666 | + | |
10667 | +{"maskg", XRC(31,29,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10668 | +{"maskg.", XRC(31,29,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10669 | + | |
10670 | +{"ldepx", X(31,29), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
10671 | +{"lwepx", X(31,31), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
10672 | + | |
10673 | +{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, | |
10674 | +{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, | |
10675 | +{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, | |
10676 | +{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPCNONE, {BF, RA, RB}}, | |
10677 | + | |
10678 | +{"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, | |
10679 | +{"lvehx", X(31,39), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, | |
10680 | +{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
10681 | + | |
10682 | +{"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, | |
10683 | + | |
10684 | +{"lvewx", X(31,71), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, | |
10685 | + | |
10686 | +{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}}, | |
10687 | + | |
10688 | +{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, | |
10689 | + | |
10690 | +{"isel", XISEL(31,15), XISEL_MASK, PPCISEL, PPCNONE, {RT, RA, RB, CRB}}, | |
10691 | + | |
10692 | +{"subf", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
10693 | +{"sub", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, | |
10694 | +{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
10695 | +{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, | |
10696 | + | |
10697 | +{"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}}, | |
10698 | + | |
10699 | +{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}}, | |
10700 | + | |
10701 | +{"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}}, | |
10702 | + | |
10703 | +{"lwzux", X(31,55), X_MASK, PPCCOM, PPCNONE, {RT, RAL, RB}}, | |
10704 | +{"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10705 | + | |
10706 | +{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, | |
10707 | +{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, | |
10708 | + | |
10709 | +{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10710 | +{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10711 | + | |
10712 | +{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}}, | |
10713 | +{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC, PPCNONE, {0}}, | |
10714 | +{"wait", X(31,62), XWC_MASK, POWER7|E500MC, PPCNONE, {WC}}, | |
10715 | + | |
10716 | +{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, | |
10717 | + | |
10718 | +{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10719 | +{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10720 | +{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10721 | +{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10722 | +{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10723 | +{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10724 | +{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10725 | +{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10726 | +{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10727 | +{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10728 | +{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10729 | +{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10730 | +{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10731 | +{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, | |
10732 | +{"td", X(31,68), X_MASK, PPC64, PPCNONE, {TO, RA, RB}}, | |
10733 | + | |
10734 | +{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
10735 | +{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
10736 | +{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
10737 | + | |
10738 | +{"mulhw", XO(31,75,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
10739 | +{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
10740 | + | |
10741 | +{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, PPCNONE, {RA, RS, RB}}, | |
10742 | +{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, PPCNONE, {RA, RS, RB}}, | |
10743 | + | |
10744 | +{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}}, | |
10745 | + | |
10746 | +{"mfmsr", X(31,83), XRARB_MASK, COM, PPCNONE, {RT}}, | |
10747 | + | |
10748 | +{"ldarx", X(31,84), XEH_MASK, PPC64, PPCNONE, {RT, RA0, RB, EH}}, | |
10749 | + | |
10750 | +{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPCNONE, {RA, RB}}, | |
10751 | +{"dcbf", X(31,86), XLRT_MASK, PPC, PPCNONE, {RA, RB, L}}, | |
10752 | + | |
10753 | +{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, | |
10754 | + | |
10755 | +{"lbepx", X(31,95), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
10756 | + | |
10757 | +{"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, | |
10758 | +{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
10759 | + | |
10760 | +{"neg", XO(31,104,0,0), XORB_MASK, COM, PPCNONE, {RT, RA}}, | |
10761 | +{"neg.", XO(31,104,0,1), XORB_MASK, COM, PPCNONE, {RT, RA}}, | |
10762 | + | |
10763 | +{"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
10764 | +{"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
10765 | + | |
10766 | +{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, | |
10767 | + | |
10768 | +{"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}}, | |
10769 | + | |
10770 | +{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}}, | |
10771 | + | |
10772 | +{"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, | |
10773 | + | |
10774 | +{"popcntb", X(31,122), XRB_MASK, POWER5, PPCNONE, {RA, RS}}, | |
10775 | + | |
10776 | +{"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, | |
10777 | +{"nor", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10778 | +{"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, | |
10779 | +{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10780 | + | |
10781 | +{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, | |
10782 | + | |
10783 | +{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE, PPCNONE, {RS}}, | |
10784 | + | |
10785 | +{"dcbtstls", X(31,134), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
10786 | + | |
10787 | +{"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, | |
10788 | +{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
10789 | + | |
10790 | +{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10791 | +{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10792 | +{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10793 | +{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10794 | + | |
10795 | +{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10796 | +{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10797 | +{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10798 | +{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10799 | + | |
10800 | +{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
10801 | + | |
10802 | +{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}}, | |
10803 | +{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, | |
10804 | +{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, | |
10805 | + | |
10806 | +{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}}, | |
10807 | + | |
10808 | +{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}}, | |
10809 | + | |
10810 | +{"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}}, | |
10811 | + | |
10812 | +{"stwx", X(31,151), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, | |
10813 | +{"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}}, | |
10814 | + | |
10815 | +{"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10816 | +{"slq.", XRC(31,152,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10817 | + | |
10818 | +{"sle", XRC(31,153,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10819 | +{"sle.", XRC(31,153,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10820 | + | |
10821 | +{"prtyw", X(31,154), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, | |
10822 | + | |
10823 | +{"stdepx", X(31,157), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, | |
10824 | + | |
10825 | +{"stwepx", X(31,159), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, | |
10826 | + | |
10827 | +{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE, PPCNONE, {E}}, | |
10828 | + | |
10829 | +{"dcbtls", X(31,166), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
10830 | + | |
10831 | +{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, | |
10832 | +{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
10833 | + | |
10834 | +{"dcbtlse", X(31,174), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
10835 | + | |
10836 | +{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}}, | |
10837 | + | |
10838 | +{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}}, | |
10839 | + | |
10840 | +{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}}, | |
10841 | +{"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, | |
10842 | + | |
10843 | +{"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
10844 | +{"sliq.", XRC(31,184,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
10845 | + | |
10846 | +{"prtyd", X(31,186), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, | |
10847 | + | |
10848 | +{"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, | |
10849 | +{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
10850 | + | |
10851 | +{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
10852 | +{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
10853 | +{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
10854 | +{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
10855 | + | |
10856 | +{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
10857 | +{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
10858 | +{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
10859 | +{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
10860 | + | |
10861 | +{"msgsnd", XRTRA(31,206,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}}, | |
10862 | + | |
10863 | +{"mtsr", X(31,210), XRB_MASK|(1<<20), COM32, PPCNONE, {SR, RS}}, | |
10864 | + | |
10865 | +{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}}, | |
10866 | + | |
10867 | +{"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, | |
10868 | + | |
10869 | +{"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10870 | +{"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10871 | + | |
10872 | +{"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10873 | +{"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
10874 | + | |
10875 | +{"stbepx", X(31,223), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, | |
10876 | + | |
10877 | +{"icblc", X(31,230), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
10878 | + | |
10879 | +{"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, | |
10880 | +{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
10881 | + | |
10882 | +{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
10883 | +{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
10884 | +{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
10885 | +{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
10886 | + | |
10887 | +{"mulld", XO(31,233,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
10888 | +{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
10889 | + | |
10890 | +{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
10891 | +{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
10892 | +{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
10893 | +{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
10894 | + | |
10895 | +{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10896 | +{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10897 | +{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10898 | +{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10899 | + | |
10900 | +{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC, PPCNONE, {RB}}, | |
10901 | +{"icblce", X(31,238), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
10902 | +{"mtsrin", X(31,242), XRA_MASK, PPC32, PPCNONE, {RS, RB}}, | |
10903 | +{"mtsri", X(31,242), XRA_MASK, POWER32, PPCNONE, {RS, RB}}, | |
10904 | + | |
10905 | +{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}}, | |
10906 | +{"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}}, | |
10907 | +{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}}, | |
10908 | + | |
10909 | +{"stbux", X(31,247), X_MASK, COM, PPCNONE, {RS, RAS, RB}}, | |
10910 | + | |
10911 | +{"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
10912 | +{"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
10913 | + | |
10914 | +{"bpermd", X(31,252), X_MASK, POWER7, PPCNONE, {RA, RS, RB}}, | |
10915 | + | |
10916 | +{"dcbtstep", XRT(31,255,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
10917 | + | |
10918 | +{"mfdcrx", X(31,259), X_MASK, BOOKE, PPCNONE, {RS, RA}}, | |
10919 | + | |
10920 | +{"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}}, | |
10921 | + | |
10922 | +{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
10923 | +{"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
10924 | +{"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
10925 | + | |
10926 | +{"add", XO(31,266,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10927 | +{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10928 | +{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
10929 | +{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
10930 | + | |
10931 | +{"ehpriv", X(31,270), 0xffffffff, E500MC, PPCNONE, {0}}, | |
10932 | + | |
10933 | +{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPCNONE, {RB, L}}, | |
10934 | + | |
10935 | +{"mfapidi", X(31,275), X_MASK, BOOKE, PPCNONE, {RT, RA}}, | |
10936 | + | |
10937 | +{"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
10938 | +{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
10939 | + | |
10940 | +{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}}, | |
10941 | +{"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}}, | |
10942 | +{"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}}, | |
10943 | + | |
10944 | +{"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, | |
10945 | + | |
10946 | +{"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, | |
10947 | + | |
10948 | +{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10949 | +{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10950 | + | |
10951 | +{"lhepx", X(31,287), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
10952 | + | |
10953 | +{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}}, | |
10954 | + | |
10955 | +{"tlbie", X(31,306), XRTLRA_MASK, PPC, PPCNONE, {RB, L}}, | |
10956 | +{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}}, | |
10957 | + | |
10958 | +{"eciwx", X(31,310), X_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
10959 | + | |
10960 | +{"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, | |
10961 | + | |
10962 | +{"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, | |
10963 | + | |
10964 | +{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10965 | +{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
10966 | + | |
10967 | +{"dcbtep", XRT(31,319,0), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
10968 | + | |
10969 | +{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10970 | +{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10971 | +{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10972 | +{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10973 | +{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10974 | +{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10975 | +{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10976 | +{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10977 | +{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10978 | +{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10979 | +{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10980 | +{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10981 | +{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10982 | +{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10983 | +{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10984 | +{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10985 | +{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10986 | +{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10987 | +{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10988 | +{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10989 | +{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10990 | +{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10991 | +{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10992 | +{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10993 | +{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10994 | +{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10995 | +{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10996 | +{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10997 | +{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10998 | +{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
10999 | +{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11000 | +{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11001 | +{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11002 | +{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11003 | +{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE, PPCNONE, {RT, SPR}}, | |
11004 | + | |
11005 | +{"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11006 | +{"div.", XO(31,331,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11007 | + | |
11008 | +{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, | |
11009 | + | |
11010 | +{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}}, | |
11011 | + | |
11012 | +{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}}, | |
11013 | +{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11014 | +{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11015 | +{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11016 | +{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}}, | |
11017 | +{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11018 | +{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11019 | +{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}}, | |
11020 | +{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11021 | +{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11022 | +{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, PPCNONE, {RT}}, | |
11023 | +{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, PPCNONE, {RT}}, | |
11024 | +{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11025 | +{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11026 | +{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}}, | |
11027 | +{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}}, | |
11028 | +{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11029 | +{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11030 | +{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11031 | +{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11032 | +{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11033 | +{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11034 | +{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11035 | +{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11036 | +{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11037 | +{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11038 | +{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11039 | +{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11040 | +{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11041 | +{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11042 | +{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11043 | +{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11044 | +{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11045 | +{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11046 | +{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11047 | +{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11048 | +{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11049 | +{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11050 | +{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}}, | |
11051 | +{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11052 | +{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, PPCNONE, {RT, SPRG}}, | |
11053 | +{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, | |
11054 | +{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, | |
11055 | +{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, | |
11056 | +{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, | |
11057 | +{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11058 | +{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11059 | +{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11060 | +{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, PPCNONE, {RT}}, | |
11061 | +{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, PPCNONE, {RT}}, | |
11062 | +{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, PPCNONE, {RT}}, | |
11063 | +{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, PPCNONE, {RT}}, | |
11064 | +{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}}, | |
11065 | +{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, PPCNONE, {RT}}, | |
11066 | +{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11067 | +{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, PPCNONE, {RT}}, | |
11068 | +{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11069 | +{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11070 | +{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11071 | +{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11072 | +{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11073 | +{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11074 | +{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11075 | +{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11076 | +{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11077 | +{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11078 | +{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11079 | +{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11080 | +{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11081 | +{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11082 | +{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11083 | +{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11084 | +{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11085 | +{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11086 | +{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11087 | +{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11088 | +{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11089 | +{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11090 | +{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11091 | +{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11092 | +{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11093 | +{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11094 | +{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11095 | +{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11096 | +{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11097 | +{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, PPCNONE, {RT}}, | |
11098 | +{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, | |
11099 | +{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, | |
11100 | +{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, | |
11101 | +{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, | |
11102 | +{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}}, | |
11103 | +{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, | |
11104 | +{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}}, | |
11105 | +{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, | |
11106 | +{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, PPCNONE, {RT}}, | |
11107 | +{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}}, | |
11108 | +{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, PPCNONE, {RT, SPRBAT}}, | |
11109 | +{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11110 | +{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11111 | +{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11112 | +{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11113 | +{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11114 | +{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11115 | +{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, | |
11116 | +{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, | |
11117 | +{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, | |
11118 | +{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, PPCNONE, {RT}}, | |
11119 | +{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11120 | +{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11121 | +{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11122 | +{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11123 | +{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11124 | +{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11125 | +{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11126 | +{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11127 | +{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11128 | +{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11129 | +{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11130 | +{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11131 | +{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11132 | +{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11133 | +{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11134 | +{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11135 | +{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11136 | +{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11137 | +{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11138 | +{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11139 | +{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11140 | +{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, PPCNONE, {RT}}, | |
11141 | +{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11142 | +{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11143 | +{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11144 | +{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11145 | +{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11146 | +{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11147 | +{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11148 | +{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11149 | +{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11150 | +{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
11151 | +{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
11152 | +{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
11153 | +{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
11154 | +{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
11155 | +{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11156 | +{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11157 | +{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11158 | +{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11159 | +{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11160 | +{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11161 | +{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
11162 | +{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11163 | +{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
11164 | +{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
11165 | +{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11166 | +{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11167 | +{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11168 | +{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11169 | +{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11170 | +{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11171 | +{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11172 | +{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11173 | +{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11174 | +{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11175 | +{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11176 | +{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11177 | +{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11178 | +{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11179 | +{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11180 | +{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, PPCNONE, {RT}}, | |
11181 | +{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11182 | +{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11183 | +{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11184 | +{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11185 | +{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11186 | +{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11187 | +{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11188 | +{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11189 | +{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11190 | +{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11191 | +{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11192 | +{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11193 | +{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11194 | +{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}}, | |
11195 | +{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}}, | |
11196 | +{"mfspr", X(31,339), X_MASK, COM, PPCNONE, {RT, SPR}}, | |
11197 | + | |
11198 | +{"lwax", X(31,341), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}}, | |
11199 | + | |
11200 | +{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, | |
11201 | + | |
11202 | +{"lhax", X(31,343), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, | |
11203 | + | |
11204 | +{"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, | |
11205 | + | |
11206 | +{"abs", XO(31,360,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
11207 | +{"abs.", XO(31,360,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
11208 | + | |
11209 | +{"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11210 | +{"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11211 | + | |
11212 | +{"tlbia", X(31,370), 0xffffffff, PPC, PPCNONE, {0}}, | |
11213 | + | |
11214 | +{"mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, PPCNONE, {RT}}, | |
11215 | +{"mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, PPCNONE, {RT}}, | |
11216 | +{"mftb", X(31,371), X_MASK, CLASSIC, POWER7, {RT, TBR}}, | |
11217 | + | |
11218 | +{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}}, | |
11219 | + | |
11220 | +{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, | |
11221 | + | |
11222 | +{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, | |
11223 | + | |
11224 | +{"popcntw", X(31,378), XRB_MASK, POWER7, PPCNONE, {RA, RS}}, | |
11225 | + | |
11226 | +{"mtdcrx", X(31,387), X_MASK, BOOKE, PPCNONE, {RA, RS}}, | |
11227 | + | |
11228 | +{"dcblc", X(31,390), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
11229 | +{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11230 | + | |
11231 | +{"divdeu", XO(31,393,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11232 | +{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11233 | +{"divweu", XO(31,395,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11234 | +{"divweu.", XO(31,395,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11235 | + | |
11236 | +{"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
11237 | + | |
11238 | +{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, | |
11239 | + | |
11240 | +{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, | |
11241 | + | |
11242 | +{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
11243 | +{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
11244 | + | |
11245 | +{"sthepx", X(31,415), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, | |
11246 | + | |
11247 | +{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}}, | |
11248 | + | |
11249 | +{"divde", XO(31,425,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11250 | +{"divde.", XO(31,425,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11251 | +{"divwe", XO(31,427,0,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11252 | +{"divwe.", XO(31,427,0,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11253 | + | |
11254 | +{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}}, | |
11255 | + | |
11256 | +{"ecowx", X(31,438), X_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11257 | + | |
11258 | +{"sthux", X(31,439), X_MASK, COM, PPCNONE, {RS, RAS, RB}}, | |
11259 | + | |
11260 | +{"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}}, | |
11261 | + | |
11262 | +{"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, | |
11263 | +{"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
11264 | +{"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, | |
11265 | +{"or.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
11266 | + | |
11267 | +{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11268 | +{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11269 | +{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11270 | +{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11271 | +{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11272 | +{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11273 | +{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11274 | +{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11275 | +{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11276 | +{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11277 | +{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11278 | +{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11279 | +{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11280 | +{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11281 | +{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11282 | +{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11283 | +{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11284 | +{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11285 | +{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11286 | +{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11287 | +{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11288 | +{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11289 | +{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11290 | +{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11291 | +{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11292 | +{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11293 | +{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11294 | +{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11295 | +{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11296 | +{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11297 | +{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11298 | +{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11299 | +{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11300 | +{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11301 | +{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE, PPCNONE, {SPR, RS}}, | |
11302 | + | |
11303 | +{"dccci", X(31,454), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}}, | |
11304 | + | |
11305 | +{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11306 | +{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11307 | + | |
11308 | +{"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11309 | +{"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11310 | + | |
11311 | +{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}}, | |
11312 | + | |
11313 | +{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}}, | |
11314 | +{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11315 | +{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11316 | +{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11317 | +{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}}, | |
11318 | +{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11319 | +{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11320 | +{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11321 | +{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11322 | +{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11323 | +{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}}, | |
11324 | +{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11325 | +{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11326 | +{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, PPCNONE, {RS}}, | |
11327 | +{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}}, | |
11328 | +{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11329 | +{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11330 | +{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11331 | +{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11332 | +{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11333 | +{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11334 | +{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11335 | +{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11336 | +{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11337 | +{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11338 | +{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11339 | +{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11340 | +{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11341 | +{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11342 | +{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11343 | +{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11344 | +{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11345 | +{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11346 | +{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11347 | +{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11348 | +{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11349 | +{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11350 | +{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}}, | |
11351 | +{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}}, | |
11352 | +{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11353 | +{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, PPCNONE, {SPRG, RS}}, | |
11354 | +{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, PPCNONE, {RS}}, | |
11355 | +{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, PPCNONE, {RS}}, | |
11356 | +{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, PPCNONE, {RS}}, | |
11357 | +{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, PPCNONE, {RS}}, | |
11358 | +{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, | |
11359 | +{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, | |
11360 | +{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, | |
11361 | +{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, | |
11362 | +{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}}, | |
11363 | +{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, PPCNONE, {RS}}, | |
11364 | +{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}}, | |
11365 | +{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}}, | |
11366 | +{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11367 | +{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11368 | +{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11369 | +{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11370 | +{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11371 | +{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11372 | +{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11373 | +{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11374 | +{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11375 | +{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11376 | +{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11377 | +{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11378 | +{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11379 | +{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11380 | +{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11381 | +{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11382 | +{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11383 | +{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11384 | +{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11385 | +{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11386 | +{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11387 | +{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11388 | +{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11389 | +{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11390 | +{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11391 | +{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11392 | +{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11393 | +{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11394 | +{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11395 | +{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, PPCNONE, {RS}}, | |
11396 | +{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, | |
11397 | +{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, | |
11398 | +{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, | |
11399 | +{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, | |
11400 | +{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}}, | |
11401 | +{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, | |
11402 | +{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}}, | |
11403 | +{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, | |
11404 | +{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}}, | |
11405 | +{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}}, | |
11406 | +{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, PPCNONE, {SPRBAT, RS}}, | |
11407 | +{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, | |
11408 | +{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, | |
11409 | +{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, | |
11410 | +{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11411 | +{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11412 | +{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11413 | +{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11414 | +{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11415 | +{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11416 | +{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11417 | +{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11418 | +{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11419 | +{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
11420 | +{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
11421 | +{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
11422 | +{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
11423 | +{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
11424 | +{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11425 | +{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11426 | +{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11427 | +{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11428 | +{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11429 | +{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11430 | +{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
11431 | +{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11432 | +{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
11433 | +{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
11434 | +{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11435 | +{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11436 | +{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11437 | +{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11438 | +{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11439 | +{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11440 | +{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11441 | +{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11442 | +{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11443 | +{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11444 | +{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11445 | +{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11446 | +{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11447 | +{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11448 | +{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11449 | +{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, PPCNONE, {RS}}, | |
11450 | +{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11451 | +{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11452 | +{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11453 | +{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11454 | +{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11455 | +{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11456 | +{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11457 | +{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11458 | +{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11459 | +{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11460 | +{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11461 | +{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11462 | +{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11463 | +{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}}, | |
11464 | +{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}}, | |
11465 | +{"mtspr", X(31,467), X_MASK, COM, PPCNONE, {SPR, RS}}, | |
11466 | + | |
11467 | +{"dcbi", X(31,470), XRT_MASK, PPC, PPCNONE, {RA, RB}}, | |
11468 | + | |
11469 | +{"nand", XRC(31,476,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
11470 | +{"nand.", XRC(31,476,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, | |
11471 | + | |
11472 | +{"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, | |
11473 | + | |
11474 | +{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCNONE, {RT, RA, RB}}, | |
11475 | + | |
11476 | +{"icbtls", X(31,486), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
11477 | + | |
11478 | +{"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, | |
11479 | + | |
11480 | +{"nabs", XO(31,488,0,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
11481 | +{"nabs.", XO(31,488,0,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
11482 | + | |
11483 | +{"divd", XO(31,489,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11484 | +{"divd.", XO(31,489,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11485 | + | |
11486 | +{"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11487 | +{"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11488 | + | |
11489 | +{"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, | |
11490 | + | |
11491 | +{"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}}, | |
11492 | + | |
11493 | +{"cli", X(31,502), XRB_MASK, POWER, PPCNONE, {RT, RA}}, | |
11494 | + | |
11495 | +{"popcntd", X(31,506), XRB_MASK, POWER7, PPCNONE, {RA, RS}}, | |
11496 | + | |
11497 | +{"cmpb", X(31,508), X_MASK, POWER6, PPCNONE, {RA, RS, RB}}, | |
11498 | + | |
11499 | +{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, POWER7, {BF}}, | |
11500 | + | |
11501 | +{"lbdx", X(31,515), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
11502 | + | |
11503 | +{"bblels", X(31,518), X_MASK, PPCBRLK, PPCNONE, {0}}, | |
11504 | + | |
11505 | +{"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, | |
11506 | +{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11507 | + | |
11508 | +{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11509 | +{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11510 | +{"subco", XO(31,8,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, | |
11511 | +{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11512 | +{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11513 | +{"subco.", XO(31,8,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, | |
11514 | + | |
11515 | +{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11516 | +{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11517 | +{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11518 | +{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11519 | + | |
11520 | +{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}}, | |
11521 | + | |
11522 | +{"ldbrx", X(31,532), X_MASK, CELL|POWER7, PPCNONE, {RT, RA0, RB}}, | |
11523 | + | |
11524 | +{"lswx", X(31,533), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, | |
11525 | +{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11526 | + | |
11527 | +{"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, | |
11528 | +{"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11529 | + | |
11530 | +{"lfsx", X(31,535), X_MASK, COM, PPCNONE, {FRT, RA0, RB}}, | |
11531 | + | |
11532 | +{"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
11533 | +{"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, | |
11534 | +{"srw.", XRC(31,536,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
11535 | +{"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, | |
11536 | + | |
11537 | +{"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11538 | +{"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11539 | + | |
11540 | +{"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
11541 | +{"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
11542 | + | |
11543 | +{"maskir", XRC(31,541,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11544 | +{"maskir.", XRC(31,541,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11545 | + | |
11546 | +{"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
11547 | + | |
11548 | +{"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}}, | |
11549 | + | |
11550 | +{"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, | |
11551 | +{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11552 | + | |
11553 | +{"subfo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11554 | +{"subo", XO(31,40,1,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, | |
11555 | +{"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11556 | +{"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, | |
11557 | + | |
11558 | +{"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}}, | |
11559 | + | |
11560 | +{"lfsux", X(31,567), X_MASK, COM, PPCNONE, {FRT, RAS, RB}}, | |
11561 | + | |
11562 | +{"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
11563 | + | |
11564 | +{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11565 | + | |
11566 | +{"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, | |
11567 | + | |
11568 | +{"mfsr", X(31,595), XRB_MASK|(1<<20), COM32, PPCNONE, {RT, SR}}, | |
11569 | + | |
11570 | +{"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}}, | |
11571 | +{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}}, | |
11572 | + | |
11573 | +{"msync", X(31,598), 0xffffffff, BOOKE, PPCNONE, {0}}, | |
11574 | +{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, PPCNONE, {0}}, | |
11575 | +{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, | |
11576 | +{"sync", X(31,598), XSYNC_MASK, PPCCOM, PPCNONE, {LS}}, | |
11577 | +{"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}}, | |
11578 | + | |
11579 | +{"lfdx", X(31,599), X_MASK, COM, PPCNONE, {FRT, RA0, RB}}, | |
11580 | + | |
11581 | +{"lfdepx", X(31,607), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}}, | |
11582 | +{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, | |
11583 | + | |
11584 | +{"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, | |
11585 | + | |
11586 | +{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11587 | + | |
11588 | +{"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}}, | |
11589 | +{"nego.", XO(31,104,1,1), XORB_MASK, COM, PPCNONE, {RT, RA}}, | |
11590 | + | |
11591 | +{"mulo", XO(31,107,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11592 | +{"mulo.", XO(31,107,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11593 | + | |
11594 | +{"lxsdux", X(31,620), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, | |
11595 | + | |
11596 | +{"mfsri", X(31,627), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11597 | + | |
11598 | +{"dclst", X(31,630), XRB_MASK, PWRCOM, PPCNONE, {RS, RA}}, | |
11599 | + | |
11600 | +{"lfdux", X(31,631), X_MASK, COM, PPCNONE, {FRT, RAS, RB}}, | |
11601 | + | |
11602 | +{"stbdx", X(31,643), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, | |
11603 | + | |
11604 | +{"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, | |
11605 | +{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11606 | + | |
11607 | +{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11608 | +{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11609 | +{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11610 | +{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11611 | + | |
11612 | +{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11613 | +{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11614 | +{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11615 | +{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11616 | + | |
11617 | +{"mfsrin", X(31,659), XRA_MASK, PPC32, PPCNONE, {RT, RB}}, | |
11618 | + | |
11619 | +{"stdbrx", X(31,660), X_MASK, CELL|POWER7, PPCNONE, {RS, RA0, RB}}, | |
11620 | + | |
11621 | +{"stswx", X(31,661), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, | |
11622 | +{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, | |
11623 | + | |
11624 | +{"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, | |
11625 | +{"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, | |
11626 | + | |
11627 | +{"stfsx", X(31,663), X_MASK, COM, PPCNONE, {FRS, RA0, RB}}, | |
11628 | + | |
11629 | +{"srq", XRC(31,664,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11630 | +{"srq.", XRC(31,664,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11631 | + | |
11632 | +{"sre", XRC(31,665,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11633 | +{"sre.", XRC(31,665,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11634 | + | |
11635 | +{"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, | |
11636 | + | |
11637 | +{"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, | |
11638 | +{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11639 | + | |
11640 | +{"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, | |
11641 | + | |
11642 | +{"stfsux", X(31,695), X_MASK, COM, PPCNONE, {FRS, RAS, RB}}, | |
11643 | + | |
11644 | +{"sriq", XRC(31,696,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
11645 | +{"sriq.", XRC(31,696,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
11646 | + | |
11647 | +{"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, | |
11648 | + | |
11649 | +{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11650 | + | |
11651 | +{"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, | |
11652 | + | |
11653 | +{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
11654 | +{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
11655 | +{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
11656 | +{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
11657 | + | |
11658 | +{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
11659 | +{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
11660 | +{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
11661 | +{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
11662 | + | |
11663 | +{"stswi", X(31,725), X_MASK, PPCCOM, PPCNONE, {RS, RA0, NB}}, | |
11664 | +{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}}, | |
11665 | + | |
11666 | +{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, | |
11667 | + | |
11668 | +{"stfdx", X(31,727), X_MASK, COM, PPCNONE, {FRS, RA0, RB}}, | |
11669 | + | |
11670 | +{"srlq", XRC(31,728,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11671 | +{"srlq.", XRC(31,728,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11672 | + | |
11673 | +{"sreq", XRC(31,729,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11674 | +{"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11675 | + | |
11676 | +{"stfdepx", X(31,735), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, | |
11677 | +{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, | |
11678 | + | |
11679 | +{"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, | |
11680 | + | |
11681 | +{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11682 | + | |
11683 | +{"stxsdux", X(31,748), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, | |
11684 | + | |
11685 | +{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
11686 | +{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
11687 | +{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
11688 | +{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
11689 | + | |
11690 | +{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11691 | +{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11692 | + | |
11693 | +{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
11694 | +{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
11695 | +{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, | |
11696 | +{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, | |
11697 | + | |
11698 | +{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11699 | +{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11700 | +{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11701 | +{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11702 | + | |
11703 | +{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE, PPCNONE, {RA, RB}}, | |
11704 | +{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, | |
11705 | + | |
11706 | +{"stfdux", X(31,759), X_MASK, COM, PPCNONE, {FRS, RAS, RB}}, | |
11707 | + | |
11708 | +{"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
11709 | +{"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
11710 | + | |
11711 | +{"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, | |
11712 | +{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11713 | + | |
11714 | +{"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11715 | +{"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11716 | + | |
11717 | +{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11718 | +{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11719 | +{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, | |
11720 | +{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11721 | + | |
11722 | +{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, | |
11723 | + | |
11724 | +{"tlbivax", X(31,786), XRT_MASK, BOOKE, PPCNONE, {RA, RB}}, | |
11725 | +{"tlbilx", X(31,787), X_MASK, E500MC, PPCNONE, {T, RA0, RB}}, | |
11726 | +{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, PPCNONE, {0}}, | |
11727 | +{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, PPCNONE, {0}}, | |
11728 | +{"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, PPCNONE, {RA0, RB}}, | |
11729 | + | |
11730 | +{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, | |
11731 | + | |
11732 | +{"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, | |
11733 | + | |
11734 | +{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB}}, | |
11735 | +{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, | |
11736 | + | |
11737 | +{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
11738 | +{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, | |
11739 | +{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, | |
11740 | +{"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, | |
11741 | + | |
11742 | +{"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
11743 | +{"srad.", XRC(31,794,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, | |
11744 | + | |
11745 | +{"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}}, | |
11746 | + | |
11747 | +{"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, | |
11748 | + | |
11749 | +{"lxvw4ux", X(31,812), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, | |
11750 | + | |
11751 | +{"rac", X(31,818), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, | |
11752 | + | |
11753 | +{"lhzcix", X(31,821), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, | |
11754 | + | |
11755 | +{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, PPCNONE, {STRM}}, | |
11756 | + | |
11757 | +{"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, | |
11758 | + | |
11759 | +{"srawi", XRC(31,824,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, | |
11760 | +{"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, | |
11761 | +{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, | |
11762 | +{"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, | |
11763 | + | |
11764 | +{"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, | |
11765 | +{"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, | |
11766 | + | |
11767 | +{"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11768 | +{"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11769 | + | |
11770 | +{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, | |
11771 | + | |
11772 | +{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, | |
11773 | + | |
11774 | +{"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, | |
11775 | + | |
11776 | +{"mbar", X(31,854), X_MASK, BOOKE, PPCNONE, {MO}}, | |
11777 | +{"eieio", X(31,854), 0xffffffff, PPC, PPCNONE, {0}}, | |
11778 | + | |
11779 | +{"lfiwax", X(31,855), X_MASK, POWER6, PPCNONE, {FRT, RA0, RB}}, | |
11780 | + | |
11781 | +{"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
11782 | +{"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
11783 | + | |
11784 | +{"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11785 | +{"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, | |
11786 | + | |
11787 | +{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, | |
11788 | + | |
11789 | +{"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, | |
11790 | + | |
11791 | +{"lfiwzx", X(31,887), X_MASK, POWER7, PPCNONE, {FRT, RA0, RB}}, | |
11792 | + | |
11793 | +{"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, | |
11794 | +{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, | |
11795 | + | |
11796 | +{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11797 | +{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11798 | +{"divweuo", XO(31,395,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11799 | +{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11800 | + | |
11801 | +{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, | |
11802 | + | |
11803 | +{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}}, | |
11804 | +{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, PPCNONE, {RTO, RA, RB}}, | |
11805 | + | |
11806 | +{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, | |
11807 | + | |
11808 | +{"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, | |
11809 | + | |
11810 | +{"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, | |
11811 | + | |
11812 | +{"stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB}}, | |
11813 | +{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, | |
11814 | + | |
11815 | +{"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11816 | +{"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11817 | + | |
11818 | +{"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11819 | +{"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, | |
11820 | + | |
11821 | +{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, | |
11822 | +{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, | |
11823 | +{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, | |
11824 | +{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, | |
11825 | + | |
11826 | +{"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, | |
11827 | + | |
11828 | +{"stvrxl", X(31,935), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, | |
11829 | + | |
11830 | +{"divdeo", XO(31,425,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11831 | +{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11832 | +{"divweo", XO(31,427,1,0), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11833 | +{"divweo.", XO(31,427,1,1), XO_MASK, POWER7, PPCNONE, {RT, RA, RB}}, | |
11834 | + | |
11835 | +{"stxvw4ux", X(31,940), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, | |
11836 | + | |
11837 | +{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, | |
11838 | +{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, | |
11839 | +{"tlbre", X(31,946), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}}, | |
11840 | + | |
11841 | +{"sthcix", X(31,949), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, | |
11842 | + | |
11843 | +{"stfqux", X(31,951), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}}, | |
11844 | + | |
11845 | +{"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
11846 | +{"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, | |
11847 | + | |
11848 | +{"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}}, | |
11849 | +{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}}, | |
11850 | + | |
11851 | +{"iccci", X(31,966), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}}, | |
11852 | + | |
11853 | +{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11854 | +{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11855 | + | |
11856 | +{"divwuo", XO(31,459,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11857 | +{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11858 | + | |
11859 | +{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, | |
11860 | + | |
11861 | +{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, | |
11862 | +{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, | |
11863 | +{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, PPCNONE, {RSO, RAOPT, SHO}}, | |
11864 | +{"tlbld", X(31,978), XRTRA_MASK, PPC, PPCNONE, {RB}}, | |
11865 | + | |
11866 | +{"stbcix", X(31,981), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, | |
11867 | + | |
11868 | +{"icbi", X(31,982), XRT_MASK, PPC, PPCNONE, {RA, RB}}, | |
11869 | + | |
11870 | +{"stfiwx", X(31,983), X_MASK, PPC, PPCNONE, {FRS, RA0, RB}}, | |
11871 | + | |
11872 | +{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, | |
11873 | +{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, | |
11874 | + | |
11875 | +{"icbiep", XRT(31,991,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, | |
11876 | + | |
11877 | +{"icread", X(31,998), XRT_MASK, PPC403|PPC440, PPCNONE, {RA, RB}}, | |
11878 | + | |
11879 | +{"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
11880 | +{"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, | |
11881 | + | |
11882 | +{"divdo", XO(31,489,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11883 | +{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, | |
11884 | + | |
11885 | +{"divwo", XO(31,491,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11886 | +{"divwo.", XO(31,491,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, | |
11887 | + | |
11888 | +{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, | |
11889 | + | |
11890 | +{"tlbli", X(31,1010), XRTRA_MASK, PPC, PPCNONE, {RB}}, | |
11891 | + | |
11892 | +{"stdcix", X(31,1013), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, | |
11893 | + | |
11894 | +{"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}}, | |
11895 | +{"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}}, | |
11896 | + | |
11897 | +{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, | |
11898 | + | |
11899 | +{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4, PPCNONE, {RA, RB}}, | |
11900 | +{"dcbzl", XOPL(31,1014,1), XRT_MASK, PPCCOM|E500MC,POWER4, {RA, RB}}, | |
11901 | + | |
11902 | +{"cctpl", 0x7c210b78, 0xffffffff, CELL, PPCNONE, {0}}, | |
11903 | +{"cctpm", 0x7c421378, 0xffffffff, CELL, PPCNONE, {0}}, | |
11904 | +{"cctph", 0x7c631b78, 0xffffffff, CELL, PPCNONE, {0}}, | |
11905 | + | |
11906 | +{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, | |
11907 | +{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, | |
11908 | +{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, PPCNONE, {0}}, | |
11909 | + | |
11910 | +{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, PPCNONE, {0}}, | |
11911 | +{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, PPCNONE, {0}}, | |
11912 | +{"db12cyc", 0x7fdef378, 0xffffffff, CELL, PPCNONE, {0}}, | |
11913 | +{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, PPCNONE, {0}}, | |
11914 | + | |
11915 | +{"lwz", OP(32), OP_MASK, PPCCOM, PPCNONE, {RT, D, RA0}}, | |
11916 | +{"l", OP(32), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, | |
11917 | + | |
11918 | +{"lwzu", OP(33), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAL}}, | |
11919 | +{"lu", OP(33), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, | |
11920 | + | |
11921 | +{"lbz", OP(34), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, | |
11922 | + | |
11923 | +{"lbzu", OP(35), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, | |
11924 | + | |
11925 | +{"stw", OP(36), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}}, | |
11926 | +{"st", OP(36), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, | |
11927 | + | |
11928 | +{"stwu", OP(37), OP_MASK, PPCCOM, PPCNONE, {RS, D, RAS}}, | |
11929 | +{"stu", OP(37), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, | |
11930 | + | |
11931 | +{"stb", OP(38), OP_MASK, COM, PPCNONE, {RS, D, RA0}}, | |
11932 | + | |
11933 | +{"stbu", OP(39), OP_MASK, COM, PPCNONE, {RS, D, RAS}}, | |
11934 | + | |
11935 | +{"lhz", OP(40), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, | |
11936 | + | |
11937 | +{"lhzu", OP(41), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, | |
11938 | + | |
11939 | +{"lha", OP(42), OP_MASK, COM, PPCNONE, {RT, D, RA0}}, | |
11940 | + | |
11941 | +{"lhau", OP(43), OP_MASK, COM, PPCNONE, {RT, D, RAL}}, | |
11942 | + | |
11943 | +{"sth", OP(44), OP_MASK, COM, PPCNONE, {RS, D, RA0}}, | |
11944 | + | |
11945 | +{"sthu", OP(45), OP_MASK, COM, PPCNONE, {RS, D, RAS}}, | |
11946 | + | |
11947 | +{"lmw", OP(46), OP_MASK, PPCCOM, PPCNONE, {RT, D, RAM}}, | |
11948 | +{"lm", OP(46), OP_MASK, PWRCOM, PPCNONE, {RT, D, RA0}}, | |
11949 | + | |
11950 | +{"stmw", OP(47), OP_MASK, PPCCOM, PPCNONE, {RS, D, RA0}}, | |
11951 | +{"stm", OP(47), OP_MASK, PWRCOM, PPCNONE, {RS, D, RA0}}, | |
11952 | + | |
11953 | +{"lfs", OP(48), OP_MASK, COM, PPCNONE, {FRT, D, RA0}}, | |
11954 | + | |
11955 | +{"lfsu", OP(49), OP_MASK, COM, PPCNONE, {FRT, D, RAS}}, | |
11956 | + | |
11957 | +{"lfd", OP(50), OP_MASK, COM, PPCNONE, {FRT, D, RA0}}, | |
11958 | + | |
11959 | +{"lfdu", OP(51), OP_MASK, COM, PPCNONE, {FRT, D, RAS}}, | |
11960 | + | |
11961 | +{"stfs", OP(52), OP_MASK, COM, PPCNONE, {FRS, D, RA0}}, | |
11962 | + | |
11963 | +{"stfsu", OP(53), OP_MASK, COM, PPCNONE, {FRS, D, RAS}}, | |
11964 | + | |
11965 | +{"stfd", OP(54), OP_MASK, COM, PPCNONE, {FRS, D, RA0}}, | |
11966 | + | |
11967 | +{"stfdu", OP(55), OP_MASK, COM, PPCNONE, {FRS, D, RAS}}, | |
11968 | + | |
11969 | +{"lq", OP(56), OP_MASK, POWER4, PPCNONE, {RTQ, DQ, RAQ}}, | |
11970 | + | |
11971 | +{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, | |
11972 | + | |
11973 | +{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, | |
11974 | + | |
11975 | +{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}}, | |
11976 | + | |
11977 | +{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, | |
11978 | + | |
11979 | +{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, | |
11980 | + | |
11981 | +{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, | |
11982 | +{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}}, | |
11983 | +{"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}}, | |
11984 | + | |
11985 | +{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
11986 | +{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
11987 | + | |
11988 | +{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, | |
11989 | +{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCNONE, {FRT,FRA,FRB,RMC}}, | |
11990 | + | |
11991 | +{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, | |
11992 | +{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, | |
11993 | + | |
11994 | +{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, | |
11995 | +{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, | |
11996 | + | |
11997 | +{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, | |
11998 | +{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCNONE, {FRT, FRA, FRB}}, | |
11999 | + | |
12000 | +{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}}, | |
12001 | +{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, PPCNONE, {FRT, FRB}}, | |
12002 | + | |
12003 | +{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, | |
12004 | +{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, | |
12005 | +{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12006 | +{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12007 | + | |
12008 | +{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}}, | |
12009 | +{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCNONE, {FRT, FRA, FRC}}, | |
12010 | + | |
12011 | +{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, | |
12012 | +{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, | |
12013 | +{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12014 | +{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12015 | + | |
12016 | +{"fmsubs", A(59,28,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12017 | +{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12018 | + | |
12019 | +{"fmadds", A(59,29,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12020 | +{"fmadds.", A(59,29,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12021 | + | |
12022 | +{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12023 | +{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12024 | + | |
12025 | +{"fnmadds", A(59,31,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12026 | +{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12027 | + | |
12028 | +{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12029 | +{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12030 | + | |
12031 | +{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, | |
12032 | +{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, | |
12033 | + | |
12034 | +{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
12035 | +{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
12036 | + | |
12037 | +{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}}, | |
12038 | +{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT,FRB,RMC}}, | |
12039 | + | |
12040 | +{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
12041 | +{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
12042 | + | |
12043 | +{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
12044 | +{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
12045 | + | |
12046 | +{"dcmpo", X(59,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, | |
12047 | + | |
12048 | +{"dtstex", X(59,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, | |
12049 | +{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}}, | |
12050 | +{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}}, | |
12051 | + | |
12052 | +{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
12053 | +{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
12054 | + | |
12055 | +{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12056 | +{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12057 | + | |
12058 | +{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12059 | +{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12060 | + | |
12061 | +{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, | |
12062 | +{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, | |
12063 | + | |
12064 | +{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12065 | +{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12066 | + | |
12067 | +{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12068 | +{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12069 | + | |
12070 | +{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12071 | +{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12072 | + | |
12073 | +{"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, | |
12074 | + | |
12075 | +{"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, | |
12076 | + | |
12077 | +{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12078 | +{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12079 | + | |
12080 | +{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12081 | +{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12082 | + | |
12083 | +{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, | |
12084 | +{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, | |
12085 | + | |
12086 | +{"fcfids", XRC(59,846,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12087 | +{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12088 | + | |
12089 | +{"diex", XRC(59,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12090 | +{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12091 | + | |
12092 | +{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12093 | +{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12094 | + | |
12095 | +{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}}, | |
12096 | +{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}}, | |
12097 | +{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}}, | |
12098 | +{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12099 | +{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, | |
12100 | +{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12101 | +{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}}, | |
12102 | +{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12103 | +{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12104 | +{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12105 | +{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
12106 | +{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12107 | +{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12108 | +{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
12109 | +{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12110 | +{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12111 | +{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12112 | +{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12113 | +{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12114 | +{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
12115 | +{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12116 | +{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12117 | +{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12118 | +{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12119 | +{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12120 | +{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12121 | +{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12122 | +{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12123 | +{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12124 | +{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12125 | +{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12126 | +{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12127 | +{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12128 | +{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12129 | +{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12130 | +{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12131 | +{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12132 | +{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12133 | +{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12134 | +{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12135 | +{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12136 | +{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
12137 | +{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12138 | +{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12139 | +{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12140 | +{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12141 | +{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12142 | +{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12143 | +{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12144 | +{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, | |
12145 | +{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12146 | +{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12147 | +{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12148 | +{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12149 | +{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12150 | +{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12151 | +{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12152 | +{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12153 | +{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12154 | +{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12155 | +{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, | |
12156 | +{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12157 | +{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12158 | +{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12159 | +{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12160 | +{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12161 | +{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12162 | +{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12163 | +{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12164 | +{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12165 | +{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12166 | +{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12167 | +{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12168 | +{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12169 | +{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12170 | +{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}}, | |
12171 | +{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12172 | +{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12173 | +{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12174 | +{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12175 | +{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, | |
12176 | +{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12177 | +{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12178 | +{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12179 | +{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12180 | +{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12181 | +{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12182 | +{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12183 | +{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12184 | +{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12185 | +{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12186 | +{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12187 | +{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12188 | +{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12189 | +{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12190 | +{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, | |
12191 | +{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12192 | +{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12193 | +{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12194 | +{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12195 | +{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12196 | +{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12197 | +{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12198 | +{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12199 | +{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12200 | +{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12201 | +{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12202 | +{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12203 | +{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, | |
12204 | +{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12205 | +{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, | |
12206 | +{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12207 | +{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12208 | +{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12209 | +{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, | |
12210 | +{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12211 | +{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12212 | +{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12213 | +{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12214 | +{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12215 | +{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12216 | +{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12217 | +{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12218 | +{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12219 | +{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12220 | +{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12221 | +{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12222 | +{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12223 | +{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12224 | +{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12225 | +{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12226 | +{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12227 | +{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12228 | +{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12229 | +{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12230 | +{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12231 | +{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12232 | +{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12233 | +{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12234 | +{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12235 | +{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, | |
12236 | + | |
12237 | +{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, | |
12238 | + | |
12239 | +{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, | |
12240 | + | |
12241 | +{"stfdp", OP(61), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}}, | |
12242 | + | |
12243 | +{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, | |
12244 | + | |
12245 | +{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, | |
12246 | + | |
12247 | +{"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}}, | |
12248 | +{"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}}, | |
12249 | +{"stq", DSO(62,2), DS_MASK, POWER4, PPCNONE, {RSQ, DS, RA0}}, | |
12250 | + | |
12251 | +{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}}, | |
12252 | + | |
12253 | +{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12254 | +{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12255 | + | |
12256 | +{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, | |
12257 | +{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, | |
12258 | + | |
12259 | +{"fcpsgn", XRC(63,8,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12260 | +{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12261 | + | |
12262 | +{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12263 | +{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12264 | + | |
12265 | +{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, | |
12266 | +{"fcir", XRC(63,14,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, | |
12267 | +{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, | |
12268 | +{"fcir.", XRC(63,14,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, | |
12269 | + | |
12270 | +{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, | |
12271 | +{"fcirz", XRC(63,15,0), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, | |
12272 | +{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCNONE, {FRT, FRB}}, | |
12273 | +{"fcirz.", XRC(63,15,1), XRA_MASK, POWER2, PPCNONE, {FRT, FRB}}, | |
12274 | + | |
12275 | +{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12276 | +{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12277 | +{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12278 | +{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12279 | + | |
12280 | +{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12281 | +{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12282 | +{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12283 | +{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12284 | + | |
12285 | +{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12286 | +{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12287 | +{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12288 | +{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRB}}, | |
12289 | + | |
12290 | +{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}}, | |
12291 | +{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, PPCNONE, {FRT, FRB}}, | |
12292 | + | |
12293 | +{"fsel", A(63,23,0), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12294 | +{"fsel.", A(63,23,1), A_MASK, PPC, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12295 | + | |
12296 | +{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, | |
12297 | +{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7, {FRT, FRB, A_L}}, | |
12298 | +{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12299 | +{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12300 | + | |
12301 | +{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}}, | |
12302 | +{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, | |
12303 | +{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC}}, | |
12304 | +{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC}}, | |
12305 | + | |
12306 | +{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, | |
12307 | +{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7, {FRT, FRB, A_L}}, | |
12308 | +{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12309 | +{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12310 | + | |
12311 | +{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12312 | +{"fms", A(63,28,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12313 | +{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12314 | +{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12315 | + | |
12316 | +{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12317 | +{"fma", A(63,29,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12318 | +{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12319 | +{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12320 | + | |
12321 | +{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12322 | +{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12323 | +{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12324 | +{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12325 | + | |
12326 | +{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12327 | +{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12328 | +{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12329 | +{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, | |
12330 | + | |
12331 | +{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCNONE, {BF, FRA, FRB}}, | |
12332 | + | |
12333 | +{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12334 | +{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12335 | + | |
12336 | +{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, | |
12337 | +{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRT, FRA, FRB, RMC}}, | |
12338 | + | |
12339 | +{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}}, | |
12340 | +{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}}, | |
12341 | + | |
12342 | +{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12343 | +{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12344 | + | |
12345 | +{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, | |
12346 | + | |
12347 | +{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
12348 | +{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
12349 | + | |
12350 | +{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}}, | |
12351 | +{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCNONE, {TE, FRT, FRB, RMC}}, | |
12352 | + | |
12353 | +{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCNONE, {BT}}, | |
12354 | +{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCNONE, {BT}}, | |
12355 | + | |
12356 | +{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12357 | +{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12358 | + | |
12359 | +{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
12360 | +{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCNONE, {FRT, FRA, SH16}}, | |
12361 | + | |
12362 | +{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
12363 | +{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
12364 | + | |
12365 | +{"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}}, | |
12366 | + | |
12367 | +{"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, | |
12368 | + | |
12369 | +{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}}, | |
12370 | +{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}}, | |
12371 | +{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6, {BFF, U}}, | |
12372 | +{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6, PPCNONE, {BFF, U, W}}, | |
12373 | + | |
12374 | +{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12375 | +{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12376 | + | |
12377 | +{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12378 | +{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12379 | +{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12380 | +{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12381 | + | |
12382 | +{"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}}, | |
12383 | + | |
12384 | +{"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, | |
12385 | +{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRA, DCM}}, | |
12386 | +{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRA, DGM}}, | |
12387 | + | |
12388 | +{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
12389 | +{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCNONE, {R, FRT, FRB, RMC}}, | |
12390 | + | |
12391 | +{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12392 | +{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12393 | + | |
12394 | +{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12395 | +{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCNONE, {FRT, FRB}}, | |
12396 | + | |
12397 | +{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12398 | +{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12399 | + | |
12400 | +{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, | |
12401 | +{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCNONE, {SP, FRT, FRB}}, | |
12402 | + | |
12403 | +{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12404 | +{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12405 | + | |
12406 | +{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
12407 | +{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
12408 | +{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
12409 | +{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
12410 | +{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
12411 | +{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
12412 | +{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
12413 | +{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, | |
12414 | + | |
12415 | +{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12416 | +{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12417 | + | |
12418 | +{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12419 | +{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12420 | + | |
12421 | +{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCNONE, {FRT}}, | |
12422 | +{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCNONE, {FRT}}, | |
12423 | + | |
12424 | +{"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, | |
12425 | + | |
12426 | +{"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, | |
12427 | + | |
12428 | +{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6, {FLM, FRB}}, | |
12429 | +{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}}, | |
12430 | +{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6, {FLM, FRB}}, | |
12431 | +{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6, PPCNONE, {FLM, FRB, XFL_L, W}}, | |
12432 | + | |
12433 | +{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12434 | +{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12435 | + | |
12436 | +{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12437 | +{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, | |
12438 | + | |
12439 | +{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, | |
12440 | +{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, | |
12441 | + | |
12442 | +{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, | |
12443 | +{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, | |
12444 | + | |
12445 | +{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, | |
12446 | +{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRT, FRB}}, | |
12447 | + | |
12448 | +{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, | |
12449 | +{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, | |
12450 | + | |
12451 | +{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12452 | +{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRT, FRA, FRB}}, | |
12453 | ||
12454 | -{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, {FRT, FRB}}, | |
12455 | -{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, {FRT, FRB}}, | |
12456 | +{"fctidu", XRC(63,942,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12457 | +{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12458 | ||
12459 | -{"diexq", XRC(63,866,0), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
12460 | -{"diexq.", XRC(63,866,1), X_MASK, POWER6, {FRT, FRA, FRB}}, | |
12461 | +{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12462 | +{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12463 | ||
12464 | +{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12465 | +{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, | |
12466 | }; | |
12467 | ||
12468 | const int powerpc_num_opcodes = |