| 1 | diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Kconfig linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Kconfig |
| 2 | --- linux-2.6.16.60/arch/arm/mach-s3c2410/Kconfig 2008-01-27 17:58:41.000000000 +0100 |
| 3 | +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Kconfig 2010-02-18 01:19:10.259895346 +0100 |
| 4 | @@ -86,8 +86,24 @@ config MACH_NEXCODER_2440 |
| 5 | help |
| 6 | Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board |
| 7 | |
| 8 | +config MACH_GP32 |
| 9 | + bool "GamePark GP32" |
| 10 | + depends on EXPERIMENTAL |
| 11 | + select CPU_S3C2400 |
| 12 | + help |
| 13 | + Say Y here if you are using the GamePark GP32 handheld. |
| 14 | + |
| 15 | + See <http://sourceforge.net/projects/gp32linux> for more |
| 16 | + information on this project. |
| 17 | + |
| 18 | endmenu |
| 19 | |
| 20 | +config CPU_S3C2400 |
| 21 | + bool |
| 22 | + depends on ARCH_S3C2410 |
| 23 | + help |
| 24 | + Support for the S3C2400 from S3C24XX line of Samsung Mobile CPUs. |
| 25 | + |
| 26 | config CPU_S3C2410 |
| 27 | bool |
| 28 | depends on ARCH_S3C2410 |
| 29 | diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile |
| 30 | --- linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile 2008-01-27 17:58:41.000000000 +0100 |
| 31 | +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile 2010-02-18 01:19:18.503894425 +0100 |
| 32 | @@ -5,17 +5,19 @@ |
| 33 | |
| 34 | # Object file lists. |
| 35 | |
| 36 | -obj-y := cpu.o irq.o time.o gpio.o clock.o devs.o |
| 37 | +obj-y := cpu.o time.o gpio.o clock.o devs.o |
| 38 | obj-m := |
| 39 | obj-n := |
| 40 | obj- := |
| 41 | |
| 42 | # S3C2400 support files |
| 43 | +obj-$(CONFIG_CPU_S3C2400) += s3c2400.o |
| 44 | +obj-$(CONFIG_CPU_S3C2400) += s3c2400-irq.o |
| 45 | obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o |
| 46 | |
| 47 | # S3C2410 support files |
| 48 | |
| 49 | -obj-$(CONFIG_CPU_S3C2410) += s3c2410.o |
| 50 | +obj-$(CONFIG_CPU_S3C2410) += s3c2410.o irq.o |
| 51 | obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o |
| 52 | obj-$(CONFIG_S3C2410_DMA) += dma.o |
| 53 | |
| 54 | @@ -27,7 +29,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec. |
| 55 | # S3C2440 support |
| 56 | |
| 57 | obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o |
| 58 | -obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o |
| 59 | +obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o irq.o |
| 60 | obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o |
| 61 | obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o |
| 62 | |
| 63 | @@ -40,6 +42,7 @@ obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq |
| 64 | obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o |
| 65 | obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o |
| 66 | obj-$(CONFIG_ARCH_H1940) += mach-h1940.o |
| 67 | +obj-$(CONFIG_MACH_GP32) += mach-gp32.o |
| 68 | obj-$(CONFIG_MACH_N30) += mach-n30.o |
| 69 | obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o |
| 70 | obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o |
| 71 | diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile.boot linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile.boot |
| 72 | --- linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile.boot 2008-01-27 17:58:41.000000000 +0100 |
| 73 | +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile.boot 2010-02-18 01:13:59.467897060 +0100 |
| 74 | @@ -1,3 +1,7 @@ |
| 75 | +ifeq ($(CONFIG_CPU_S3C2400),y) |
| 76 | + zreladdr-y := 0x0c008000 |
| 77 | +params_phys-y := 0x0c000100 |
| 78 | +else |
| 79 | zreladdr-y := 0x30008000 |
| 80 | params_phys-y := 0x30000100 |
| 81 | - |
| 82 | +endif |
| 83 | diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/devs.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/devs.c |
| 84 | --- linux-2.6.16.60/arch/arm/mach-s3c2410/devs.c 2008-01-27 17:58:41.000000000 +0100 |
| 85 | +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/devs.c 2010-02-18 02:20:22.071894261 +0100 |
| 86 | @@ -273,11 +273,19 @@ static struct resource s3c_adc_resource[ |
| 87 | .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1, |
| 88 | .flags = IORESOURCE_MEM, |
| 89 | }, |
| 90 | +#ifdef CONFIG_CPU_S3C2400 |
| 91 | + [1] = { |
| 92 | + .start = IRQ_ADC, |
| 93 | + .end = IRQ_ADC, |
| 94 | + .flags = IORESOURCE_IRQ, |
| 95 | + }, |
| 96 | +#else |
| 97 | [1] = { |
| 98 | .start = IRQ_TC, |
| 99 | - .end = IRQ_TC, |
| 100 | + .end = IRQ_ADC, |
| 101 | .flags = IORESOURCE_IRQ, |
| 102 | }, |
| 103 | +#endif |
| 104 | [2] = { |
| 105 | .start = IRQ_ADC, |
| 106 | .end = IRQ_ADC, |
| 107 | diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/irq.h linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/irq.h |
| 108 | --- linux-2.6.16.60/arch/arm/mach-s3c2410/irq.h 2008-01-27 17:58:41.000000000 +0100 |
| 109 | +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/irq.h 2010-02-18 02:38:04.967896102 +0100 |
| 110 | @@ -17,8 +17,6 @@ |
| 111 | |
| 112 | #define EXTINT_OFF (IRQ_EINT4 - 4) |
| 113 | |
| 114 | -extern struct irqchip s3c_irq_level_chip; |
| 115 | - |
| 116 | static inline void |
| 117 | s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, |
| 118 | int subcheck) |
| 119 | diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/mach-gp32.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/mach-gp32.c |
| 120 | --- linux-2.6.16.60/arch/arm/mach-s3c2410/mach-gp32.c 1970-01-01 01:00:00.000000000 +0100 |
| 121 | +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/mach-gp32.c 2010-02-18 01:19:10.259895346 +0100 |
| 122 | @@ -0,0 +1,108 @@ |
| 123 | +/* linux/arch/arm/mach-s3c2410/mach-gp32.c |
| 124 | + * |
| 125 | + * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org> |
| 126 | + * |
| 127 | + * http://sourceforge.net/projects/gp32linux |
| 128 | + * |
| 129 | + * This program is free software; you can redistribute it and/or modify |
| 130 | + * it under the terms of the GNU General Public License version 2 as |
| 131 | + * published by the Free Software Foundation. |
| 132 | + * |
| 133 | + * Modifications: |
| 134 | + * 15-Jan-2006 LCVR Created initial version |
| 135 | +*/ |
| 136 | + |
| 137 | +#include <linux/kernel.h> |
| 138 | +#include <linux/types.h> |
| 139 | +#include <linux/interrupt.h> |
| 140 | +#include <linux/list.h> |
| 141 | +#include <linux/timer.h> |
| 142 | +#include <linux/init.h> |
| 143 | +#include <linux/platform_device.h> |
| 144 | +#include <linux/serial_core.h> |
| 145 | + |
| 146 | +#include <asm/arch/gp32-map.h> |
| 147 | +#include <asm/mach/arch.h> |
| 148 | +#include <asm/mach/map.h> |
| 149 | +#include <asm/mach/irq.h> |
| 150 | + |
| 151 | +#include <asm/hardware.h> |
| 152 | +#include <asm/io.h> |
| 153 | +#include <asm/irq.h> |
| 154 | +#include <asm/mach-types.h> |
| 155 | + |
| 156 | +#include <asm/arch/regs-serial.h> |
| 157 | +#include <asm/arch/regs-gpio.h> |
| 158 | +#include <asm/arch/regs-mem.h> |
| 159 | + |
| 160 | +#include "clock.h" |
| 161 | +#include "devs.h" |
| 162 | +#include "cpu.h" |
| 163 | + |
| 164 | +static struct map_desc gp32_iodesc[] __initdata = { |
| 165 | + /* dump ISA space somewhere unused */ |
| 166 | + |
| 167 | + { (u32)S3C24XX_VA_ISA_WORD, S3C2400_CS3, SZ_16M, MT_DEVICE }, |
| 168 | + { (u32)S3C24XX_VA_ISA_BYTE, S3C2400_CS3, SZ_16M, MT_DEVICE }, |
| 169 | + |
| 170 | + /* the BOOT-ROM is assigned to the nGCS0 */ |
| 171 | + |
| 172 | + { GP32_VA_BOOT_ROM, S3C2400_CS0, SZ_16M, MT_DEVICE }, |
| 173 | +}; |
| 174 | + |
| 175 | +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK |
| 176 | +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB |
| 177 | +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE |
| 178 | + |
| 179 | +static struct s3c2410_uartcfg gp32_uartcfgs[] = { |
| 180 | + [0] = { |
| 181 | + .hwport = 0, |
| 182 | + .flags = 0, |
| 183 | + .ucon = UCON, |
| 184 | + .ulcon = ULCON, |
| 185 | + .ufcon = UFCON, |
| 186 | + }, |
| 187 | + [1] = { |
| 188 | + .hwport = 1, |
| 189 | + .flags = 0, |
| 190 | + .ucon = UCON, |
| 191 | + .ulcon = ULCON, |
| 192 | + .ufcon = UFCON, |
| 193 | + } |
| 194 | +}; |
| 195 | + |
| 196 | +/* GP32 devices */ |
| 197 | + |
| 198 | +static struct platform_device *gp32_devices[] __initdata = { |
| 199 | + &s3c_device_usb, |
| 200 | + &s3c_device_usbgadget, |
| 201 | + &s3c_device_lcd, |
| 202 | + &s3c_device_wdt, |
| 203 | + &s3c_device_i2c, |
| 204 | + &s3c_device_iis, |
| 205 | + &s3c_device_spi0, |
| 206 | +}; |
| 207 | + |
| 208 | +static struct s3c24xx_board gp32_board __initdata = { |
| 209 | + .devices = gp32_devices, |
| 210 | + .devices_count = ARRAY_SIZE(gp32_devices), |
| 211 | +}; |
| 212 | + |
| 213 | + |
| 214 | +void __init gp32_map_io(void) |
| 215 | +{ |
| 216 | + s3c24xx_init_io(gp32_iodesc, ARRAY_SIZE(gp32_iodesc)); |
| 217 | + s3c24xx_init_clocks(0); |
| 218 | + s3c24xx_init_uarts(gp32_uartcfgs, ARRAY_SIZE(gp32_uartcfgs)); |
| 219 | + s3c24xx_set_board(&gp32_board); |
| 220 | +} |
| 221 | + |
| 222 | +MACHINE_START(GP32, "GamePark GP32") |
| 223 | + /* Maintainer: Lucas Correia Villa Real <lucasvr@gobolinux.org> */ |
| 224 | + .phys_io = S3C2400_PA_UART, |
| 225 | + .io_pg_offst = ((u32)S3C24XX_VA_UART >> 18) & 0xfffc, |
| 226 | + .boot_params = S3C2400_SDRAM_PA + 0x100, |
| 227 | + .map_io = gp32_map_io, |
| 228 | + .init_irq = s3c24xx_init_irq, |
| 229 | + .timer = &s3c24xx_timer, |
| 230 | +MACHINE_END |
| 231 | diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400-irq.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400-irq.c |
| 232 | --- linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400-irq.c 1970-01-01 01:00:00.000000000 +0100 |
| 233 | +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400-irq.c 2010-02-18 02:27:58.571895480 +0100 |
| 234 | @@ -0,0 +1,308 @@ |
| 235 | +/* linux/arch/arm/mach-s3c2410/s3c2400-irq.c |
| 236 | + * |
| 237 | + * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org> |
| 238 | + * |
| 239 | + * Based on mach-s3c2410/irq.c, |
| 240 | + * Copyright (c) 2003,2004 Simtec Electronics |
| 241 | + * Ben Dooks <ben@simtec.co.uk> |
| 242 | + * |
| 243 | + * This program is free software; you can redistribute it and/or modify |
| 244 | + * it under the terms of the GNU General Public License as published by |
| 245 | + * the Free Software Foundation; either version 2 of the License, or |
| 246 | + * (at your option) any later version. |
| 247 | + * |
| 248 | + * This program is distributed in the hope that it will be useful, |
| 249 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 250 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 251 | + * GNU General Public License for more details. |
| 252 | + * |
| 253 | + * You should have received a copy of the GNU General Public License |
| 254 | + * along with this program; if not, write to the Free Software |
| 255 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 256 | + * |
| 257 | + * Changelog: |
| 258 | + * |
| 259 | + * 19-Jan-2006 Lucas Correia Villa Real <lucasvr@gobolinux.org> |
| 260 | + * First version, based on S3C2410 code |
| 261 | +*/ |
| 262 | + |
| 263 | +#include <linux/init.h> |
| 264 | +#include <linux/module.h> |
| 265 | +#include <linux/interrupt.h> |
| 266 | +#include <linux/ioport.h> |
| 267 | +#include <linux/ptrace.h> |
| 268 | +#include <linux/sysdev.h> |
| 269 | + |
| 270 | +#include <asm/hardware.h> |
| 271 | +#include <asm/irq.h> |
| 272 | +#include <asm/io.h> |
| 273 | + |
| 274 | +#include <asm/mach/irq.h> |
| 275 | + |
| 276 | +#include <asm/arch/regs-irq.h> |
| 277 | +#include <asm/arch/regs-gpio.h> |
| 278 | + |
| 279 | +#include "cpu.h" |
| 280 | +#include "pm.h" |
| 281 | +#include "irq.h" |
| 282 | + |
| 283 | + |
| 284 | +/* wakeup irq control */ |
| 285 | + |
| 286 | +#ifdef CONFIG_PM |
| 287 | + |
| 288 | +/* state for IRQs over sleep */ |
| 289 | + |
| 290 | +/* default is to allow for EINT0..EINT7, and IRQ_RTC as wakeup sources |
| 291 | + * |
| 292 | + * set bit to 1 in allow bitfield to enable the wakeup settings on it |
| 293 | +*/ |
| 294 | + |
| 295 | +unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xffL; |
| 296 | +unsigned long s3c_irqwake_intmask = 0xffffffffL; |
| 297 | + |
| 298 | +static int |
| 299 | +s3c_irq_wake(unsigned int irqno, unsigned int state) |
| 300 | +{ |
| 301 | + unsigned long irqbit = 1 << (irqno - IRQ_EINT0); |
| 302 | + |
| 303 | + if (!(s3c_irqwake_intallow & irqbit)) |
| 304 | + return -ENOENT; |
| 305 | + |
| 306 | + printk(KERN_INFO "wake %s for irq %d\n", |
| 307 | + state ? "enabled" : "disabled", irqno); |
| 308 | + |
| 309 | + if (!state) |
| 310 | + s3c_irqwake_intmask |= irqbit; |
| 311 | + else |
| 312 | + s3c_irqwake_intmask &= ~irqbit; |
| 313 | + |
| 314 | + return 0; |
| 315 | +} |
| 316 | + |
| 317 | +#else |
| 318 | +#define s3c_irq_wake NULL |
| 319 | +#endif |
| 320 | + |
| 321 | + |
| 322 | +static void |
| 323 | +s3c_irq_mask(unsigned int irqno) |
| 324 | +{ |
| 325 | + unsigned long mask; |
| 326 | + |
| 327 | + irqno -= IRQ_EINT0; |
| 328 | + |
| 329 | + mask = __raw_readl(S3C2410_INTMSK); |
| 330 | + mask |= 1UL << irqno; |
| 331 | + __raw_writel(mask, S3C2410_INTMSK); |
| 332 | +} |
| 333 | + |
| 334 | +static inline void |
| 335 | +s3c_irq_ack(unsigned int irqno) |
| 336 | +{ |
| 337 | + unsigned long bitval = 1UL << (irqno - IRQ_EINT0); |
| 338 | + |
| 339 | + __raw_writel(bitval, S3C2410_SRCPND); |
| 340 | + __raw_writel(bitval, S3C2410_INTPND); |
| 341 | +} |
| 342 | + |
| 343 | +static inline void |
| 344 | +s3c_irq_maskack(unsigned int irqno) |
| 345 | +{ |
| 346 | + unsigned long bitval = 1UL << (irqno - IRQ_EINT0); |
| 347 | + unsigned long mask; |
| 348 | + |
| 349 | + mask = __raw_readl(S3C2410_INTMSK); |
| 350 | + __raw_writel(mask|bitval, S3C2410_INTMSK); |
| 351 | + |
| 352 | + __raw_writel(bitval, S3C2410_SRCPND); |
| 353 | + __raw_writel(bitval, S3C2410_INTPND); |
| 354 | +} |
| 355 | + |
| 356 | + |
| 357 | +static void |
| 358 | +s3c_irq_unmask(unsigned int irqno) |
| 359 | +{ |
| 360 | + unsigned long mask; |
| 361 | + |
| 362 | + irqno -= IRQ_EINT0; |
| 363 | + |
| 364 | + mask = __raw_readl(S3C2410_INTMSK); |
| 365 | + mask &= ~(1UL << irqno); |
| 366 | + __raw_writel(mask, S3C2410_INTMSK); |
| 367 | +} |
| 368 | + |
| 369 | +static struct irqchip s3c_irq_level_chip = { |
| 370 | + .ack = s3c_irq_maskack, |
| 371 | + .mask = s3c_irq_mask, |
| 372 | + .unmask = s3c_irq_unmask, |
| 373 | + .set_wake = s3c_irq_wake |
| 374 | +}; |
| 375 | + |
| 376 | +static struct irqchip s3c_irq_chip = { |
| 377 | + .ack = s3c_irq_ack, |
| 378 | + .mask = s3c_irq_mask, |
| 379 | + .unmask = s3c_irq_unmask, |
| 380 | + .set_wake = s3c_irq_wake |
| 381 | +}; |
| 382 | + |
| 383 | + |
| 384 | +static int |
| 385 | +s3c_irqext_type(unsigned int irq, unsigned int type) |
| 386 | +{ |
| 387 | + unsigned long gpcon_offset, extint_offset; |
| 388 | + unsigned long newvalue = 0, value; |
| 389 | + |
| 390 | + if ((irq < IRQ_EINT0) || (irq > IRQ_EINT7)) |
| 391 | + return -1; |
| 392 | + |
| 393 | + gpcon_offset = (irq - IRQ_EINT0) * 2; |
| 394 | + extint_offset = (irq - IRQ_EINT0) * 4; |
| 395 | + |
| 396 | + /* Set the GPIO to external interrupt mode */ |
| 397 | + value = __raw_readl(S3C2400_GPECON); |
| 398 | + value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); |
| 399 | + __raw_writel(value, S3C2400_GPECON); |
| 400 | + |
| 401 | + /* Set the external interrupt to pointed trigger type */ |
| 402 | + switch (type) |
| 403 | + { |
| 404 | + case IRQT_NOEDGE: |
| 405 | + printk(KERN_WARNING "No edge setting!\n"); |
| 406 | + break; |
| 407 | + |
| 408 | + case IRQT_RISING: |
| 409 | + newvalue = S3C2410_EXTINT_RISEEDGE; |
| 410 | + break; |
| 411 | + |
| 412 | + case IRQT_FALLING: |
| 413 | + newvalue = S3C2410_EXTINT_FALLEDGE; |
| 414 | + break; |
| 415 | + |
| 416 | + case IRQT_BOTHEDGE: |
| 417 | + newvalue = S3C2410_EXTINT_BOTHEDGE; |
| 418 | + break; |
| 419 | + |
| 420 | + case IRQT_LOW: |
| 421 | + newvalue = S3C2410_EXTINT_LOWLEV; |
| 422 | + break; |
| 423 | + |
| 424 | + case IRQT_HIGH: |
| 425 | + newvalue = S3C2410_EXTINT_HILEV; |
| 426 | + break; |
| 427 | + |
| 428 | + default: |
| 429 | + printk(KERN_ERR "No such irq type %d", type); |
| 430 | + return -1; |
| 431 | + } |
| 432 | + |
| 433 | + value = __raw_readl(S3C2400_EXTINT0); |
| 434 | + value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); |
| 435 | + __raw_writel(value, S3C2400_EXTINT0); |
| 436 | + |
| 437 | + return 0; |
| 438 | +} |
| 439 | + |
| 440 | +static struct irqchip s3c_irq_eint = { |
| 441 | + .ack = s3c_irq_ack, |
| 442 | + .mask = s3c_irq_mask, |
| 443 | + .unmask = s3c_irq_unmask, |
| 444 | + .set_wake = s3c_irq_wake, |
| 445 | + .set_type = s3c_irqext_type, |
| 446 | +}; |
| 447 | + |
| 448 | + |
| 449 | +/* s3c24xx_init_irq |
| 450 | + * |
| 451 | + * Initialise S3C2400 IRQ system |
| 452 | +*/ |
| 453 | + |
| 454 | +void __init s3c24xx_init_irq(void) |
| 455 | +{ |
| 456 | + unsigned long pend; |
| 457 | + unsigned long last; |
| 458 | + int irqno, uart_irq[3]; |
| 459 | + int i; |
| 460 | + |
| 461 | + irqdbf("s3c24xx_init_irq: clearing interrupt status flags\n"); |
| 462 | + |
| 463 | + /* first, clear all interrupts pending... */ |
| 464 | + |
| 465 | + last = 0; |
| 466 | + for (i = 0; i < 4; i++) { |
| 467 | + pend = __raw_readl(S3C2410_INTPND); |
| 468 | + |
| 469 | + if (pend == 0 || pend == last) |
| 470 | + break; |
| 471 | + |
| 472 | + __raw_writel(pend, S3C2410_SRCPND); |
| 473 | + __raw_writel(pend, S3C2410_INTPND); |
| 474 | + printk("irq: clearing pending status %08x\n", (int)pend); |
| 475 | + last = pend; |
| 476 | + } |
| 477 | + |
| 478 | + /* register the main interrupts */ |
| 479 | + |
| 480 | + irqdbf("s3c24xx_init_irq: registering s3c2400 interrupt handlers\n"); |
| 481 | + |
| 482 | + for (irqno = IRQ_TICK; irqno <= IRQ_ADCPARENT; irqno++) { |
| 483 | + /* set all the s3c2400 internal irqs */ |
| 484 | + |
| 485 | + switch (irqno) { |
| 486 | + /* deal with the special IRQs (cascaded) */ |
| 487 | + |
| 488 | + case IRQ_UTXD0: |
| 489 | + case IRQ_UTXD1: |
| 490 | + case IRQ_URXD0: |
| 491 | + case IRQ_URXD1: |
| 492 | + case IRQ_UERR01: |
| 493 | + case IRQ_ADCPARENT: |
| 494 | + set_irq_chip(irqno, &s3c_irq_level_chip); |
| 495 | + set_irq_handler(irqno, do_level_IRQ); |
| 496 | + break; |
| 497 | + |
| 498 | + case IRQ_RESERVED6: |
| 499 | + case IRQ_RESERVED16: |
| 500 | + /* no IRQ here */ |
| 501 | + break; |
| 502 | + |
| 503 | + default: |
| 504 | + //irqdbf("registering irq %d (s3c irq)\n", irqno); |
| 505 | + set_irq_chip(irqno, &s3c_irq_chip); |
| 506 | + set_irq_handler(irqno, do_edge_IRQ); |
| 507 | + set_irq_flags(irqno, IRQF_VALID); |
| 508 | + } |
| 509 | + } |
| 510 | + |
| 511 | + /* external interrupts */ |
| 512 | + |
| 513 | + for (irqno = IRQ_EINT0; irqno <= IRQ_EINT7; irqno++) { |
| 514 | + irqdbf("registering irq %d (ext int)\n", irqno); |
| 515 | + set_irq_chip(irqno, &s3c_irq_eint); |
| 516 | + set_irq_handler(irqno, do_edge_IRQ); |
| 517 | + set_irq_flags(irqno, IRQF_VALID); |
| 518 | + } |
| 519 | + |
| 520 | + /* register the uart interrupts */ |
| 521 | + |
| 522 | + uart_irq[0] = IRQ_URXD0; |
| 523 | + uart_irq[1] = IRQ_UTXD0; |
| 524 | + uart_irq[2] = IRQ_UERR01; |
| 525 | + for (i = 0; i < 3; i++) { |
| 526 | + irqdbf("registering irq %d (s3c uart0 irq)\n", uart_irq[i]); |
| 527 | + set_irq_chip(uart_irq[i], &s3c_irq_chip); |
| 528 | + set_irq_handler(uart_irq[i], do_level_IRQ); |
| 529 | + set_irq_flags(uart_irq[i], IRQF_VALID); |
| 530 | + } |
| 531 | + |
| 532 | + uart_irq[0] = IRQ_URXD1; |
| 533 | + uart_irq[1] = IRQ_UTXD1; |
| 534 | + for (i = 0; i < 2; i++) { |
| 535 | + irqdbf("registering irq %d (s3c uart1 irq)\n", uart_irq[i]); |
| 536 | + set_irq_chip(uart_irq[i], &s3c_irq_chip); |
| 537 | + set_irq_handler(uart_irq[i], do_level_IRQ); |
| 538 | + set_irq_flags(uart_irq[i], IRQF_VALID); |
| 539 | + } |
| 540 | + |
| 541 | + irqdbf("s3c2400: registered interrupt handlers\n"); |
| 542 | +} |
| 543 | diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400.c |
| 544 | --- linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400.c 1970-01-01 01:00:00.000000000 +0100 |
| 545 | +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400.c 2010-02-18 01:13:59.467897060 +0100 |
| 546 | @@ -0,0 +1,167 @@ |
| 547 | +/* linux/arch/arm/mach-s3c2410/s3c2400.c |
| 548 | + * |
| 549 | + * Copyright (c) 2003-2006 Simtec Electronics |
| 550 | + * Ben Dooks <ben@simtec.co.uk> |
| 551 | + * |
| 552 | + * This program is free software; you can redistribute it and/or modify |
| 553 | + * it under the terms of the GNU General Public License version 2 as |
| 554 | + * published by the Free Software Foundation. |
| 555 | + * |
| 556 | + * Modifications: |
| 557 | + * 15-Jan-2006 LCVR First version, based on s3c2410.c |
| 558 | +*/ |
| 559 | + |
| 560 | +#include <linux/kernel.h> |
| 561 | +#include <linux/types.h> |
| 562 | +#include <linux/interrupt.h> |
| 563 | +#include <linux/list.h> |
| 564 | +#include <linux/timer.h> |
| 565 | +#include <linux/init.h> |
| 566 | +#include <linux/platform_device.h> |
| 567 | + |
| 568 | +#include <asm/mach/arch.h> |
| 569 | +#include <asm/mach/map.h> |
| 570 | +#include <asm/mach/irq.h> |
| 571 | + |
| 572 | +#include <asm/hardware.h> |
| 573 | +#include <asm/io.h> |
| 574 | +#include <asm/irq.h> |
| 575 | + |
| 576 | +#include <asm/arch/regs-clock.h> |
| 577 | +#include <asm/arch/regs-serial.h> |
| 578 | + |
| 579 | +#include "s3c2400.h" |
| 580 | +#include "cpu.h" |
| 581 | +#include "clock.h" |
| 582 | + |
| 583 | +/* Initial IO mappings */ |
| 584 | + |
| 585 | +static struct map_desc s3c2400_iodesc[] __initdata = { |
| 586 | + IODESC_ENT(USBHOST), |
| 587 | + IODESC_ENT(USBDEV), |
| 588 | + IODESC_ENT(CLKPWR), |
| 589 | + IODESC_ENT(LCD), |
| 590 | + IODESC_ENT(TIMER), |
| 591 | + IODESC_ENT(ADC), |
| 592 | + IODESC_ENT(WATCHDOG) |
| 593 | +}; |
| 594 | + |
| 595 | +static struct resource s3c_uart0_resource[] = { |
| 596 | + [0] = { |
| 597 | + .start = S3C2410_PA_UART0, |
| 598 | + .end = S3C2410_PA_UART0 + 0x3fff, |
| 599 | + .flags = IORESOURCE_MEM, |
| 600 | + }, |
| 601 | + [1] = { |
| 602 | + .start = IRQ_S3CUART_RX0, |
| 603 | + .end = IRQ_S3CUART_ERR0, |
| 604 | + .flags = IORESOURCE_IRQ, |
| 605 | + } |
| 606 | + |
| 607 | +}; |
| 608 | + |
| 609 | +static struct resource s3c_uart1_resource[] = { |
| 610 | + [0] = { |
| 611 | + .start = S3C2410_PA_UART1, |
| 612 | + .end = S3C2410_PA_UART1 + 0x3fff, |
| 613 | + .flags = IORESOURCE_MEM, |
| 614 | + }, |
| 615 | + [1] = { |
| 616 | + .start = IRQ_S3CUART_RX1, |
| 617 | + .end = IRQ_S3CUART_ERR1, |
| 618 | + .flags = IORESOURCE_IRQ, |
| 619 | + } |
| 620 | +}; |
| 621 | + |
| 622 | +/* our uart devices */ |
| 623 | + |
| 624 | +static struct platform_device s3c_uart0 = { |
| 625 | + .name = "s3c2400-uart", |
| 626 | + .id = 0, |
| 627 | + .num_resources = ARRAY_SIZE(s3c_uart0_resource), |
| 628 | + .resource = s3c_uart0_resource, |
| 629 | +}; |
| 630 | + |
| 631 | + |
| 632 | +static struct platform_device s3c_uart1 = { |
| 633 | + .name = "s3c2400-uart", |
| 634 | + .id = 1, |
| 635 | + .num_resources = ARRAY_SIZE(s3c_uart1_resource), |
| 636 | + .resource = s3c_uart1_resource, |
| 637 | +}; |
| 638 | + |
| 639 | +static struct platform_device *uart_devices[] __initdata = { |
| 640 | + &s3c_uart0, |
| 641 | + &s3c_uart1 |
| 642 | +}; |
| 643 | + |
| 644 | +static int s3c2400_uart_count = 0; |
| 645 | + |
| 646 | +/* uart registration process */ |
| 647 | + |
| 648 | +void __init s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
| 649 | +{ |
| 650 | + struct platform_device *platdev; |
| 651 | + int uart; |
| 652 | + |
| 653 | + for (uart = 0; uart < no; uart++, cfg++) { |
| 654 | + platdev = uart_devices[cfg->hwport]; |
| 655 | + |
| 656 | + s3c24xx_uart_devs[uart] = platdev; |
| 657 | + platdev->dev.platform_data = cfg; |
| 658 | + } |
| 659 | + |
| 660 | + s3c2400_uart_count = uart; |
| 661 | +} |
| 662 | + |
| 663 | +/* s3c2400_map_io |
| 664 | + * |
| 665 | + * register the standard cpu IO areas, and any passed in from the |
| 666 | + * machine specific initialisation. |
| 667 | +*/ |
| 668 | + |
| 669 | +void __init s3c2400_map_io(struct map_desc *mach_desc, int mach_size) |
| 670 | +{ |
| 671 | + /* register our io-tables */ |
| 672 | + |
| 673 | + iotable_init(s3c2400_iodesc, ARRAY_SIZE(s3c2400_iodesc)); |
| 674 | + iotable_init(mach_desc, mach_size); |
| 675 | +} |
| 676 | + |
| 677 | +void __init s3c2400_init_clocks(int xtal) |
| 678 | +{ |
| 679 | + unsigned long tmp; |
| 680 | + unsigned long fclk; |
| 681 | + unsigned long hclk; |
| 682 | + unsigned long pclk; |
| 683 | + |
| 684 | + /* now we've got our machine bits initialised, work out what |
| 685 | + * clocks we've got */ |
| 686 | + |
| 687 | + fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); |
| 688 | + |
| 689 | + tmp = __raw_readl(S3C2410_CLKDIVN); |
| 690 | + |
| 691 | + /* work out clock scalings */ |
| 692 | + |
| 693 | + hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); |
| 694 | + pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); |
| 695 | + |
| 696 | + /* print brieft summary of clocks, etc */ |
| 697 | + |
| 698 | + printk("S3C2400: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", |
| 699 | + print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); |
| 700 | + |
| 701 | + /* initialise the clocks here, to allow other things like the |
| 702 | + * console to use them |
| 703 | + */ |
| 704 | + |
| 705 | + s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); |
| 706 | +} |
| 707 | + |
| 708 | +int __init s3c2400_init(void) |
| 709 | +{ |
| 710 | + printk("S3C2400: Initialising architecture\n"); |
| 711 | + |
| 712 | + return platform_add_devices(s3c24xx_uart_devs, s3c2400_uart_count); |
| 713 | +} |
| 714 | diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/entry-macro.S linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/entry-macro.S |
| 715 | --- linux-2.6.16.60/include/asm-arm/arch-s3c2410/entry-macro.S 2008-01-27 17:58:41.000000000 +0100 |
| 716 | +++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/entry-macro.S 2010-02-18 01:19:18.503894425 +0100 |
| 717 | @@ -9,6 +9,7 @@ |
| 718 | |
| 719 | * Modifications: |
| 720 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA |
| 721 | + * 19-Jan-2006 LCVR Added support to S3C2400 |
| 722 | */ |
| 723 | #include <asm/hardware.h> |
| 724 | #include <asm/arch/irqs.h> |
| 725 | @@ -19,10 +20,11 @@ |
| 726 | mov \tmp, #S3C24XX_VA_IRQ |
| 727 | ldr \irqnr, [ \tmp, #0x14 ] @ get irq no |
| 728 | 30000: |
| 729 | +#ifndef CONFIG_CPU_S3C2400 |
| 730 | teq \irqnr, #4 |
| 731 | teqne \irqnr, #5 |
| 732 | beq 1002f @ external irq reg |
| 733 | - |
| 734 | +#endif |
| 735 | @ debug check to see if interrupt reported is the same |
| 736 | @ as the offset.... |
| 737 | |
| 738 | @@ -97,6 +99,7 @@ |
| 739 | mov \irqnr, #IRQ_EINT4 @ start extint nos |
| 740 | mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits |
| 741 | 10021: |
| 742 | +#ifndef CONFIG_CPU_S3C2400 |
| 743 | movs \irqstat, \irqstat, lsr#1 |
| 744 | bcs 1004f |
| 745 | add \irqnr, \irqnr, #1 |
| 746 | @@ -105,6 +108,7 @@ |
| 747 | |
| 748 | @ found no interrupt, set Z flag and leave |
| 749 | movs \irqnr, #0 |
| 750 | +#endif |
| 751 | |
| 752 | 1004: @ ensure Z flag clear in case our MOVS shifted out the last bit |
| 753 | teq \irqnr, #0 |
| 754 | diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/gp32-map.h linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/gp32-map.h |
| 755 | --- linux-2.6.16.60/include/asm-arm/arch-s3c2410/gp32-map.h 1970-01-01 01:00:00.000000000 +0100 |
| 756 | +++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/gp32-map.h 2010-02-18 01:19:10.259895346 +0100 |
| 757 | @@ -0,0 +1,23 @@ |
| 758 | +/* linux/include/asm-arm/arch-s3c2410/gp32-map.h |
| 759 | + * |
| 760 | + * Copyright (c) 2005 Lucas Correia Villa Real <lucasvr@gobolinux.org> |
| 761 | + * |
| 762 | + * Machine GP32 - Memory map definitions |
| 763 | + * |
| 764 | + * This program is free software; you can redistribute it and/or modify |
| 765 | + * it under the terms of the GNU General Public License version 2 as |
| 766 | + * published by the Free Software Foundation. |
| 767 | + * |
| 768 | +*/ |
| 769 | + |
| 770 | +/* needs arch/map.h including with this */ |
| 771 | + |
| 772 | +#ifndef __ASM_ARCH_GP32MAP_H |
| 773 | +#define __ASM_ARCH_GP32MAP_H |
| 774 | + |
| 775 | +#define GP32_IOADDR(x) (0xC0000000 + (x)) |
| 776 | + |
| 777 | +/* maps the BOOT ROM, which is connected to nGCS0 */ |
| 778 | +#define GP32_VA_BOOT_ROM GP32_IOADDR(0x00000000) |
| 779 | + |
| 780 | +#endif /* __ASM_ARCH_GP32MAP_H */ |
| 781 | diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/irqs.h linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/irqs.h |
| 782 | --- linux-2.6.16.60/include/asm-arm/arch-s3c2410/irqs.h 2008-01-27 17:58:41.000000000 +0100 |
| 783 | +++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/irqs.h 2010-02-18 01:19:18.503894425 +0100 |
| 784 | @@ -13,6 +13,7 @@ |
| 785 | * 12-Mar-2004 BJD Fixed bug in header protection |
| 786 | * 10-Feb-2005 BJD Added camera IRQ from guillaume.gourat@nexvision.tv |
| 787 | * 28-Feb-2005 BJD Updated s3c2440 IRQs |
| 788 | + * 19-Jan-2006 LCVR Added S3C2400 definitions |
| 789 | */ |
| 790 | |
| 791 | |
| 792 | @@ -48,24 +49,53 @@ |
| 793 | #define IRQ_TIMER3 S3C2410_IRQ(13) |
| 794 | #define IRQ_TIMER4 S3C2410_IRQ(14) |
| 795 | #define IRQ_UART2 S3C2410_IRQ(15) |
| 796 | +#define IRQ_UERR01 S3C2410_IRQ(15) /* for s3c2400 */ |
| 797 | #define IRQ_LCD S3C2410_IRQ(16) /* 32 */ |
| 798 | +#define IRQ_RESERVED16 S3C2410_IRQ(16) /* for s3c2400 */ |
| 799 | #define IRQ_DMA0 S3C2410_IRQ(17) |
| 800 | #define IRQ_DMA1 S3C2410_IRQ(18) |
| 801 | #define IRQ_DMA2 S3C2410_IRQ(19) |
| 802 | #define IRQ_DMA3 S3C2410_IRQ(20) |
| 803 | #define IRQ_SDI S3C2410_IRQ(21) |
| 804 | -#define IRQ_SPI0 S3C2410_IRQ(22) |
| 805 | +#define IRQ_MMC S3C2410_IRQ(21) /* for s3c2400 */ |
| 806 | +#define IRQ_SPI0 S3C2410_IRQ(22) /* s3c2400 has only 1 SPI */ |
| 807 | #define IRQ_UART1 S3C2410_IRQ(23) |
| 808 | +#define IRQ_URXD0 S3C2410_IRQ(23) /* for s3c2400 */ |
| 809 | +#define IRQ_URXD1 S3C2410_IRQ(24) /* for s3c2400 */ |
| 810 | #define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ |
| 811 | #define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ |
| 812 | #define IRQ_USBD S3C2410_IRQ(25) |
| 813 | #define IRQ_USBH S3C2410_IRQ(26) |
| 814 | #define IRQ_IIC S3C2410_IRQ(27) |
| 815 | #define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ |
| 816 | +#define IRQ_UTXD0 S3C2410_IRQ(28) /* for s3c2400 */ |
| 817 | +#define IRQ_UTXD1 S3C2410_IRQ(29) /* for s3c2400 */ |
| 818 | #define IRQ_SPI1 S3C2410_IRQ(29) |
| 819 | #define IRQ_RTC S3C2410_IRQ(30) |
| 820 | #define IRQ_ADCPARENT S3C2410_IRQ(31) |
| 821 | |
| 822 | +#ifdef CONFIG_CPU_S3C2400 |
| 823 | + |
| 824 | +/* interrupts generated from the external interrupts sources */ |
| 825 | +#define IRQ_EINT4 S3C2410_IRQ(4) |
| 826 | +#define IRQ_EINT5 S3C2410_IRQ(5) |
| 827 | +#define IRQ_EINT6 S3C2410_IRQ(6) |
| 828 | +#define IRQ_EINT7 S3C2410_IRQ(7) |
| 829 | +#define IRQ_ADC S3C2410_IRQ(31) |
| 830 | + |
| 831 | +/* aliases to keep compatibility with S3C2410 code */ |
| 832 | +#define IRQ_S3CUART_RX0 IRQ_URXD0 |
| 833 | +#define IRQ_S3CUART_TX0 IRQ_UTXD0 |
| 834 | +#define IRQ_S3CUART_ERR0 IRQ_UERR01 |
| 835 | + |
| 836 | +#define IRQ_S3CUART_RX1 IRQ_URXD1 |
| 837 | +#define IRQ_S3CUART_TX1 IRQ_UTXD1 |
| 838 | +#define IRQ_S3CUART_ERR1 IRQ_UERR01 |
| 839 | + |
| 840 | +#define NR_IRQS (IRQ_ADC+1) |
| 841 | + |
| 842 | +#else |
| 843 | + |
| 844 | /* interrupts generated from the external interrupts sources */ |
| 845 | #define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ |
| 846 | #define IRQ_EINT5 S3C2410_IRQ(33) |
| 847 | @@ -122,5 +152,6 @@ |
| 848 | |
| 849 | #define NR_IRQS (IRQ_S3C2440_AC97+1) |
| 850 | |
| 851 | +#endif /* CONFIG_CPU_S3C2400 */ |
| 852 | |
| 853 | #endif /* __ASM_ARCH_IRQ_H */ |