1 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Kconfig linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Kconfig
2 --- linux-2.6.16.60/arch/arm/mach-s3c2410/Kconfig 2008-01-27 17:58:41.000000000 +0100
3 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Kconfig 2010-02-18 01:19:10.259895346 +0100
4 @@ -86,8 +86,24 @@ config MACH_NEXCODER_2440
6 Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
10 + depends on EXPERIMENTAL
13 + Say Y here if you are using the GamePark GP32 handheld.
15 + See <http://sourceforge.net/projects/gp32linux> for more
16 + information on this project.
22 + depends on ARCH_S3C2410
24 + Support for the S3C2400 from S3C24XX line of Samsung Mobile CPUs.
28 depends on ARCH_S3C2410
29 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile
30 --- linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile 2008-01-27 17:58:41.000000000 +0100
31 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile 2010-02-18 01:19:18.503894425 +0100
36 -obj-y := cpu.o irq.o time.o gpio.o clock.o devs.o
37 +obj-y := cpu.o time.o gpio.o clock.o devs.o
42 # S3C2400 support files
43 +obj-$(CONFIG_CPU_S3C2400) += s3c2400.o
44 +obj-$(CONFIG_CPU_S3C2400) += s3c2400-irq.o
45 obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o
47 # S3C2410 support files
49 -obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
50 +obj-$(CONFIG_CPU_S3C2410) += s3c2410.o irq.o
51 obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o
52 obj-$(CONFIG_S3C2410_DMA) += dma.o
54 @@ -27,7 +29,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.
57 obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o
58 -obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o
59 +obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o irq.o
60 obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o
61 obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o
63 @@ -40,6 +42,7 @@ obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq
64 obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
65 obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o
66 obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
67 +obj-$(CONFIG_MACH_GP32) += mach-gp32.o
68 obj-$(CONFIG_MACH_N30) += mach-n30.o
69 obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
70 obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
71 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile.boot linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile.boot
72 --- linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile.boot 2008-01-27 17:58:41.000000000 +0100
73 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile.boot 2010-02-18 01:13:59.467897060 +0100
75 +ifeq ($(CONFIG_CPU_S3C2400),y)
76 + zreladdr-y := 0x0c008000
77 +params_phys-y := 0x0c000100
79 zreladdr-y := 0x30008000
80 params_phys-y := 0x30000100
83 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/devs.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/devs.c
84 --- linux-2.6.16.60/arch/arm/mach-s3c2410/devs.c 2008-01-27 17:58:41.000000000 +0100
85 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/devs.c 2010-02-18 02:20:22.071894261 +0100
86 @@ -273,11 +273,19 @@ static struct resource s3c_adc_resource[
87 .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
88 .flags = IORESOURCE_MEM,
90 +#ifdef CONFIG_CPU_S3C2400
94 + .flags = IORESOURCE_IRQ,
101 .flags = IORESOURCE_IRQ,
107 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/mach-gp32.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/mach-gp32.c
108 --- linux-2.6.16.60/arch/arm/mach-s3c2410/mach-gp32.c 1970-01-01 01:00:00.000000000 +0100
109 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/mach-gp32.c 2010-02-18 01:19:10.259895346 +0100
111 +/* linux/arch/arm/mach-s3c2410/mach-gp32.c
113 + * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
115 + * http://sourceforge.net/projects/gp32linux
117 + * This program is free software; you can redistribute it and/or modify
118 + * it under the terms of the GNU General Public License version 2 as
119 + * published by the Free Software Foundation.
122 + * 15-Jan-2006 LCVR Created initial version
125 +#include <linux/kernel.h>
126 +#include <linux/types.h>
127 +#include <linux/interrupt.h>
128 +#include <linux/list.h>
129 +#include <linux/timer.h>
130 +#include <linux/init.h>
131 +#include <linux/platform_device.h>
132 +#include <linux/serial_core.h>
134 +#include <asm/arch/gp32-map.h>
135 +#include <asm/mach/arch.h>
136 +#include <asm/mach/map.h>
137 +#include <asm/mach/irq.h>
139 +#include <asm/hardware.h>
141 +#include <asm/irq.h>
142 +#include <asm/mach-types.h>
144 +#include <asm/arch/regs-serial.h>
145 +#include <asm/arch/regs-gpio.h>
146 +#include <asm/arch/regs-mem.h>
152 +static struct map_desc gp32_iodesc[] __initdata = {
153 + /* dump ISA space somewhere unused */
155 + { (u32)S3C24XX_VA_ISA_WORD, S3C2400_CS3, SZ_16M, MT_DEVICE },
156 + { (u32)S3C24XX_VA_ISA_BYTE, S3C2400_CS3, SZ_16M, MT_DEVICE },
158 + /* the BOOT-ROM is assigned to the nGCS0 */
160 + { GP32_VA_BOOT_ROM, S3C2400_CS0, SZ_16M, MT_DEVICE },
163 +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
164 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
165 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
167 +static struct s3c2410_uartcfg gp32_uartcfgs[] = {
186 +static struct platform_device *gp32_devices[] __initdata = {
188 + &s3c_device_usbgadget,
196 +static struct s3c24xx_board gp32_board __initdata = {
197 + .devices = gp32_devices,
198 + .devices_count = ARRAY_SIZE(gp32_devices),
202 +void __init gp32_map_io(void)
204 + s3c24xx_init_io(gp32_iodesc, ARRAY_SIZE(gp32_iodesc));
205 + s3c24xx_init_clocks(0);
206 + s3c24xx_init_uarts(gp32_uartcfgs, ARRAY_SIZE(gp32_uartcfgs));
207 + s3c24xx_set_board(&gp32_board);
210 +MACHINE_START(GP32, "GamePark GP32")
211 + /* Maintainer: Lucas Correia Villa Real <lucasvr@gobolinux.org> */
212 + .phys_io = S3C2400_PA_UART,
213 + .io_pg_offst = ((u32)S3C24XX_VA_UART >> 18) & 0xfffc,
214 + .boot_params = S3C2400_SDRAM_PA + 0x100,
215 + .map_io = gp32_map_io,
216 + .init_irq = s3c24xx_init_irq,
217 + .timer = &s3c24xx_timer,
219 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400-irq.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400-irq.c
220 --- linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400-irq.c 1970-01-01 01:00:00.000000000 +0100
221 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400-irq.c 2010-02-18 02:27:58.571895480 +0100
223 +/* linux/arch/arm/mach-s3c2410/s3c2400-irq.c
225 + * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
227 + * Based on mach-s3c2410/irq.c,
228 + * Copyright (c) 2003,2004 Simtec Electronics
229 + * Ben Dooks <ben@simtec.co.uk>
231 + * This program is free software; you can redistribute it and/or modify
232 + * it under the terms of the GNU General Public License as published by
233 + * the Free Software Foundation; either version 2 of the License, or
234 + * (at your option) any later version.
236 + * This program is distributed in the hope that it will be useful,
237 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
238 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
239 + * GNU General Public License for more details.
241 + * You should have received a copy of the GNU General Public License
242 + * along with this program; if not, write to the Free Software
243 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
247 + * 19-Jan-2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
248 + * First version, based on S3C2410 code
251 +#include <linux/init.h>
252 +#include <linux/module.h>
253 +#include <linux/interrupt.h>
254 +#include <linux/ioport.h>
255 +#include <linux/ptrace.h>
256 +#include <linux/sysdev.h>
258 +#include <asm/hardware.h>
259 +#include <asm/irq.h>
262 +#include <asm/mach/irq.h>
264 +#include <asm/arch/regs-irq.h>
265 +#include <asm/arch/regs-gpio.h>
272 +/* wakeup irq control */
276 +/* state for IRQs over sleep */
278 +/* default is to allow for EINT0..EINT7, and IRQ_RTC as wakeup sources
280 + * set bit to 1 in allow bitfield to enable the wakeup settings on it
283 +unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xffL;
284 +unsigned long s3c_irqwake_intmask = 0xffffffffL;
287 +s3c_irq_wake(unsigned int irqno, unsigned int state)
289 + unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
291 + if (!(s3c_irqwake_intallow & irqbit))
294 + printk(KERN_INFO "wake %s for irq %d\n",
295 + state ? "enabled" : "disabled", irqno);
298 + s3c_irqwake_intmask |= irqbit;
300 + s3c_irqwake_intmask &= ~irqbit;
306 +#define s3c_irq_wake NULL
311 +s3c_irq_mask(unsigned int irqno)
313 + unsigned long mask;
315 + irqno -= IRQ_EINT0;
317 + mask = __raw_readl(S3C2410_INTMSK);
318 + mask |= 1UL << irqno;
319 + __raw_writel(mask, S3C2410_INTMSK);
323 +s3c_irq_ack(unsigned int irqno)
325 + unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
327 + __raw_writel(bitval, S3C2410_SRCPND);
328 + __raw_writel(bitval, S3C2410_INTPND);
332 +s3c_irq_maskack(unsigned int irqno)
334 + unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
335 + unsigned long mask;
337 + mask = __raw_readl(S3C2410_INTMSK);
338 + __raw_writel(mask|bitval, S3C2410_INTMSK);
340 + __raw_writel(bitval, S3C2410_SRCPND);
341 + __raw_writel(bitval, S3C2410_INTPND);
346 +s3c_irq_unmask(unsigned int irqno)
348 + unsigned long mask;
350 + irqno -= IRQ_EINT0;
352 + mask = __raw_readl(S3C2410_INTMSK);
353 + mask &= ~(1UL << irqno);
354 + __raw_writel(mask, S3C2410_INTMSK);
357 +static struct irqchip s3c_irq_level_chip = {
358 + .ack = s3c_irq_maskack,
359 + .mask = s3c_irq_mask,
360 + .unmask = s3c_irq_unmask,
361 + .set_wake = s3c_irq_wake
364 +static struct irqchip s3c_irq_chip = {
365 + .ack = s3c_irq_ack,
366 + .mask = s3c_irq_mask,
367 + .unmask = s3c_irq_unmask,
368 + .set_wake = s3c_irq_wake
373 +s3c_irqext_type(unsigned int irq, unsigned int type)
375 + unsigned long gpcon_offset, extint_offset;
376 + unsigned long newvalue = 0, value;
378 + if ((irq < IRQ_EINT0) || (irq > IRQ_EINT7))
381 + gpcon_offset = (irq - IRQ_EINT0) * 2;
382 + extint_offset = (irq - IRQ_EINT0) * 4;
384 + /* Set the GPIO to external interrupt mode */
385 + value = __raw_readl(S3C2400_GPECON);
386 + value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
387 + __raw_writel(value, S3C2400_GPECON);
389 + /* Set the external interrupt to pointed trigger type */
393 + printk(KERN_WARNING "No edge setting!\n");
397 + newvalue = S3C2410_EXTINT_RISEEDGE;
401 + newvalue = S3C2410_EXTINT_FALLEDGE;
404 + case IRQT_BOTHEDGE:
405 + newvalue = S3C2410_EXTINT_BOTHEDGE;
409 + newvalue = S3C2410_EXTINT_LOWLEV;
413 + newvalue = S3C2410_EXTINT_HILEV;
417 + printk(KERN_ERR "No such irq type %d", type);
421 + value = __raw_readl(S3C2400_EXTINT0);
422 + value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
423 + __raw_writel(value, S3C2400_EXTINT0);
428 +static struct irqchip s3c_irq_eint = {
429 + .ack = s3c_irq_ack,
430 + .mask = s3c_irq_mask,
431 + .unmask = s3c_irq_unmask,
432 + .set_wake = s3c_irq_wake,
433 + .set_type = s3c_irqext_type,
439 + * Initialise S3C2400 IRQ system
442 +void __init s3c24xx_init_irq(void)
444 + unsigned long pend;
445 + unsigned long last;
446 + int irqno, uart_irq[3];
449 + irqdbf("s3c24xx_init_irq: clearing interrupt status flags\n");
451 + /* first, clear all interrupts pending... */
454 + for (i = 0; i < 4; i++) {
455 + pend = __raw_readl(S3C2410_INTPND);
457 + if (pend == 0 || pend == last)
460 + __raw_writel(pend, S3C2410_SRCPND);
461 + __raw_writel(pend, S3C2410_INTPND);
462 + printk("irq: clearing pending status %08x\n", (int)pend);
466 + /* register the main interrupts */
468 + irqdbf("s3c24xx_init_irq: registering s3c2400 interrupt handlers\n");
470 + for (irqno = IRQ_TICK; irqno <= IRQ_ADCPARENT; irqno++) {
471 + /* set all the s3c2400 internal irqs */
474 + /* deal with the special IRQs (cascaded) */
481 + case IRQ_ADCPARENT:
482 + set_irq_chip(irqno, &s3c_irq_level_chip);
483 + set_irq_handler(irqno, do_level_IRQ);
486 + case IRQ_RESERVED6:
487 + case IRQ_RESERVED16:
492 + //irqdbf("registering irq %d (s3c irq)\n", irqno);
493 + set_irq_chip(irqno, &s3c_irq_chip);
494 + set_irq_handler(irqno, do_edge_IRQ);
495 + set_irq_flags(irqno, IRQF_VALID);
499 + /* external interrupts */
501 + for (irqno = IRQ_EINT0; irqno <= IRQ_EINT7; irqno++) {
502 + irqdbf("registering irq %d (ext int)\n", irqno);
503 + set_irq_chip(irqno, &s3c_irq_eint);
504 + set_irq_handler(irqno, do_edge_IRQ);
505 + set_irq_flags(irqno, IRQF_VALID);
508 + /* register the uart interrupts */
510 + uart_irq[0] = IRQ_URXD0;
511 + uart_irq[1] = IRQ_UTXD0;
512 + uart_irq[2] = IRQ_UERR01;
513 + for (i = 0; i < 3; i++) {
514 + irqdbf("registering irq %d (s3c uart0 irq)\n", uart_irq[i]);
515 + set_irq_chip(uart_irq[i], &s3c_irq_chip);
516 + set_irq_handler(uart_irq[i], do_level_IRQ);
517 + set_irq_flags(uart_irq[i], IRQF_VALID);
520 + uart_irq[0] = IRQ_URXD1;
521 + uart_irq[1] = IRQ_UTXD1;
522 + for (i = 0; i < 2; i++) {
523 + irqdbf("registering irq %d (s3c uart1 irq)\n", uart_irq[i]);
524 + set_irq_chip(uart_irq[i], &s3c_irq_chip);
525 + set_irq_handler(uart_irq[i], do_level_IRQ);
526 + set_irq_flags(uart_irq[i], IRQF_VALID);
529 + irqdbf("s3c2400: registered interrupt handlers\n");
531 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400.c
532 --- linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400.c 1970-01-01 01:00:00.000000000 +0100
533 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400.c 2010-02-18 01:13:59.467897060 +0100
535 +/* linux/arch/arm/mach-s3c2410/s3c2400.c
537 + * Copyright (c) 2003-2006 Simtec Electronics
538 + * Ben Dooks <ben@simtec.co.uk>
540 + * This program is free software; you can redistribute it and/or modify
541 + * it under the terms of the GNU General Public License version 2 as
542 + * published by the Free Software Foundation.
545 + * 15-Jan-2006 LCVR First version, based on s3c2410.c
548 +#include <linux/kernel.h>
549 +#include <linux/types.h>
550 +#include <linux/interrupt.h>
551 +#include <linux/list.h>
552 +#include <linux/timer.h>
553 +#include <linux/init.h>
554 +#include <linux/platform_device.h>
556 +#include <asm/mach/arch.h>
557 +#include <asm/mach/map.h>
558 +#include <asm/mach/irq.h>
560 +#include <asm/hardware.h>
562 +#include <asm/irq.h>
564 +#include <asm/arch/regs-clock.h>
565 +#include <asm/arch/regs-serial.h>
567 +#include "s3c2400.h"
571 +/* Initial IO mappings */
573 +static struct map_desc s3c2400_iodesc[] __initdata = {
574 + IODESC_ENT(USBHOST),
575 + IODESC_ENT(USBDEV),
576 + IODESC_ENT(CLKPWR),
580 + IODESC_ENT(WATCHDOG)
583 +static struct resource s3c_uart0_resource[] = {
585 + .start = S3C2410_PA_UART0,
586 + .end = S3C2410_PA_UART0 + 0x3fff,
587 + .flags = IORESOURCE_MEM,
590 + .start = IRQ_S3CUART_RX0,
591 + .end = IRQ_S3CUART_ERR0,
592 + .flags = IORESOURCE_IRQ,
597 +static struct resource s3c_uart1_resource[] = {
599 + .start = S3C2410_PA_UART1,
600 + .end = S3C2410_PA_UART1 + 0x3fff,
601 + .flags = IORESOURCE_MEM,
604 + .start = IRQ_S3CUART_RX1,
605 + .end = IRQ_S3CUART_ERR1,
606 + .flags = IORESOURCE_IRQ,
610 +/* our uart devices */
612 +static struct platform_device s3c_uart0 = {
613 + .name = "s3c2400-uart",
615 + .num_resources = ARRAY_SIZE(s3c_uart0_resource),
616 + .resource = s3c_uart0_resource,
620 +static struct platform_device s3c_uart1 = {
621 + .name = "s3c2400-uart",
623 + .num_resources = ARRAY_SIZE(s3c_uart1_resource),
624 + .resource = s3c_uart1_resource,
627 +static struct platform_device *uart_devices[] __initdata = {
632 +static int s3c2400_uart_count = 0;
634 +/* uart registration process */
636 +void __init s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no)
638 + struct platform_device *platdev;
641 + for (uart = 0; uart < no; uart++, cfg++) {
642 + platdev = uart_devices[cfg->hwport];
644 + s3c24xx_uart_devs[uart] = platdev;
645 + platdev->dev.platform_data = cfg;
648 + s3c2400_uart_count = uart;
653 + * register the standard cpu IO areas, and any passed in from the
654 + * machine specific initialisation.
657 +void __init s3c2400_map_io(struct map_desc *mach_desc, int mach_size)
659 + /* register our io-tables */
661 + iotable_init(s3c2400_iodesc, ARRAY_SIZE(s3c2400_iodesc));
662 + iotable_init(mach_desc, mach_size);
665 +void __init s3c2400_init_clocks(int xtal)
668 + unsigned long fclk;
669 + unsigned long hclk;
670 + unsigned long pclk;
672 + /* now we've got our machine bits initialised, work out what
673 + * clocks we've got */
675 + fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
677 + tmp = __raw_readl(S3C2410_CLKDIVN);
679 + /* work out clock scalings */
681 + hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
682 + pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
684 + /* print brieft summary of clocks, etc */
686 + printk("S3C2400: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
687 + print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
689 + /* initialise the clocks here, to allow other things like the
690 + * console to use them
693 + s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
696 +int __init s3c2400_init(void)
698 + printk("S3C2400: Initialising architecture\n");
700 + return platform_add_devices(s3c24xx_uart_devs, s3c2400_uart_count);
702 diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/entry-macro.S linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/entry-macro.S
703 --- linux-2.6.16.60/include/asm-arm/arch-s3c2410/entry-macro.S 2008-01-27 17:58:41.000000000 +0100
704 +++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/entry-macro.S 2010-02-18 01:19:18.503894425 +0100
708 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
709 + * 19-Jan-2006 LCVR Added support to S3C2400
711 #include <asm/hardware.h>
712 #include <asm/arch/irqs.h>
714 mov \tmp, #S3C24XX_VA_IRQ
715 ldr \irqnr, [ \tmp, #0x14 ] @ get irq no
717 +#ifndef CONFIG_CPU_S3C2400
720 beq 1002f @ external irq reg
723 @ debug check to see if interrupt reported is the same
727 mov \irqnr, #IRQ_EINT4 @ start extint nos
728 mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits
730 +#ifndef CONFIG_CPU_S3C2400
731 movs \irqstat, \irqstat, lsr#1
733 add \irqnr, \irqnr, #1
736 @ found no interrupt, set Z flag and leave
740 1004: @ ensure Z flag clear in case our MOVS shifted out the last bit
742 diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/gp32-map.h linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/gp32-map.h
743 --- linux-2.6.16.60/include/asm-arm/arch-s3c2410/gp32-map.h 1970-01-01 01:00:00.000000000 +0100
744 +++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/gp32-map.h 2010-02-18 01:19:10.259895346 +0100
746 +/* linux/include/asm-arm/arch-s3c2410/gp32-map.h
748 + * Copyright (c) 2005 Lucas Correia Villa Real <lucasvr@gobolinux.org>
750 + * Machine GP32 - Memory map definitions
752 + * This program is free software; you can redistribute it and/or modify
753 + * it under the terms of the GNU General Public License version 2 as
754 + * published by the Free Software Foundation.
758 +/* needs arch/map.h including with this */
760 +#ifndef __ASM_ARCH_GP32MAP_H
761 +#define __ASM_ARCH_GP32MAP_H
763 +#define GP32_IOADDR(x) (0xC0000000 + (x))
765 +/* maps the BOOT ROM, which is connected to nGCS0 */
766 +#define GP32_VA_BOOT_ROM GP32_IOADDR(0x00000000)
768 +#endif /* __ASM_ARCH_GP32MAP_H */
769 diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/irqs.h linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/irqs.h
770 --- linux-2.6.16.60/include/asm-arm/arch-s3c2410/irqs.h 2008-01-27 17:58:41.000000000 +0100
771 +++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/irqs.h 2010-02-18 01:19:18.503894425 +0100
773 * 12-Mar-2004 BJD Fixed bug in header protection
774 * 10-Feb-2005 BJD Added camera IRQ from guillaume.gourat@nexvision.tv
775 * 28-Feb-2005 BJD Updated s3c2440 IRQs
776 + * 19-Jan-2006 LCVR Added S3C2400 definitions
781 #define IRQ_TIMER3 S3C2410_IRQ(13)
782 #define IRQ_TIMER4 S3C2410_IRQ(14)
783 #define IRQ_UART2 S3C2410_IRQ(15)
784 +#define IRQ_UERR01 S3C2410_IRQ(15) /* for s3c2400 */
785 #define IRQ_LCD S3C2410_IRQ(16) /* 32 */
786 +#define IRQ_RESERVED16 S3C2410_IRQ(16) /* for s3c2400 */
787 #define IRQ_DMA0 S3C2410_IRQ(17)
788 #define IRQ_DMA1 S3C2410_IRQ(18)
789 #define IRQ_DMA2 S3C2410_IRQ(19)
790 #define IRQ_DMA3 S3C2410_IRQ(20)
791 #define IRQ_SDI S3C2410_IRQ(21)
792 -#define IRQ_SPI0 S3C2410_IRQ(22)
793 +#define IRQ_MMC S3C2410_IRQ(21) /* for s3c2400 */
794 +#define IRQ_SPI0 S3C2410_IRQ(22) /* s3c2400 has only 1 SPI */
795 #define IRQ_UART1 S3C2410_IRQ(23)
796 +#define IRQ_URXD0 S3C2410_IRQ(23) /* for s3c2400 */
797 +#define IRQ_URXD1 S3C2410_IRQ(24) /* for s3c2400 */
798 #define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
799 #define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
800 #define IRQ_USBD S3C2410_IRQ(25)
801 #define IRQ_USBH S3C2410_IRQ(26)
802 #define IRQ_IIC S3C2410_IRQ(27)
803 #define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
804 +#define IRQ_UTXD0 S3C2410_IRQ(28) /* for s3c2400 */
805 +#define IRQ_UTXD1 S3C2410_IRQ(29) /* for s3c2400 */
806 #define IRQ_SPI1 S3C2410_IRQ(29)
807 #define IRQ_RTC S3C2410_IRQ(30)
808 #define IRQ_ADCPARENT S3C2410_IRQ(31)
810 +#ifdef CONFIG_CPU_S3C2400
812 +/* interrupts generated from the external interrupts sources */
813 +#define IRQ_EINT4 S3C2410_IRQ(4)
814 +#define IRQ_EINT5 S3C2410_IRQ(5)
815 +#define IRQ_EINT6 S3C2410_IRQ(6)
816 +#define IRQ_EINT7 S3C2410_IRQ(7)
817 +#define IRQ_ADC S3C2410_IRQ(31)
819 +/* aliases to keep compatibility with S3C2410 code */
820 +#define IRQ_S3CUART_RX0 IRQ_URXD0
821 +#define IRQ_S3CUART_TX0 IRQ_UTXD0
822 +#define IRQ_S3CUART_ERR0 IRQ_UERR01
824 +#define IRQ_S3CUART_RX1 IRQ_URXD1
825 +#define IRQ_S3CUART_TX1 IRQ_UTXD1
826 +#define IRQ_S3CUART_ERR1 IRQ_UERR01
828 +#define NR_IRQS (IRQ_ADC+1)
832 /* interrupts generated from the external interrupts sources */
833 #define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
834 #define IRQ_EINT5 S3C2410_IRQ(33)
837 #define NR_IRQS (IRQ_S3C2440_AC97+1)
839 +#endif /* CONFIG_CPU_S3C2400 */
841 #endif /* __ASM_ARCH_IRQ_H */