1 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Kconfig linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Kconfig
2 --- linux-2.6.16.60/arch/arm/mach-s3c2410/Kconfig 2008-01-27 17:58:41.000000000 +0100
3 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Kconfig 2010-02-18 01:19:10.259895346 +0100
4 @@ -86,8 +86,24 @@ config MACH_NEXCODER_2440
6 Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
10 + depends on EXPERIMENTAL
13 + Say Y here if you are using the GamePark GP32 handheld.
15 + See <http://sourceforge.net/projects/gp32linux> for more
16 + information on this project.
22 + depends on ARCH_S3C2410
24 + Support for the S3C2400 from S3C24XX line of Samsung Mobile CPUs.
28 depends on ARCH_S3C2410
29 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile
30 --- linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile 2008-01-27 17:58:41.000000000 +0100
31 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile 2010-02-18 01:19:18.503894425 +0100
36 -obj-y := cpu.o irq.o time.o gpio.o clock.o devs.o
37 +obj-y := cpu.o time.o gpio.o clock.o devs.o
42 # S3C2400 support files
43 +obj-$(CONFIG_CPU_S3C2400) += s3c2400.o
44 +obj-$(CONFIG_CPU_S3C2400) += s3c2400-irq.o
45 obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o
47 # S3C2410 support files
49 -obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
50 +obj-$(CONFIG_CPU_S3C2410) += s3c2410.o irq.o
51 obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o
52 obj-$(CONFIG_S3C2410_DMA) += dma.o
54 @@ -27,7 +29,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.
57 obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o
58 -obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o
59 +obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o irq.o
60 obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o
61 obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o
63 @@ -40,6 +42,7 @@ obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq
64 obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
65 obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o
66 obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
67 +obj-$(CONFIG_MACH_GP32) += mach-gp32.o
68 obj-$(CONFIG_MACH_N30) += mach-n30.o
69 obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
70 obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
71 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile.boot linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile.boot
72 --- linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile.boot 2008-01-27 17:58:41.000000000 +0100
73 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile.boot 2010-02-18 01:13:59.467897060 +0100
75 +ifeq ($(CONFIG_CPU_S3C2400),y)
76 + zreladdr-y := 0x0c008000
77 +params_phys-y := 0x0c000100
79 zreladdr-y := 0x30008000
80 params_phys-y := 0x30000100
83 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/devs.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/devs.c
84 --- linux-2.6.16.60/arch/arm/mach-s3c2410/devs.c 2008-01-27 17:58:41.000000000 +0100
85 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/devs.c 2010-02-18 02:20:22.071894261 +0100
86 @@ -273,11 +273,19 @@ static struct resource s3c_adc_resource[
87 .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
88 .flags = IORESOURCE_MEM,
90 +#ifdef CONFIG_CPU_S3C2400
94 + .flags = IORESOURCE_IRQ,
101 .flags = IORESOURCE_IRQ,
107 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/irq.h linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/irq.h
108 --- linux-2.6.16.60/arch/arm/mach-s3c2410/irq.h 2008-01-27 17:58:41.000000000 +0100
109 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/irq.h 2010-02-18 02:38:04.967896102 +0100
112 #define EXTINT_OFF (IRQ_EINT4 - 4)
114 -extern struct irqchip s3c_irq_level_chip;
117 s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
119 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/mach-gp32.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/mach-gp32.c
120 --- linux-2.6.16.60/arch/arm/mach-s3c2410/mach-gp32.c 1970-01-01 01:00:00.000000000 +0100
121 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/mach-gp32.c 2010-02-18 01:19:10.259895346 +0100
123 +/* linux/arch/arm/mach-s3c2410/mach-gp32.c
125 + * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
127 + * http://sourceforge.net/projects/gp32linux
129 + * This program is free software; you can redistribute it and/or modify
130 + * it under the terms of the GNU General Public License version 2 as
131 + * published by the Free Software Foundation.
134 + * 15-Jan-2006 LCVR Created initial version
137 +#include <linux/kernel.h>
138 +#include <linux/types.h>
139 +#include <linux/interrupt.h>
140 +#include <linux/list.h>
141 +#include <linux/timer.h>
142 +#include <linux/init.h>
143 +#include <linux/platform_device.h>
144 +#include <linux/serial_core.h>
146 +#include <asm/arch/gp32-map.h>
147 +#include <asm/mach/arch.h>
148 +#include <asm/mach/map.h>
149 +#include <asm/mach/irq.h>
151 +#include <asm/hardware.h>
153 +#include <asm/irq.h>
154 +#include <asm/mach-types.h>
156 +#include <asm/arch/regs-serial.h>
157 +#include <asm/arch/regs-gpio.h>
158 +#include <asm/arch/regs-mem.h>
164 +static struct map_desc gp32_iodesc[] __initdata = {
165 + /* dump ISA space somewhere unused */
167 + { (u32)S3C24XX_VA_ISA_WORD, S3C2400_CS3, SZ_16M, MT_DEVICE },
168 + { (u32)S3C24XX_VA_ISA_BYTE, S3C2400_CS3, SZ_16M, MT_DEVICE },
170 + /* the BOOT-ROM is assigned to the nGCS0 */
172 + { GP32_VA_BOOT_ROM, S3C2400_CS0, SZ_16M, MT_DEVICE },
175 +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
176 +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
177 +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
179 +static struct s3c2410_uartcfg gp32_uartcfgs[] = {
198 +static struct platform_device *gp32_devices[] __initdata = {
200 + &s3c_device_usbgadget,
208 +static struct s3c24xx_board gp32_board __initdata = {
209 + .devices = gp32_devices,
210 + .devices_count = ARRAY_SIZE(gp32_devices),
214 +void __init gp32_map_io(void)
216 + s3c24xx_init_io(gp32_iodesc, ARRAY_SIZE(gp32_iodesc));
217 + s3c24xx_init_clocks(0);
218 + s3c24xx_init_uarts(gp32_uartcfgs, ARRAY_SIZE(gp32_uartcfgs));
219 + s3c24xx_set_board(&gp32_board);
222 +MACHINE_START(GP32, "GamePark GP32")
223 + /* Maintainer: Lucas Correia Villa Real <lucasvr@gobolinux.org> */
224 + .phys_io = S3C2400_PA_UART,
225 + .io_pg_offst = ((u32)S3C24XX_VA_UART >> 18) & 0xfffc,
226 + .boot_params = S3C2400_SDRAM_PA + 0x100,
227 + .map_io = gp32_map_io,
228 + .init_irq = s3c24xx_init_irq,
229 + .timer = &s3c24xx_timer,
231 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400-irq.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400-irq.c
232 --- linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400-irq.c 1970-01-01 01:00:00.000000000 +0100
233 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400-irq.c 2010-02-18 02:27:58.571895480 +0100
235 +/* linux/arch/arm/mach-s3c2410/s3c2400-irq.c
237 + * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
239 + * Based on mach-s3c2410/irq.c,
240 + * Copyright (c) 2003,2004 Simtec Electronics
241 + * Ben Dooks <ben@simtec.co.uk>
243 + * This program is free software; you can redistribute it and/or modify
244 + * it under the terms of the GNU General Public License as published by
245 + * the Free Software Foundation; either version 2 of the License, or
246 + * (at your option) any later version.
248 + * This program is distributed in the hope that it will be useful,
249 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
250 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
251 + * GNU General Public License for more details.
253 + * You should have received a copy of the GNU General Public License
254 + * along with this program; if not, write to the Free Software
255 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
259 + * 19-Jan-2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
260 + * First version, based on S3C2410 code
263 +#include <linux/init.h>
264 +#include <linux/module.h>
265 +#include <linux/interrupt.h>
266 +#include <linux/ioport.h>
267 +#include <linux/ptrace.h>
268 +#include <linux/sysdev.h>
270 +#include <asm/hardware.h>
271 +#include <asm/irq.h>
274 +#include <asm/mach/irq.h>
276 +#include <asm/arch/regs-irq.h>
277 +#include <asm/arch/regs-gpio.h>
284 +/* wakeup irq control */
288 +/* state for IRQs over sleep */
290 +/* default is to allow for EINT0..EINT7, and IRQ_RTC as wakeup sources
292 + * set bit to 1 in allow bitfield to enable the wakeup settings on it
295 +unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xffL;
296 +unsigned long s3c_irqwake_intmask = 0xffffffffL;
299 +s3c_irq_wake(unsigned int irqno, unsigned int state)
301 + unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
303 + if (!(s3c_irqwake_intallow & irqbit))
306 + printk(KERN_INFO "wake %s for irq %d\n",
307 + state ? "enabled" : "disabled", irqno);
310 + s3c_irqwake_intmask |= irqbit;
312 + s3c_irqwake_intmask &= ~irqbit;
318 +#define s3c_irq_wake NULL
323 +s3c_irq_mask(unsigned int irqno)
325 + unsigned long mask;
327 + irqno -= IRQ_EINT0;
329 + mask = __raw_readl(S3C2410_INTMSK);
330 + mask |= 1UL << irqno;
331 + __raw_writel(mask, S3C2410_INTMSK);
335 +s3c_irq_ack(unsigned int irqno)
337 + unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
339 + __raw_writel(bitval, S3C2410_SRCPND);
340 + __raw_writel(bitval, S3C2410_INTPND);
344 +s3c_irq_maskack(unsigned int irqno)
346 + unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
347 + unsigned long mask;
349 + mask = __raw_readl(S3C2410_INTMSK);
350 + __raw_writel(mask|bitval, S3C2410_INTMSK);
352 + __raw_writel(bitval, S3C2410_SRCPND);
353 + __raw_writel(bitval, S3C2410_INTPND);
358 +s3c_irq_unmask(unsigned int irqno)
360 + unsigned long mask;
362 + irqno -= IRQ_EINT0;
364 + mask = __raw_readl(S3C2410_INTMSK);
365 + mask &= ~(1UL << irqno);
366 + __raw_writel(mask, S3C2410_INTMSK);
369 +static struct irqchip s3c_irq_level_chip = {
370 + .ack = s3c_irq_maskack,
371 + .mask = s3c_irq_mask,
372 + .unmask = s3c_irq_unmask,
373 + .set_wake = s3c_irq_wake
376 +static struct irqchip s3c_irq_chip = {
377 + .ack = s3c_irq_ack,
378 + .mask = s3c_irq_mask,
379 + .unmask = s3c_irq_unmask,
380 + .set_wake = s3c_irq_wake
385 +s3c_irqext_type(unsigned int irq, unsigned int type)
387 + unsigned long gpcon_offset, extint_offset;
388 + unsigned long newvalue = 0, value;
390 + if ((irq < IRQ_EINT0) || (irq > IRQ_EINT7))
393 + gpcon_offset = (irq - IRQ_EINT0) * 2;
394 + extint_offset = (irq - IRQ_EINT0) * 4;
396 + /* Set the GPIO to external interrupt mode */
397 + value = __raw_readl(S3C2400_GPECON);
398 + value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
399 + __raw_writel(value, S3C2400_GPECON);
401 + /* Set the external interrupt to pointed trigger type */
405 + printk(KERN_WARNING "No edge setting!\n");
409 + newvalue = S3C2410_EXTINT_RISEEDGE;
413 + newvalue = S3C2410_EXTINT_FALLEDGE;
416 + case IRQT_BOTHEDGE:
417 + newvalue = S3C2410_EXTINT_BOTHEDGE;
421 + newvalue = S3C2410_EXTINT_LOWLEV;
425 + newvalue = S3C2410_EXTINT_HILEV;
429 + printk(KERN_ERR "No such irq type %d", type);
433 + value = __raw_readl(S3C2400_EXTINT0);
434 + value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
435 + __raw_writel(value, S3C2400_EXTINT0);
440 +static struct irqchip s3c_irq_eint = {
441 + .ack = s3c_irq_ack,
442 + .mask = s3c_irq_mask,
443 + .unmask = s3c_irq_unmask,
444 + .set_wake = s3c_irq_wake,
445 + .set_type = s3c_irqext_type,
451 + * Initialise S3C2400 IRQ system
454 +void __init s3c24xx_init_irq(void)
456 + unsigned long pend;
457 + unsigned long last;
458 + int irqno, uart_irq[3];
461 + irqdbf("s3c24xx_init_irq: clearing interrupt status flags\n");
463 + /* first, clear all interrupts pending... */
466 + for (i = 0; i < 4; i++) {
467 + pend = __raw_readl(S3C2410_INTPND);
469 + if (pend == 0 || pend == last)
472 + __raw_writel(pend, S3C2410_SRCPND);
473 + __raw_writel(pend, S3C2410_INTPND);
474 + printk("irq: clearing pending status %08x\n", (int)pend);
478 + /* register the main interrupts */
480 + irqdbf("s3c24xx_init_irq: registering s3c2400 interrupt handlers\n");
482 + for (irqno = IRQ_TICK; irqno <= IRQ_ADCPARENT; irqno++) {
483 + /* set all the s3c2400 internal irqs */
486 + /* deal with the special IRQs (cascaded) */
493 + case IRQ_ADCPARENT:
494 + set_irq_chip(irqno, &s3c_irq_level_chip);
495 + set_irq_handler(irqno, do_level_IRQ);
498 + case IRQ_RESERVED6:
499 + case IRQ_RESERVED16:
504 + //irqdbf("registering irq %d (s3c irq)\n", irqno);
505 + set_irq_chip(irqno, &s3c_irq_chip);
506 + set_irq_handler(irqno, do_edge_IRQ);
507 + set_irq_flags(irqno, IRQF_VALID);
511 + /* external interrupts */
513 + for (irqno = IRQ_EINT0; irqno <= IRQ_EINT7; irqno++) {
514 + irqdbf("registering irq %d (ext int)\n", irqno);
515 + set_irq_chip(irqno, &s3c_irq_eint);
516 + set_irq_handler(irqno, do_edge_IRQ);
517 + set_irq_flags(irqno, IRQF_VALID);
520 + /* register the uart interrupts */
522 + uart_irq[0] = IRQ_URXD0;
523 + uart_irq[1] = IRQ_UTXD0;
524 + uart_irq[2] = IRQ_UERR01;
525 + for (i = 0; i < 3; i++) {
526 + irqdbf("registering irq %d (s3c uart0 irq)\n", uart_irq[i]);
527 + set_irq_chip(uart_irq[i], &s3c_irq_chip);
528 + set_irq_handler(uart_irq[i], do_level_IRQ);
529 + set_irq_flags(uart_irq[i], IRQF_VALID);
532 + uart_irq[0] = IRQ_URXD1;
533 + uart_irq[1] = IRQ_UTXD1;
534 + for (i = 0; i < 2; i++) {
535 + irqdbf("registering irq %d (s3c uart1 irq)\n", uart_irq[i]);
536 + set_irq_chip(uart_irq[i], &s3c_irq_chip);
537 + set_irq_handler(uart_irq[i], do_level_IRQ);
538 + set_irq_flags(uart_irq[i], IRQF_VALID);
541 + irqdbf("s3c2400: registered interrupt handlers\n");
543 diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400.c
544 --- linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400.c 1970-01-01 01:00:00.000000000 +0100
545 +++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400.c 2010-02-18 01:13:59.467897060 +0100
547 +/* linux/arch/arm/mach-s3c2410/s3c2400.c
549 + * Copyright (c) 2003-2006 Simtec Electronics
550 + * Ben Dooks <ben@simtec.co.uk>
552 + * This program is free software; you can redistribute it and/or modify
553 + * it under the terms of the GNU General Public License version 2 as
554 + * published by the Free Software Foundation.
557 + * 15-Jan-2006 LCVR First version, based on s3c2410.c
560 +#include <linux/kernel.h>
561 +#include <linux/types.h>
562 +#include <linux/interrupt.h>
563 +#include <linux/list.h>
564 +#include <linux/timer.h>
565 +#include <linux/init.h>
566 +#include <linux/platform_device.h>
568 +#include <asm/mach/arch.h>
569 +#include <asm/mach/map.h>
570 +#include <asm/mach/irq.h>
572 +#include <asm/hardware.h>
574 +#include <asm/irq.h>
576 +#include <asm/arch/regs-clock.h>
577 +#include <asm/arch/regs-serial.h>
579 +#include "s3c2400.h"
583 +/* Initial IO mappings */
585 +static struct map_desc s3c2400_iodesc[] __initdata = {
586 + IODESC_ENT(USBHOST),
587 + IODESC_ENT(USBDEV),
588 + IODESC_ENT(CLKPWR),
592 + IODESC_ENT(WATCHDOG)
595 +static struct resource s3c_uart0_resource[] = {
597 + .start = S3C2410_PA_UART0,
598 + .end = S3C2410_PA_UART0 + 0x3fff,
599 + .flags = IORESOURCE_MEM,
602 + .start = IRQ_S3CUART_RX0,
603 + .end = IRQ_S3CUART_ERR0,
604 + .flags = IORESOURCE_IRQ,
609 +static struct resource s3c_uart1_resource[] = {
611 + .start = S3C2410_PA_UART1,
612 + .end = S3C2410_PA_UART1 + 0x3fff,
613 + .flags = IORESOURCE_MEM,
616 + .start = IRQ_S3CUART_RX1,
617 + .end = IRQ_S3CUART_ERR1,
618 + .flags = IORESOURCE_IRQ,
622 +/* our uart devices */
624 +static struct platform_device s3c_uart0 = {
625 + .name = "s3c2400-uart",
627 + .num_resources = ARRAY_SIZE(s3c_uart0_resource),
628 + .resource = s3c_uart0_resource,
632 +static struct platform_device s3c_uart1 = {
633 + .name = "s3c2400-uart",
635 + .num_resources = ARRAY_SIZE(s3c_uart1_resource),
636 + .resource = s3c_uart1_resource,
639 +static struct platform_device *uart_devices[] __initdata = {
644 +static int s3c2400_uart_count = 0;
646 +/* uart registration process */
648 +void __init s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no)
650 + struct platform_device *platdev;
653 + for (uart = 0; uart < no; uart++, cfg++) {
654 + platdev = uart_devices[cfg->hwport];
656 + s3c24xx_uart_devs[uart] = platdev;
657 + platdev->dev.platform_data = cfg;
660 + s3c2400_uart_count = uart;
665 + * register the standard cpu IO areas, and any passed in from the
666 + * machine specific initialisation.
669 +void __init s3c2400_map_io(struct map_desc *mach_desc, int mach_size)
671 + /* register our io-tables */
673 + iotable_init(s3c2400_iodesc, ARRAY_SIZE(s3c2400_iodesc));
674 + iotable_init(mach_desc, mach_size);
677 +void __init s3c2400_init_clocks(int xtal)
680 + unsigned long fclk;
681 + unsigned long hclk;
682 + unsigned long pclk;
684 + /* now we've got our machine bits initialised, work out what
685 + * clocks we've got */
687 + fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
689 + tmp = __raw_readl(S3C2410_CLKDIVN);
691 + /* work out clock scalings */
693 + hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
694 + pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
696 + /* print brieft summary of clocks, etc */
698 + printk("S3C2400: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
699 + print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
701 + /* initialise the clocks here, to allow other things like the
702 + * console to use them
705 + s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
708 +int __init s3c2400_init(void)
710 + printk("S3C2400: Initialising architecture\n");
712 + return platform_add_devices(s3c24xx_uart_devs, s3c2400_uart_count);
714 diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/entry-macro.S linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/entry-macro.S
715 --- linux-2.6.16.60/include/asm-arm/arch-s3c2410/entry-macro.S 2008-01-27 17:58:41.000000000 +0100
716 +++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/entry-macro.S 2010-02-18 01:19:18.503894425 +0100
720 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
721 + * 19-Jan-2006 LCVR Added support to S3C2400
723 #include <asm/hardware.h>
724 #include <asm/arch/irqs.h>
726 mov \tmp, #S3C24XX_VA_IRQ
727 ldr \irqnr, [ \tmp, #0x14 ] @ get irq no
729 +#ifndef CONFIG_CPU_S3C2400
732 beq 1002f @ external irq reg
735 @ debug check to see if interrupt reported is the same
739 mov \irqnr, #IRQ_EINT4 @ start extint nos
740 mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits
742 +#ifndef CONFIG_CPU_S3C2400
743 movs \irqstat, \irqstat, lsr#1
745 add \irqnr, \irqnr, #1
748 @ found no interrupt, set Z flag and leave
752 1004: @ ensure Z flag clear in case our MOVS shifted out the last bit
754 diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/gp32-map.h linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/gp32-map.h
755 --- linux-2.6.16.60/include/asm-arm/arch-s3c2410/gp32-map.h 1970-01-01 01:00:00.000000000 +0100
756 +++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/gp32-map.h 2010-02-18 01:19:10.259895346 +0100
758 +/* linux/include/asm-arm/arch-s3c2410/gp32-map.h
760 + * Copyright (c) 2005 Lucas Correia Villa Real <lucasvr@gobolinux.org>
762 + * Machine GP32 - Memory map definitions
764 + * This program is free software; you can redistribute it and/or modify
765 + * it under the terms of the GNU General Public License version 2 as
766 + * published by the Free Software Foundation.
770 +/* needs arch/map.h including with this */
772 +#ifndef __ASM_ARCH_GP32MAP_H
773 +#define __ASM_ARCH_GP32MAP_H
775 +#define GP32_IOADDR(x) (0xC0000000 + (x))
777 +/* maps the BOOT ROM, which is connected to nGCS0 */
778 +#define GP32_VA_BOOT_ROM GP32_IOADDR(0x00000000)
780 +#endif /* __ASM_ARCH_GP32MAP_H */
781 diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/irqs.h linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/irqs.h
782 --- linux-2.6.16.60/include/asm-arm/arch-s3c2410/irqs.h 2008-01-27 17:58:41.000000000 +0100
783 +++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/irqs.h 2010-02-18 01:19:18.503894425 +0100
785 * 12-Mar-2004 BJD Fixed bug in header protection
786 * 10-Feb-2005 BJD Added camera IRQ from guillaume.gourat@nexvision.tv
787 * 28-Feb-2005 BJD Updated s3c2440 IRQs
788 + * 19-Jan-2006 LCVR Added S3C2400 definitions
793 #define IRQ_TIMER3 S3C2410_IRQ(13)
794 #define IRQ_TIMER4 S3C2410_IRQ(14)
795 #define IRQ_UART2 S3C2410_IRQ(15)
796 +#define IRQ_UERR01 S3C2410_IRQ(15) /* for s3c2400 */
797 #define IRQ_LCD S3C2410_IRQ(16) /* 32 */
798 +#define IRQ_RESERVED16 S3C2410_IRQ(16) /* for s3c2400 */
799 #define IRQ_DMA0 S3C2410_IRQ(17)
800 #define IRQ_DMA1 S3C2410_IRQ(18)
801 #define IRQ_DMA2 S3C2410_IRQ(19)
802 #define IRQ_DMA3 S3C2410_IRQ(20)
803 #define IRQ_SDI S3C2410_IRQ(21)
804 -#define IRQ_SPI0 S3C2410_IRQ(22)
805 +#define IRQ_MMC S3C2410_IRQ(21) /* for s3c2400 */
806 +#define IRQ_SPI0 S3C2410_IRQ(22) /* s3c2400 has only 1 SPI */
807 #define IRQ_UART1 S3C2410_IRQ(23)
808 +#define IRQ_URXD0 S3C2410_IRQ(23) /* for s3c2400 */
809 +#define IRQ_URXD1 S3C2410_IRQ(24) /* for s3c2400 */
810 #define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
811 #define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
812 #define IRQ_USBD S3C2410_IRQ(25)
813 #define IRQ_USBH S3C2410_IRQ(26)
814 #define IRQ_IIC S3C2410_IRQ(27)
815 #define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
816 +#define IRQ_UTXD0 S3C2410_IRQ(28) /* for s3c2400 */
817 +#define IRQ_UTXD1 S3C2410_IRQ(29) /* for s3c2400 */
818 #define IRQ_SPI1 S3C2410_IRQ(29)
819 #define IRQ_RTC S3C2410_IRQ(30)
820 #define IRQ_ADCPARENT S3C2410_IRQ(31)
822 +#ifdef CONFIG_CPU_S3C2400
824 +/* interrupts generated from the external interrupts sources */
825 +#define IRQ_EINT4 S3C2410_IRQ(4)
826 +#define IRQ_EINT5 S3C2410_IRQ(5)
827 +#define IRQ_EINT6 S3C2410_IRQ(6)
828 +#define IRQ_EINT7 S3C2410_IRQ(7)
829 +#define IRQ_ADC S3C2410_IRQ(31)
831 +/* aliases to keep compatibility with S3C2410 code */
832 +#define IRQ_S3CUART_RX0 IRQ_URXD0
833 +#define IRQ_S3CUART_TX0 IRQ_UTXD0
834 +#define IRQ_S3CUART_ERR0 IRQ_UERR01
836 +#define IRQ_S3CUART_RX1 IRQ_URXD1
837 +#define IRQ_S3CUART_TX1 IRQ_UTXD1
838 +#define IRQ_S3CUART_ERR1 IRQ_UERR01
840 +#define NR_IRQS (IRQ_ADC+1)
844 /* interrupts generated from the external interrupts sources */
845 #define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
846 #define IRQ_EINT5 S3C2410_IRQ(33)
849 #define NR_IRQS (IRQ_S3C2440_AC97+1)
851 +#endif /* CONFIG_CPU_S3C2400 */
853 #endif /* __ASM_ARCH_IRQ_H */