From 164203ae18368ed27e66d2f9ab3cf94e2a698528 Mon Sep 17 00:00:00 2001 From: Jose V Beneyto Date: Thu, 18 Feb 2010 02:47:36 +0100 Subject: [PATCH] updated to 2.6.16.60 and added some patches (verified compilation) --- Makefile | 6 +- config-2.6.16 => config-2.6.16.60 | 42 +- work/linux-2.6.16.60-gp32.patch | 841 ++++++++++++++++++++++++++++++ 3 files changed, 873 insertions(+), 16 deletions(-) rename config-2.6.16 => config-2.6.16.60 (96%) create mode 100644 work/linux-2.6.16.60-gp32.patch diff --git a/Makefile b/Makefile index 918fd58..235bb51 100644 --- a/Makefile +++ b/Makefile @@ -8,7 +8,7 @@ TOPDIR = $(shell pwd) WORK = $(TOPDIR)/work CROSSTOOLS = $(TOPDIR)/../../toolchain/crosstools -KERNEL_VERSION = 2.6.16 +KERNEL_VERSION = 2.6.16.60 .PHONY: all clean image modules map config @@ -22,8 +22,10 @@ distclean: clean image-distclean modules-distclean map-distclean $(WORK)/linux-$(KERNEL_VERSION).tar.bz2: wget -P $(WORK) ftp://ftp.kernel.org/pub/linux/kernel/v2.6/linux-$(KERNEL_VERSION).tar.bz2 -$(WORK)/linux-$(KERNEL_VERSION): $(WORK)/linux-$(KERNEL_VERSION).tar.bz2 +$(WORK)/linux-$(KERNEL_VERSION): $(WORK)/linux-$(KERNEL_VERSION).tar.bz2 $(WORK)/linux-$(KERNEL_VERSION)-gp32.patch tar -C $(WORK) -xvjf $(WORK)/linux-$(KERNEL_VERSION).tar.bz2 + cd $(WORK)/linux-$(KERNEL_VERSION) && \ + patch -p1 -i $(WORK)/linux-$(KERNEL_VERSION)-gp32.patch cp -v $(TOPDIR)/config-$(KERNEL_VERSION) $(WORK)/linux-$(KERNEL_VERSION)/.config touch $(WORK)/linux-$(KERNEL_VERSION) diff --git a/config-2.6.16 b/config-2.6.16.60 similarity index 96% rename from config-2.6.16 rename to config-2.6.16.60 index ed90617..ffb938b 100644 --- a/config-2.6.16 +++ b/config-2.6.16.60 @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.16 -# Tue Feb 16 16:42:48 2010 +# Linux kernel version: 2.6.16.60 +# Thu Feb 18 02:12:33 2010 # CONFIG_ARM=y CONFIG_MMU=y @@ -13,7 +13,6 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 # @@ -118,17 +117,18 @@ CONFIG_ARCH_S3C2410=y # CONFIG_ARCH_H1940 is not set # CONFIG_MACH_N30 is not set # CONFIG_ARCH_SMDK2410 is not set -CONFIG_ARCH_S3C2440=y +# CONFIG_ARCH_S3C2440 is not set # CONFIG_MACH_VR1000 is not set # CONFIG_MACH_RX3715 is not set # CONFIG_MACH_OTOM is not set # CONFIG_MACH_NEXCODER_2440 is not set -CONFIG_CPU_S3C2440=y +CONFIG_MACH_GP32=y +CONFIG_CPU_S3C2400=y # # S3C2410 Boot # -# CONFIG_S3C2410_BOOT_WATCHDOG is not set +CONFIG_S3C2410_BOOT_WATCHDOG=y # CONFIG_S3C2410_BOOT_ERROR_RESET is not set # @@ -170,7 +170,7 @@ CONFIG_ARM_THUMB=y # # Kernel Features # -CONFIG_PREEMPT=y +# CONFIG_PREEMPT is not set # CONFIG_NO_IDLE_HZ is not set # CONFIG_AEABI is not set # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set @@ -661,9 +661,12 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83627HF is not set @@ -692,14 +695,15 @@ CONFIG_HWMON=y # Graphics support # CONFIG_FB=y -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_MACMODES is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set # CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_S3C2410 is not set +CONFIG_FB_S3C2410=y +CONFIG_FB_S3C2410_DEBUG=y # CONFIG_FB_VIRTUAL is not set # @@ -814,8 +818,17 @@ CONFIG_RAMFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set +CONFIG_JFFS_FS=y +CONFIG_JFFS_FS_VERBOSE=0 +# CONFIG_JFFS_PROC_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set @@ -900,7 +913,6 @@ CONFIG_LOG_BUF_SHIFT=14 CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_SCHEDSTATS is not set # CONFIG_DEBUG_SLAB is not set -CONFIG_DEBUG_PREEMPT=y # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set @@ -940,3 +952,5 @@ CONFIG_DEBUG_S3C2410_UART=0 # CONFIG_CRC16 is not set CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/work/linux-2.6.16.60-gp32.patch b/work/linux-2.6.16.60-gp32.patch new file mode 100644 index 0000000..97185ed --- /dev/null +++ b/work/linux-2.6.16.60-gp32.patch @@ -0,0 +1,841 @@ +diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Kconfig linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Kconfig +--- linux-2.6.16.60/arch/arm/mach-s3c2410/Kconfig 2008-01-27 17:58:41.000000000 +0100 ++++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Kconfig 2010-02-18 01:19:10.259895346 +0100 +@@ -86,8 +86,24 @@ config MACH_NEXCODER_2440 + help + Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board + ++config MACH_GP32 ++ bool "GamePark GP32" ++ depends on EXPERIMENTAL ++ select CPU_S3C2400 ++ help ++ Say Y here if you are using the GamePark GP32 handheld. ++ ++ See for more ++ information on this project. ++ + endmenu + ++config CPU_S3C2400 ++ bool ++ depends on ARCH_S3C2410 ++ help ++ Support for the S3C2400 from S3C24XX line of Samsung Mobile CPUs. ++ + config CPU_S3C2410 + bool + depends on ARCH_S3C2410 +diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile +--- linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile 2008-01-27 17:58:41.000000000 +0100 ++++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile 2010-02-18 01:19:18.503894425 +0100 +@@ -5,17 +5,19 @@ + + # Object file lists. + +-obj-y := cpu.o irq.o time.o gpio.o clock.o devs.o ++obj-y := cpu.o time.o gpio.o clock.o devs.o + obj-m := + obj-n := + obj- := + + # S3C2400 support files ++obj-$(CONFIG_CPU_S3C2400) += s3c2400.o ++obj-$(CONFIG_CPU_S3C2400) += s3c2400-irq.o + obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o + + # S3C2410 support files + +-obj-$(CONFIG_CPU_S3C2410) += s3c2410.o ++obj-$(CONFIG_CPU_S3C2410) += s3c2410.o irq.o + obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o + obj-$(CONFIG_S3C2410_DMA) += dma.o + +@@ -27,7 +29,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec. + # S3C2440 support + + obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o +-obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o ++obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o irq.o + obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o + obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o + +@@ -40,6 +42,7 @@ obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq + obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o + obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o + obj-$(CONFIG_ARCH_H1940) += mach-h1940.o ++obj-$(CONFIG_MACH_GP32) += mach-gp32.o + obj-$(CONFIG_MACH_N30) += mach-n30.o + obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o + obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o +diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile.boot linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile.boot +--- linux-2.6.16.60/arch/arm/mach-s3c2410/Makefile.boot 2008-01-27 17:58:41.000000000 +0100 ++++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/Makefile.boot 2010-02-18 01:13:59.467897060 +0100 +@@ -1,3 +1,7 @@ ++ifeq ($(CONFIG_CPU_S3C2400),y) ++ zreladdr-y := 0x0c008000 ++params_phys-y := 0x0c000100 ++else + zreladdr-y := 0x30008000 + params_phys-y := 0x30000100 +- ++endif +diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/devs.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/devs.c +--- linux-2.6.16.60/arch/arm/mach-s3c2410/devs.c 2008-01-27 17:58:41.000000000 +0100 ++++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/devs.c 2010-02-18 02:20:22.071894261 +0100 +@@ -273,11 +273,19 @@ static struct resource s3c_adc_resource[ + .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1, + .flags = IORESOURCE_MEM, + }, ++#ifdef CONFIG_CPU_S3C2400 ++ [1] = { ++ .start = IRQ_ADC, ++ .end = IRQ_ADC, ++ .flags = IORESOURCE_IRQ, ++ }, ++#else + [1] = { + .start = IRQ_TC, +- .end = IRQ_TC, ++ .end = IRQ_ADC, + .flags = IORESOURCE_IRQ, + }, ++#endif + [2] = { + .start = IRQ_ADC, + .end = IRQ_ADC, +diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/mach-gp32.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/mach-gp32.c +--- linux-2.6.16.60/arch/arm/mach-s3c2410/mach-gp32.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/mach-gp32.c 2010-02-18 01:19:10.259895346 +0100 +@@ -0,0 +1,108 @@ ++/* linux/arch/arm/mach-s3c2410/mach-gp32.c ++ * ++ * Copyright (c) 2006 Lucas Correia Villa Real ++ * ++ * http://sourceforge.net/projects/gp32linux ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Modifications: ++ * 15-Jan-2006 LCVR Created initial version ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "clock.h" ++#include "devs.h" ++#include "cpu.h" ++ ++static struct map_desc gp32_iodesc[] __initdata = { ++ /* dump ISA space somewhere unused */ ++ ++ { (u32)S3C24XX_VA_ISA_WORD, S3C2400_CS3, SZ_16M, MT_DEVICE }, ++ { (u32)S3C24XX_VA_ISA_BYTE, S3C2400_CS3, SZ_16M, MT_DEVICE }, ++ ++ /* the BOOT-ROM is assigned to the nGCS0 */ ++ ++ { GP32_VA_BOOT_ROM, S3C2400_CS0, SZ_16M, MT_DEVICE }, ++}; ++ ++#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK ++#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB ++#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE ++ ++static struct s3c2410_uartcfg gp32_uartcfgs[] = { ++ [0] = { ++ .hwport = 0, ++ .flags = 0, ++ .ucon = UCON, ++ .ulcon = ULCON, ++ .ufcon = UFCON, ++ }, ++ [1] = { ++ .hwport = 1, ++ .flags = 0, ++ .ucon = UCON, ++ .ulcon = ULCON, ++ .ufcon = UFCON, ++ } ++}; ++ ++/* GP32 devices */ ++ ++static struct platform_device *gp32_devices[] __initdata = { ++ &s3c_device_usb, ++ &s3c_device_usbgadget, ++ &s3c_device_lcd, ++ &s3c_device_wdt, ++ &s3c_device_i2c, ++ &s3c_device_iis, ++ &s3c_device_spi0, ++}; ++ ++static struct s3c24xx_board gp32_board __initdata = { ++ .devices = gp32_devices, ++ .devices_count = ARRAY_SIZE(gp32_devices), ++}; ++ ++ ++void __init gp32_map_io(void) ++{ ++ s3c24xx_init_io(gp32_iodesc, ARRAY_SIZE(gp32_iodesc)); ++ s3c24xx_init_clocks(0); ++ s3c24xx_init_uarts(gp32_uartcfgs, ARRAY_SIZE(gp32_uartcfgs)); ++ s3c24xx_set_board(&gp32_board); ++} ++ ++MACHINE_START(GP32, "GamePark GP32") ++ /* Maintainer: Lucas Correia Villa Real */ ++ .phys_io = S3C2400_PA_UART, ++ .io_pg_offst = ((u32)S3C24XX_VA_UART >> 18) & 0xfffc, ++ .boot_params = S3C2400_SDRAM_PA + 0x100, ++ .map_io = gp32_map_io, ++ .init_irq = s3c24xx_init_irq, ++ .timer = &s3c24xx_timer, ++MACHINE_END +diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400-irq.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400-irq.c +--- linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400-irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400-irq.c 2010-02-18 02:27:58.571895480 +0100 +@@ -0,0 +1,308 @@ ++/* linux/arch/arm/mach-s3c2410/s3c2400-irq.c ++ * ++ * Copyright (c) 2006 Lucas Correia Villa Real ++ * ++ * Based on mach-s3c2410/irq.c, ++ * Copyright (c) 2003,2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Changelog: ++ * ++ * 19-Jan-2006 Lucas Correia Villa Real ++ * First version, based on S3C2410 code ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#include "cpu.h" ++#include "pm.h" ++#include "irq.h" ++ ++ ++/* wakeup irq control */ ++ ++#ifdef CONFIG_PM ++ ++/* state for IRQs over sleep */ ++ ++/* default is to allow for EINT0..EINT7, and IRQ_RTC as wakeup sources ++ * ++ * set bit to 1 in allow bitfield to enable the wakeup settings on it ++*/ ++ ++unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xffL; ++unsigned long s3c_irqwake_intmask = 0xffffffffL; ++ ++static int ++s3c_irq_wake(unsigned int irqno, unsigned int state) ++{ ++ unsigned long irqbit = 1 << (irqno - IRQ_EINT0); ++ ++ if (!(s3c_irqwake_intallow & irqbit)) ++ return -ENOENT; ++ ++ printk(KERN_INFO "wake %s for irq %d\n", ++ state ? "enabled" : "disabled", irqno); ++ ++ if (!state) ++ s3c_irqwake_intmask |= irqbit; ++ else ++ s3c_irqwake_intmask &= ~irqbit; ++ ++ return 0; ++} ++ ++#else ++#define s3c_irq_wake NULL ++#endif ++ ++ ++static void ++s3c_irq_mask(unsigned int irqno) ++{ ++ unsigned long mask; ++ ++ irqno -= IRQ_EINT0; ++ ++ mask = __raw_readl(S3C2410_INTMSK); ++ mask |= 1UL << irqno; ++ __raw_writel(mask, S3C2410_INTMSK); ++} ++ ++static inline void ++s3c_irq_ack(unsigned int irqno) ++{ ++ unsigned long bitval = 1UL << (irqno - IRQ_EINT0); ++ ++ __raw_writel(bitval, S3C2410_SRCPND); ++ __raw_writel(bitval, S3C2410_INTPND); ++} ++ ++static inline void ++s3c_irq_maskack(unsigned int irqno) ++{ ++ unsigned long bitval = 1UL << (irqno - IRQ_EINT0); ++ unsigned long mask; ++ ++ mask = __raw_readl(S3C2410_INTMSK); ++ __raw_writel(mask|bitval, S3C2410_INTMSK); ++ ++ __raw_writel(bitval, S3C2410_SRCPND); ++ __raw_writel(bitval, S3C2410_INTPND); ++} ++ ++ ++static void ++s3c_irq_unmask(unsigned int irqno) ++{ ++ unsigned long mask; ++ ++ irqno -= IRQ_EINT0; ++ ++ mask = __raw_readl(S3C2410_INTMSK); ++ mask &= ~(1UL << irqno); ++ __raw_writel(mask, S3C2410_INTMSK); ++} ++ ++static struct irqchip s3c_irq_level_chip = { ++ .ack = s3c_irq_maskack, ++ .mask = s3c_irq_mask, ++ .unmask = s3c_irq_unmask, ++ .set_wake = s3c_irq_wake ++}; ++ ++static struct irqchip s3c_irq_chip = { ++ .ack = s3c_irq_ack, ++ .mask = s3c_irq_mask, ++ .unmask = s3c_irq_unmask, ++ .set_wake = s3c_irq_wake ++}; ++ ++ ++static int ++s3c_irqext_type(unsigned int irq, unsigned int type) ++{ ++ unsigned long gpcon_offset, extint_offset; ++ unsigned long newvalue = 0, value; ++ ++ if ((irq < IRQ_EINT0) || (irq > IRQ_EINT7)) ++ return -1; ++ ++ gpcon_offset = (irq - IRQ_EINT0) * 2; ++ extint_offset = (irq - IRQ_EINT0) * 4; ++ ++ /* Set the GPIO to external interrupt mode */ ++ value = __raw_readl(S3C2400_GPECON); ++ value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); ++ __raw_writel(value, S3C2400_GPECON); ++ ++ /* Set the external interrupt to pointed trigger type */ ++ switch (type) ++ { ++ case IRQT_NOEDGE: ++ printk(KERN_WARNING "No edge setting!\n"); ++ break; ++ ++ case IRQT_RISING: ++ newvalue = S3C2410_EXTINT_RISEEDGE; ++ break; ++ ++ case IRQT_FALLING: ++ newvalue = S3C2410_EXTINT_FALLEDGE; ++ break; ++ ++ case IRQT_BOTHEDGE: ++ newvalue = S3C2410_EXTINT_BOTHEDGE; ++ break; ++ ++ case IRQT_LOW: ++ newvalue = S3C2410_EXTINT_LOWLEV; ++ break; ++ ++ case IRQT_HIGH: ++ newvalue = S3C2410_EXTINT_HILEV; ++ break; ++ ++ default: ++ printk(KERN_ERR "No such irq type %d", type); ++ return -1; ++ } ++ ++ value = __raw_readl(S3C2400_EXTINT0); ++ value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); ++ __raw_writel(value, S3C2400_EXTINT0); ++ ++ return 0; ++} ++ ++static struct irqchip s3c_irq_eint = { ++ .ack = s3c_irq_ack, ++ .mask = s3c_irq_mask, ++ .unmask = s3c_irq_unmask, ++ .set_wake = s3c_irq_wake, ++ .set_type = s3c_irqext_type, ++}; ++ ++ ++/* s3c24xx_init_irq ++ * ++ * Initialise S3C2400 IRQ system ++*/ ++ ++void __init s3c24xx_init_irq(void) ++{ ++ unsigned long pend; ++ unsigned long last; ++ int irqno, uart_irq[3]; ++ int i; ++ ++ irqdbf("s3c24xx_init_irq: clearing interrupt status flags\n"); ++ ++ /* first, clear all interrupts pending... */ ++ ++ last = 0; ++ for (i = 0; i < 4; i++) { ++ pend = __raw_readl(S3C2410_INTPND); ++ ++ if (pend == 0 || pend == last) ++ break; ++ ++ __raw_writel(pend, S3C2410_SRCPND); ++ __raw_writel(pend, S3C2410_INTPND); ++ printk("irq: clearing pending status %08x\n", (int)pend); ++ last = pend; ++ } ++ ++ /* register the main interrupts */ ++ ++ irqdbf("s3c24xx_init_irq: registering s3c2400 interrupt handlers\n"); ++ ++ for (irqno = IRQ_TICK; irqno <= IRQ_ADCPARENT; irqno++) { ++ /* set all the s3c2400 internal irqs */ ++ ++ switch (irqno) { ++ /* deal with the special IRQs (cascaded) */ ++ ++ case IRQ_UTXD0: ++ case IRQ_UTXD1: ++ case IRQ_URXD0: ++ case IRQ_URXD1: ++ case IRQ_UERR01: ++ case IRQ_ADCPARENT: ++ set_irq_chip(irqno, &s3c_irq_level_chip); ++ set_irq_handler(irqno, do_level_IRQ); ++ break; ++ ++ case IRQ_RESERVED6: ++ case IRQ_RESERVED16: ++ /* no IRQ here */ ++ break; ++ ++ default: ++ //irqdbf("registering irq %d (s3c irq)\n", irqno); ++ set_irq_chip(irqno, &s3c_irq_chip); ++ set_irq_handler(irqno, do_edge_IRQ); ++ set_irq_flags(irqno, IRQF_VALID); ++ } ++ } ++ ++ /* external interrupts */ ++ ++ for (irqno = IRQ_EINT0; irqno <= IRQ_EINT7; irqno++) { ++ irqdbf("registering irq %d (ext int)\n", irqno); ++ set_irq_chip(irqno, &s3c_irq_eint); ++ set_irq_handler(irqno, do_edge_IRQ); ++ set_irq_flags(irqno, IRQF_VALID); ++ } ++ ++ /* register the uart interrupts */ ++ ++ uart_irq[0] = IRQ_URXD0; ++ uart_irq[1] = IRQ_UTXD0; ++ uart_irq[2] = IRQ_UERR01; ++ for (i = 0; i < 3; i++) { ++ irqdbf("registering irq %d (s3c uart0 irq)\n", uart_irq[i]); ++ set_irq_chip(uart_irq[i], &s3c_irq_chip); ++ set_irq_handler(uart_irq[i], do_level_IRQ); ++ set_irq_flags(uart_irq[i], IRQF_VALID); ++ } ++ ++ uart_irq[0] = IRQ_URXD1; ++ uart_irq[1] = IRQ_UTXD1; ++ for (i = 0; i < 2; i++) { ++ irqdbf("registering irq %d (s3c uart1 irq)\n", uart_irq[i]); ++ set_irq_chip(uart_irq[i], &s3c_irq_chip); ++ set_irq_handler(uart_irq[i], do_level_IRQ); ++ set_irq_flags(uart_irq[i], IRQF_VALID); ++ } ++ ++ irqdbf("s3c2400: registered interrupt handlers\n"); ++} +diff -purN linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400.c linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400.c +--- linux-2.6.16.60/arch/arm/mach-s3c2410/s3c2400.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.16.60-gp32/arch/arm/mach-s3c2410/s3c2400.c 2010-02-18 01:13:59.467897060 +0100 +@@ -0,0 +1,167 @@ ++/* linux/arch/arm/mach-s3c2410/s3c2400.c ++ * ++ * Copyright (c) 2003-2006 Simtec Electronics ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Modifications: ++ * 15-Jan-2006 LCVR First version, based on s3c2410.c ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "s3c2400.h" ++#include "cpu.h" ++#include "clock.h" ++ ++/* Initial IO mappings */ ++ ++static struct map_desc s3c2400_iodesc[] __initdata = { ++ IODESC_ENT(USBHOST), ++ IODESC_ENT(USBDEV), ++ IODESC_ENT(CLKPWR), ++ IODESC_ENT(LCD), ++ IODESC_ENT(TIMER), ++ IODESC_ENT(ADC), ++ IODESC_ENT(WATCHDOG) ++}; ++ ++static struct resource s3c_uart0_resource[] = { ++ [0] = { ++ .start = S3C2410_PA_UART0, ++ .end = S3C2410_PA_UART0 + 0x3fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX0, ++ .end = IRQ_S3CUART_ERR0, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++static struct resource s3c_uart1_resource[] = { ++ [0] = { ++ .start = S3C2410_PA_UART1, ++ .end = S3C2410_PA_UART1 + 0x3fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX1, ++ .end = IRQ_S3CUART_ERR1, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++/* our uart devices */ ++ ++static struct platform_device s3c_uart0 = { ++ .name = "s3c2400-uart", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(s3c_uart0_resource), ++ .resource = s3c_uart0_resource, ++}; ++ ++ ++static struct platform_device s3c_uart1 = { ++ .name = "s3c2400-uart", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(s3c_uart1_resource), ++ .resource = s3c_uart1_resource, ++}; ++ ++static struct platform_device *uart_devices[] __initdata = { ++ &s3c_uart0, ++ &s3c_uart1 ++}; ++ ++static int s3c2400_uart_count = 0; ++ ++/* uart registration process */ ++ ++void __init s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no) ++{ ++ struct platform_device *platdev; ++ int uart; ++ ++ for (uart = 0; uart < no; uart++, cfg++) { ++ platdev = uart_devices[cfg->hwport]; ++ ++ s3c24xx_uart_devs[uart] = platdev; ++ platdev->dev.platform_data = cfg; ++ } ++ ++ s3c2400_uart_count = uart; ++} ++ ++/* s3c2400_map_io ++ * ++ * register the standard cpu IO areas, and any passed in from the ++ * machine specific initialisation. ++*/ ++ ++void __init s3c2400_map_io(struct map_desc *mach_desc, int mach_size) ++{ ++ /* register our io-tables */ ++ ++ iotable_init(s3c2400_iodesc, ARRAY_SIZE(s3c2400_iodesc)); ++ iotable_init(mach_desc, mach_size); ++} ++ ++void __init s3c2400_init_clocks(int xtal) ++{ ++ unsigned long tmp; ++ unsigned long fclk; ++ unsigned long hclk; ++ unsigned long pclk; ++ ++ /* now we've got our machine bits initialised, work out what ++ * clocks we've got */ ++ ++ fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); ++ ++ tmp = __raw_readl(S3C2410_CLKDIVN); ++ ++ /* work out clock scalings */ ++ ++ hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1); ++ pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1); ++ ++ /* print brieft summary of clocks, etc */ ++ ++ printk("S3C2400: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", ++ print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); ++ ++ /* initialise the clocks here, to allow other things like the ++ * console to use them ++ */ ++ ++ s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); ++} ++ ++int __init s3c2400_init(void) ++{ ++ printk("S3C2400: Initialising architecture\n"); ++ ++ return platform_add_devices(s3c24xx_uart_devs, s3c2400_uart_count); ++} +diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/entry-macro.S linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/entry-macro.S +--- linux-2.6.16.60/include/asm-arm/arch-s3c2410/entry-macro.S 2008-01-27 17:58:41.000000000 +0100 ++++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/entry-macro.S 2010-02-18 01:19:18.503894425 +0100 +@@ -9,6 +9,7 @@ + + * Modifications: + * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA ++ * 19-Jan-2006 LCVR Added support to S3C2400 + */ + #include + #include +@@ -19,10 +20,11 @@ + mov \tmp, #S3C24XX_VA_IRQ + ldr \irqnr, [ \tmp, #0x14 ] @ get irq no + 30000: ++#ifndef CONFIG_CPU_S3C2400 + teq \irqnr, #4 + teqne \irqnr, #5 + beq 1002f @ external irq reg +- ++#endif + @ debug check to see if interrupt reported is the same + @ as the offset.... + +@@ -97,6 +99,7 @@ + mov \irqnr, #IRQ_EINT4 @ start extint nos + mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits + 10021: ++#ifndef CONFIG_CPU_S3C2400 + movs \irqstat, \irqstat, lsr#1 + bcs 1004f + add \irqnr, \irqnr, #1 +@@ -105,6 +108,7 @@ + + @ found no interrupt, set Z flag and leave + movs \irqnr, #0 ++#endif + + 1004: @ ensure Z flag clear in case our MOVS shifted out the last bit + teq \irqnr, #0 +diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/gp32-map.h linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/gp32-map.h +--- linux-2.6.16.60/include/asm-arm/arch-s3c2410/gp32-map.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/gp32-map.h 2010-02-18 01:19:10.259895346 +0100 +@@ -0,0 +1,23 @@ ++/* linux/include/asm-arm/arch-s3c2410/gp32-map.h ++ * ++ * Copyright (c) 2005 Lucas Correia Villa Real ++ * ++ * Machine GP32 - Memory map definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++/* needs arch/map.h including with this */ ++ ++#ifndef __ASM_ARCH_GP32MAP_H ++#define __ASM_ARCH_GP32MAP_H ++ ++#define GP32_IOADDR(x) (0xC0000000 + (x)) ++ ++/* maps the BOOT ROM, which is connected to nGCS0 */ ++#define GP32_VA_BOOT_ROM GP32_IOADDR(0x00000000) ++ ++#endif /* __ASM_ARCH_GP32MAP_H */ +diff -purN linux-2.6.16.60/include/asm-arm/arch-s3c2410/irqs.h linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/irqs.h +--- linux-2.6.16.60/include/asm-arm/arch-s3c2410/irqs.h 2008-01-27 17:58:41.000000000 +0100 ++++ linux-2.6.16.60-gp32/include/asm-arm/arch-s3c2410/irqs.h 2010-02-18 01:19:18.503894425 +0100 +@@ -13,6 +13,7 @@ + * 12-Mar-2004 BJD Fixed bug in header protection + * 10-Feb-2005 BJD Added camera IRQ from guillaume.gourat@nexvision.tv + * 28-Feb-2005 BJD Updated s3c2440 IRQs ++ * 19-Jan-2006 LCVR Added S3C2400 definitions + */ + + +@@ -48,24 +49,53 @@ + #define IRQ_TIMER3 S3C2410_IRQ(13) + #define IRQ_TIMER4 S3C2410_IRQ(14) + #define IRQ_UART2 S3C2410_IRQ(15) ++#define IRQ_UERR01 S3C2410_IRQ(15) /* for s3c2400 */ + #define IRQ_LCD S3C2410_IRQ(16) /* 32 */ ++#define IRQ_RESERVED16 S3C2410_IRQ(16) /* for s3c2400 */ + #define IRQ_DMA0 S3C2410_IRQ(17) + #define IRQ_DMA1 S3C2410_IRQ(18) + #define IRQ_DMA2 S3C2410_IRQ(19) + #define IRQ_DMA3 S3C2410_IRQ(20) + #define IRQ_SDI S3C2410_IRQ(21) +-#define IRQ_SPI0 S3C2410_IRQ(22) ++#define IRQ_MMC S3C2410_IRQ(21) /* for s3c2400 */ ++#define IRQ_SPI0 S3C2410_IRQ(22) /* s3c2400 has only 1 SPI */ + #define IRQ_UART1 S3C2410_IRQ(23) ++#define IRQ_URXD0 S3C2410_IRQ(23) /* for s3c2400 */ ++#define IRQ_URXD1 S3C2410_IRQ(24) /* for s3c2400 */ + #define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ + #define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ + #define IRQ_USBD S3C2410_IRQ(25) + #define IRQ_USBH S3C2410_IRQ(26) + #define IRQ_IIC S3C2410_IRQ(27) + #define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ ++#define IRQ_UTXD0 S3C2410_IRQ(28) /* for s3c2400 */ ++#define IRQ_UTXD1 S3C2410_IRQ(29) /* for s3c2400 */ + #define IRQ_SPI1 S3C2410_IRQ(29) + #define IRQ_RTC S3C2410_IRQ(30) + #define IRQ_ADCPARENT S3C2410_IRQ(31) + ++#ifdef CONFIG_CPU_S3C2400 ++ ++/* interrupts generated from the external interrupts sources */ ++#define IRQ_EINT4 S3C2410_IRQ(4) ++#define IRQ_EINT5 S3C2410_IRQ(5) ++#define IRQ_EINT6 S3C2410_IRQ(6) ++#define IRQ_EINT7 S3C2410_IRQ(7) ++#define IRQ_ADC S3C2410_IRQ(31) ++ ++/* aliases to keep compatibility with S3C2410 code */ ++#define IRQ_S3CUART_RX0 IRQ_URXD0 ++#define IRQ_S3CUART_TX0 IRQ_UTXD0 ++#define IRQ_S3CUART_ERR0 IRQ_UERR01 ++ ++#define IRQ_S3CUART_RX1 IRQ_URXD1 ++#define IRQ_S3CUART_TX1 IRQ_UTXD1 ++#define IRQ_S3CUART_ERR1 IRQ_UERR01 ++ ++#define NR_IRQS (IRQ_ADC+1) ++ ++#else ++ + /* interrupts generated from the external interrupts sources */ + #define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ + #define IRQ_EINT5 S3C2410_IRQ(33) +@@ -122,5 +152,6 @@ + + #define NR_IRQS (IRQ_S3C2440_AC97+1) + ++#endif /* CONFIG_CPU_S3C2400 */ + + #endif /* __ASM_ARCH_IRQ_H */ -- 2.26.2